Reference Signal Generating Method and Circuit for Differential Evaluation of the Content of Nonvolatile Memory Cells

The present invention relates to a reference signal generating method and circuit for differential evaluation of the content of nonvolatile memory, in particular flash-EEPROM memory, cells.

As is known, comparison reading of the content of a memory cell is performed by comparing a quantity related to the current through the cell to be read with a similar electric quantity related to the current through a reference cell whose content is known. In the case of flash-EEPROM arrays, a similar comparison is frequently also made after erasing the array or part of it, to verify correct erasure and, if necessary, complete the erasure.

According to one solution widely used at present, to safely distinguish between an erased cell and a written cell, the reference cell, when biased to a predetermined read voltage, generates a reference current of a value between that of an erased cell and a written cell. For this purpose, an erased reference cell with a threshold equal to the typical threshold is used, and the reference cell circuitry is so designed that the I-V characteristic (I.sub.DS -V.sub.GS) of the reference cell has a lower slope than that of the array cells. In the above solution, the minimum evaluation (read or verify) voltage is the value at which the current in the erased cell having the maximum permissible threshold is nevertheless higher than the current in the reference cell. This concept is illustrated in FIG. 1 which shows the typical I-V characteristic of a UV, i.e., UV erased, array cell whose threshold depends solely on the fabrication process (curve A); the characteristic of the erased cell with the maximum permissible threshold (curve B); the characteristic of the reference cell (curve C); and the erase-verify voltage (line D), i.e. , the voltage at which erase testing is performed to determine correct erasure of the cells (at the erase-verify voltage, cells with a current I.sub.ds greater than the corresponding reference cell are considered erased). As can be seen, the erase-verify voltage, 3.2 V, is slightly higher than the value at which the characteristic of the erased cell with the maximum threshold intersects the reference characteristic.

According to the above known solution, the erase-verify voltage also represents the minimum read voltage and hence the minimum supply voltage of the memory (which, for economy, is made equal to the read voltage). In the typical case shown, wherein the erased cell and the reference cell both have a 2 V threshold and the erase-verify voltage equals 3.2 V, the maximum-threshold erased cell has a threshold voltage of 2.5 V, and the minimum supply voltage also equals 3.2 V.

On the other hand, current demand is for a reduction in supply voltage as much as possible, to extend application of this type of memory to portable equipment and others requiring low-power consumption.

A reduction in supply voltage, however, cannot be achieved by simply reducing the erase-verify voltage (and hence shifting to the left the characteristic of the erased cell with the maximum permissible threshold), as this would also result in a leftward shift (towards lower values) of the bell describing the threshold voltage distribution of the array cells when erased. Leftward shifting of the bell would also result in the threshold of the more erased cells (left limit of the bell) being brought too close to zero or even to a negative value, thus resulting in depleted cells, i.e., cells which conduct current even when V.sub.GS =0, and which would therefore be read even when not addressed, thus impairing the accuracy of the reading.

Provision must also be made for eliminating as much as possible the presence of cells not yet depleted but with a very low threshold (ranging between 0 and 1 V) which may be subject to hole injection during subsequent programming, thus impairing the oxide layer and hence the reliability of the array.

To at least partially solve the problem of depleted or very low threshold cells, processes are currently employed for recovering the depleted cells. In addition to increasing actual erasing time, however, reducing erase-verify voltage also increases the time it takes to recover the depleted cells, thus considerably increasing erasing time as a whole and reducing the speed of the memory.

It is an object of the present invention to provide a method and circuit permitting a reduction in supply voltage, without impairing reading or erase verify of the array cells or the reliability of the array itself.

According to the present invention, there are provided a reference signal generating method and circuit for differential evaluation of the content of nonvolatile memory cells, as claimed respectively in claims 1 and 7.

FIG. 1 shows the plot of the characteristics used for evaluating memory cells according to a known method.

FIG. 2 shows a similar plot of the characteristics used for evaluating memory cells according to a first embodiment of the present invention.

FIG. 3 shows a similar plot according to a second embodiment of the present invention.

FIG. 4 shows a reference signal generating circuit in accordance with the present invention and corresponding to the FIG. 3 diagram.

FIG. 5 shows a plot of a number of characteristics obtainable as a function of supply voltage at predetermined points of the FIG. 4 circuit.

FIG. 2 plot shows the I-V characteristic of the read and erase-verify reference voltage according to a first embodiment of the present invention. As shown in FIG. 2, the reference characteristic generated by the reference branch of the array is shifted with respect to the corresponding currently used characteristic (curve C in FIG. 1) so that its threshold (voltage at which current I.sub.ds is zero) is higher or at least the same as that of the erased cell with the maximum permissible threshold (curve B). For comparison purposes, FIG. 2 also shows the characteristic A of a typical UV erased cell.

Generation of reference characteristic E provides for reading and verifying the memory cells at a lower voltage as compared with known solutions, and hence for designing memories with a lower supply voltage.

For example, assuming the threshold of the erased cell with the maximum permissible threshold is 2.5 V and the read circuit is so designed that the reference cell threshold is also 2.5 V, even allowing for uncertainty as to the supply voltage (+10%), it is possible to work with a nominal supply voltage of no more than 3 V. Even in the event the supply voltage is the minimum permissible (2.7 V), the current through the reference cell at read voltage is lower than the current through any of the erased cells (including those with a maximum threshold, corresponding to characteristic B) and higher than the current through any of the written cells (characteristic F in FIG. 2).

Referring to FIG. 3, a second embodiment of the present invention is disclosed. For safer reading--in view of the narrow margin in the FIG. 2 solution between the threshold of the erased cell with the maximum permissible threshold and the minimum read voltage (200 mV, between 2.5 and 2.7 V)--the maximum threshold of the erased cells is reduced slightly, e.g., by 200 mV, to 2.3 V. Though this shifts the overall threshold distribution bell by 200 mV, the threshold reduction is so small as to bring about only a negligible impairment in terms of the percentage of depleted or predepleted cells (with a threshold of 0 to 1 V).

Moreover, an erase-verify reference characteristic (G in FIG. 3) substantially similar to that of a maximum-threshold erased cell (maximum erased cell characteristic) is provided. According to the above solution, therefore, the erase-verify reference characteristic no longer coincides with the read reference characteristic.

According to another embodiment of the present invention, the read reference characteristic H is no longer represented by a single straight line, but by a broken line formed of two segments: a first segment H1 extending between the x axis and a predetermined voltage V.sub.S (e.g., supply voltage V.sub.CC); and a second segment H2 extending from the voltage V.sub.S. More specifically, the first segment has a slope equal to a fraction of that of the array cell characteristics (e.g., 2/5, as in known characteristic C of FIG. 1); and the second segment has a slope equal to that of the array cell characteristics. The read reference characteristic according to the above embodiment is indicated by H in FIG. 3, and comprises a first segment H1 and a second segment H2.

By virtue of being divided into two segments, read reference characteristic H is in no danger of intersecting the characteristic of a written cell (F in FIG. 2) even in the event of a high read or supply voltage. This therefore eliminates the need to reduce the maximum supply voltage of those devices that do not require low read voltage for reasons of economy and in which a high read voltage (e.g., a nominal voltage of over 5 V) is preferable. In fact, without the above change in slope (characteristic E in FIG. 2), the maximum read voltage (and hence supply voltage) must be kept below that at which the read reference characteristic and the characteristic of the least written cell intersect.

One embodiment of a circuit for generating the read and erase-verify reference characteristics of FIG. 3 is shown in FIG. 4 and described below.

In FIG. 4, the generating circuit is indicated as a whole by 10 and comprises three flash type virgin cells 11, 12, 13 external to the memory array. Cells 11-13, which themselves have a threshold of 2 V, are so biased as to present a characteristic shifted with respect to the typical characteristic of a virgin cell, which bias is achieved by means of voltage shift elements 14 and 15 supplied at the input with supply voltage V.sub.CC and supplying a shifted voltage at the output. More specifically, voltage shifter 14 has an output 14a connected to the gate terminal of cell 11 and supplies a shifted voltage of, for example, 1 V, so that the gate-source voltage drop V.sub.GS11 of cell 11 equals V.sub.CC -1 V, and cell 11 has a threshold of 3 V (supply voltage value at which cell 11 begins conducting). Voltage shifter 15 in turn has an output 15a connected to the gate terminals of cells 12 and 13 and supplies a shifted voltage of, say, 300 mV, so that the gate-source voltage drop (V.sub.GS12, V.sub.GS13) of cells 12 and 13 equals V.sub.CC -0.3 V, and cells 12, 13 both have a threshold of 2.3 V.

Cell 11 is connected to a precharge circuit 17 and a load transistor 18. Precharge circuit 17, of known type, comprises an N-channel MOS transistor 19 with the source terminal connected to the drain terminal of cell 11, the gate terminal connected to the output of an inverter 20, and the drain terminal connected to transistor 18. The input of inverter 20 is connected to the source terminal of transistor 19 to bias the drain terminal of cell 11 to a fixed voltage, e.g., 1 V, in known manner.

Between precharge circuit 17 and load transistor 18, there is inserted a switch 21 formed by a P-channel MOS transistor supplied at the gate terminal with a logic signal R for enabling cell 11 in read mode.

Load transistor 18 is a diode-connected PMOS type with the source terminal connected to V.sub.CC supply line 16, and the drain terminal connected to transistor 21. Transistor 18 is a resistive type with a size (width/length) ratio W/L of, for example, 10/2, and forms part of a current mirror circuit 22 including another P-channel MOS transistor 23 of the same size as transistor 18. Transistor 23 has the source terminal connected to supply line 16, the gate terminal connected to the gate terminal of transistor 18, and the drain terminal connected to the source terminal of a PMOS type transistor 26 operating as a switch whose gate terminal is supplied with logic signal R, and whose drain terminal is connected to a node 27.

Node 27 is connected to the drain terminal of cell 12 via a precharge circuit 28 similar to circuit 17 and therefore is not described in detail. The source terminal of cell 12 is grounded, and node 27 is also connected to the drain terminal of a PMOS type switch transistor 29, the gate terminal of which is supplied with logic signal R, and the source terminal of which is connected to the drain terminal of a resistive type load transistor 30 forming part of a second current mirror circuit 31. More specifically, P type MOS transistor 30 is diode-connected, has the source terminal connected to supply line 16, has a smaller W/L ratio than transistors 18, 23, e.g., 10/4, and is therefore more resistive than transistors 18, 23, as explained hereinbelow.

Current mirror circuit 31 also comprises a PMOS transistor 32 of the same size as transistor 30, and with the source terminal connected to supply line 16, the gate terminal connected to the gate terminal of transistor 30, and the drain terminal connected to the source terminal of a PMOS switch transistor 33, the gate terminal of which is supplied with logic signal R, and the drain terminal of which is connected to a precharge circuit 34 similar to circuits 17 and 28.

Precharge circuit 34 is interposed between switch transistor 33 and a node 37 which is also connected to the drain terminal of cell 13, the source terminal of which is grounded.

Node 37 is also connected to a read reference node 38 via a precharge circuit 39 similar to circuits 17, 28, 34; and node 38 is connected to supply line 16 via a switch transistor 40 and a load transistor 41. More specifically, switch transistor 40 is a PMOS type supplied with logic signal R at the gate terminal; and load transistor 41 is a resistive PMOS type with the same size ratio as transistors 18, 23, e.g., 10/2. Transistor 41 is diode-connected, and has the drain terminal connected to switch 40 and to its own gate terminal, the source terminal connected to line 16, and the gate terminal connected to node 27 via a PMOS type switch transistor 42, the gate terminal of which is supplied with a logic erase-verify enabling signal V.

FIG. 4 also shows a branch of a memory array 48 and the comparators for comparing the array data and reference data. More specifically, the memory array 48 shows a cell 50 with a grounded source terminal, the gate terminal supplied with a bias voltage GV, and the drain terminal connected to a node 51 via a precharge circuit 52 similar to circuit 17. Node 51 is connected to supply line 16 via a switch transistor 53 and a load transistor 54 similar in size to elements 40, 41 of the reference portion of the circuit. Unlike transistor 40, however, switch transistor 53 has a grounded gate terminal so that it is always on (closed switch).

Reference node 38 and array node 51 are connected to respective inputs of a first comparator 55 for comparing the voltages at said nodes in read mode, which voltages depend in known manner on the currents through reference cell 13 and memory cell 50.

Reference node 27 and array node 51 are connected to respective inputs of a second comparator 56 for comparing the voltages at said nodes in erase-verify mode.

Operation of the FIG. 4 circuit will now be described with reference also to FIG. 5 which, as circuit 10 may be used for memory arrays operating at various supply voltages, shows the characteristics of the major circuit nodes as a function of supply voltage.

As already stated, by virtue of voltage shifters 14 and 15, cells 11, 12, 13 have lower gate-source voltages V.sub.GS with respect to supply voltage, but their characteristic also depends on the working load as will be explained hereinbelow wherein I.sub.1 is the current through load transistor 18 (and cell 11), I.sub.2 the current through mirror transistor 23, I.sub.3R the current through cell 12 in read mode, I.sub.3V the current through cell 12 in erase-verify mode, I.sub.4 the current through load transistor 30, I.sub.5 the current through mirror transistor 32, I.sub.6 the current through cell 13, and I.sub.7 the current through load transistor 41.

In read mode, logic signal R is low and logic signal V high, so that switches 21, 26, 29, 33, 40 are closed (transistors on), switch 42 is open, and, as long as supply voltage V.sub.CC is below 2.3 V, cells 11, 12, 13 are off (V.sub.GS11 <1.3 V, V.sub.GS12 =V.sub.GS13 <2 V). Upon supply voltage exceeding 2.3 V, cells 12 and 13 begin conducting, but their characteristic presents a less than typical slope due to the loads being present. In the 2.3 to 3 V supply voltage range, cell 11 is off, I.sub.1 and hence I.sub.2 are zero, and cell 12 only conducts the current supplied by load transistor 30 which, being highly resistive, limits the supplied current. More specifically, with the above sizing, the slope of characteristic I.sub.3R (shown by I.sub.3R in FIG. 5) is roughly half that of the intrinsic characteristic of cells 11-13 (shown by I.sub.v in FIG. 5), so that I.sub.4 =I.sub.3R and I.sub.5 =I.sub.4 due to transistors 30, 32 forming a 1:1 mirror.

Within the same supply voltage range, current I.sub.6 through cell 13 has the intrinsic curve characteristic, as shown in FIG. 5, because current through the cell 13 is being supplied by both load transistors 32 and 41; and current I.sub.7 through load transistor 41, the value of which equals I.sub.6 -I.sub.5, has a slope equal to half the intrinsic slope of cells 11, 12, 13, as shown in FIG. 5.

With a supply voltage of over 3 V, circuit 10 operates differently. Cell 11 is now turned on by having a V.sub.GS voltage of over 2 V, and draws a current I.sub.1 with the curve as shown in FIG. 5, i.e. , with a 3 V threshold and the same slope as a virgin cell with no current limitation (I.sub.v). Due to the 1:1 ratio of mirror 22, I.sub.2 =I.sub.1, and at this point the current through cell 12 is no longer limited by the high resistivity of load transistor 30 by virtue of cell 12 also seeing load transistor 23. Consequently, current I.sub.3R increases alongside the supply voltage with a slope equal to the intrinsic slope, and I.sub.4 (the value of which equals I.sub.3R -I.sub.2) presents a constant curve, as does I.sub.5 which equals I.sub.4.

Current I.sub.6 maintains the curve governed by the shifted characteristic of cell 13, while I.sub.7, the value of which still equals I.sub.6 -I.sub.5, in this case presents the same slope as a virgin cell.

In the example shown, I.sub.3R =I.sub.7 due to the specific sizing of load transistors 18, 23, 30, 32, 41, though in general this does not occur.

In known manner, the voltages at nodes 38 and 51 depend solely on currents I.sub.7 and I.sub.M (the current in cell 50 with characteristic A or F in FIG. 2, depending on whether cell 50 is erased or written) and may therefore be compared directly to safely determine the state of cell 50 even in the presence of low supply voltages.

Conversely, in erase-verify mode, logic signal R is high and signal V low, so that switches 21, 26, 29, 33, 40 are open and switch 42 closed, thus connecting node 27 directly to the drain terminal of load transistor 41.

In this mode, cell 12 operates like a virgin cell with a shifted characteristic (2.3 V threshold) and unlimited slope (in this mode, at any work point, cell 12 sees the same load 41), so that the characteristic of cell 12 (I.sub.3V) coincides with characteristic I.sub.6 in FIG. 5.

As such, comparator 56 may compare the voltage at node 27 (again related solely to current I.sub.3V) with the voltage at node 51 to determine whether cell 50 is sufficiently erased.

The advantages of the method and circuit described are many. One advantage is that they provide for reading and erase-verifying the memory cells even in the presence of low supply voltage, in particular as low as a nominal voltage of 3 V; and, when the erase threshold is shifted slightly downwards, the method according to the invention provides for a good safety margin, thus ensuring highly reliable reading of the cells even with a low supply voltage.

Another advantage is that providing a read reference characteristic with two slopes--a lower slope in the low-voltage range followed by a higher slope--enables use of the same method and circuit for high-voltage storage devices as well, so that the same structure may be used for different applications, thus reducing design, fabrication and storage costs.

The circuit described is also extremely reliable. In particular, the use of virgin cells with a characteristic shifted by means of voltage shifters is especially advantageous, in that virgin cells provide for a high degree of even long-term precision and hence a high degree of stability of the circuit, unlike, for example, the use of even only partly written cells which, by their nature, tend eventually to discharge resulting in an unwanted intrinsic characteristic drift. Moreover, virgin cells present an intrinsically "safe" threshold involving no uncertainty (unlike, for example, erased cells which, as described above, present a statistic distribution of the threshold value). The use of virgin cells therefore eliminates or at least simplifies complex, high-cost matching of the reference cell threshold.

Clearly, changes may be made to the method and circuit as described and illustrated herein without, however, departing from the scope of the present invention. In particular, the circuit arrangement of the bias branches of cells 11-13 is purely indicative and may be modified in various respects. For example, as opposed to providing two comparators--one each for read and erase-verify--one comparator, e.g., 55, may be provided by connecting its reference input also to node 27 via a switch element. The sizes and voltage values are also purely indicative.

Finally, as opposed to using voltage shifters at the gate terminal of the reference cells for shifting the characteristic of the virgin memory cells, positive voltage offsets may be provided at the source terminals of the cells.