Electronic Circuit Breaker

The present invention is generally directed to electronic circuit breakers and similar devices for use in direct current systems. More particularly, the present invention is directed to a circuit breaker which provides a substantially constant impedance, as seen from the load, under varying load conditions. Additionally, the present circuit breaker is actuated by a combination of circuit conditions including not only current level but also current overload duration.

In large mainframe computer systems, there are typically provided a number of direct current power supply units. During routine maintenance situations, it often becomes necessary to turn off one or more banks of these power supply units. When mechanical circuit breakers are employed for this purpose, it is easily possible to turn off an incorrect circuit. Such activities often only compound problems which may exist. Additionally, for certain mechanical breakers, it is difficult to discern whether they are on, off, or have been tripped. Electronic circuit breakers do not necessarily exhibit these problems.

However, when a mechanical circuit breaker is replaced by an electronic circuit breaker, one must also be concerned with circuit behavior during varying load conditions which do not in fact result in overcurrent conditions and in particular do not result in overcurrent conditions which cause the circuit breaker to be "tripped". In particular, under conditions of varying load, when an electronic circuit breaker is employed, it is desirable to be able to provide a circuit which exhibits constant impedance properties as seen by the load, even under varying load conditions.

The use of an electronic circuit breaker would also provide important signal and control advantages. In particular, it would be desirable to have an electronic circuit breaker which could be addressed by name or by other designations from a computer keyboard or from another console device. Likewise it would be desirable to have information concerning the "on" or "off" status of the device being protected and/or indications to whether or not the circuit breaker has experienced a sufficiently large prior overcurrent condition to have caused an earlier fault interruption.

In accordance with a preferred embodiment of the present invention, an electronic circuit breaker comprises a current control means for connecting a load in series with a source of electrical current. There are also provided means to sense electrical current through the control means and also to sense voltage across the current control means. Additionally, there is provided an actuating means which causes the control means to interrupt the current to the load upon condition of excess current which is determined not only by the level of current but also by the duration of current overload as determined by a timing mechanism. Also, since what is provided is an electronic circuit breaker which is in series with a load which may experience power fluctuations, a mechanism is also provided to regulate the voltage across the control means as a function of the current through the control means so as to provide a substantially constant impedance, as seen by the load.

A preferred embodiment of the present invention is implemented in terms of a power MOSFET and a multi-loop control circuit. In particular, there is provided a voltage loop and a current loop. These multi-loop control circuit sensing means operate interactively with each other and cooperatively with a timing means to provide not only an appropriate mechanism for circuit interruption but also a-mechanism for simultaneously providing a constant impedance to the load.

Accordingly, it is an object of the present invention to provide an electronic circuit breaker.

More particularly, it is an object of the present invention to provide an electronic circuit breaker which may be controlled by logic level signals.

It is also an object of the present invention to provide circuit interruption means which depend not only on current level but also on current overload duration.

It is yet another object of the present invention to provide a circuit breaker which is electrically isolated with respect to its input and output logic signals.

It is a still further object of the present invention to provide a circuit breaker which exhibits a substantially constant impedance to the load.

It is also an object of the present invention to provide ease of maintenance and safety during servicing operations.

It is an additional object of the present invention to reduce the error prone aspects of interfacing with large panels of mechanical circuit breakers.

It is yet another object of the present invention to eliminate a human intervention at breaker panels, particularly when servicing a machine such as a large mainframe computer.

Lastly, but not limited hereto, it is an object of the present invention to reduce the inadvertent elimination of power across various boundaries in a large mainframe computer system and most particularly in those situations in which various units of these computer systems are operating independently of one another and which can maintain their running status when other portions of the system are either accidentally or deliberately shutdown for maintenance or other repairs.

The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of practice, together with the further objects and advantages thereof, may be best understood by reference to the following description taken in connection with the accompanying drawings in which:

FIG. 1 is an electrical schematic diagram illustrating a preferred embodiment of the present invention;

FIG. 2 is an electrical circuit diagram illustrating an input isolation circuit useable in conjunction with the circuit shown in FIG. 1;

FIG. 3 is an electrical circuit diagram illustrating an output isolation circuit which is particularly useable in conjunction with the circuit shown in FIG. 1; and

FIG. 4 is a partially schematic and partially block diagram view illustrating the major subsystems of the circuit shown in FIG. 2 and their relationships to one another.

The present invention may best be understood by reference to both FIGS. 1 and 4. FIG. 1 illustrates the total circuit employed in the present invention, while FIG. 4 provides a partially schematic and partially block view of the major components of the present and overall system. FIG. 4 provides a view of the various major components in the circuit interrupter of the present invention. In particular, it is noted that the present invention includes control means 10 (see FIG. 4). Control means 10 includes an N-channel power MOSFET Q.sub.1 which is connected in series with the load which is to be protected by the present invention. Q.sub.1 may also consist of one or more power control devices in parallel. The load current flows through Q.sub.1 through R.sub.s and fuse F.sub.1. The voltage drop across R.sub.s is used to provide a voltage input to differential amplifier A.sub.i1 (FIG. 1). It is seen that it is the voltage across R.sub.s which provides a voltage signal which is proportional to the load current. It is this voltage which drives the operation of current sensing circuit 30 (see FIG. 4). Power MOFSET Q.sub.1 is the mechanism used to control the current to the load. It is also the mechanism employed not only to interrupt this current but also to provide a constant impedance view as seen by the load under normally varying load conditions. In addition to current control means 10 and current level sensing means 30, FIGS. 1 and 4 also illustrate the presence of voltage level sensing means 20 whose input is derived directly from the voltage across Q.sub.1. It is noted in this regard that FET device Q.sub.7 normally operates in the on or conducting state, so that the voltage present at the drain of Q.sub.1 is available as an input to voltage sensing circuit 20.

Additionally reflected in FIG. 4 is the presence of timer means or timing mechanism 40. This timing mechanism operates by controlling the charging of capacitor C.sub.4 through resistor R.sub.6. This charging occurs as a function of the current level through Q.sub.1 in comparison with a reference voltage value. When the current level exceeds a predetermined value for a predetermined period of time, timer circuit 40 turns on transistor Q.sub.2 which is connected through resistor R.sub.14 to the gate of power MOFSET Q.sub.1. This provides a time dependent overcurrent control which operates to turn off Q.sub.1 during overcurrent load conditions.

However, in addition to providing to the timer a voltage which is proportional to the load current, current sensing means 30 also operates in conjunction with voltage sensing means 20 and actuating means 50 to provide control of transistor Q.sub.1 during normal circuit operation. For the purpose of clarity, it is noted herein that "normal circuit operation" refers to those times when load current is flowing through transistor Q.sub.1, or correspondingly, to those times when the current interruption aspect of the present invention is not being utilized.

In general, the flow of current through power MOFSET Q.sub.1 to the load is determined by a multiloop control circuit. During normal operation the load current is less than the breaker rating and the voltage control loop controls Q.sub.1. The voltage loop consists of operational amplifiers A.sub.v1 and A.sub.v2 together with their associated circuitry. The drain-to-source potential of Q.sub.1 is measured and amplified by operational amplifier A.sub.v1 and supplied to error amplifier, A.sub.v2 where it is compared to a variable reference voltage that is proportional to the load current. This variable reference voltage is proportional to the voltage across resistor R.sub.s. The output of error amplifier A.sub.v2 drives the gate of MOSFET Q.sub.1 through transistor Q.sub.8 which is a Darlington circuit which buffers the high input capacitance of Q.sub.1 from the error amplifier output. The voltage loop thus provides power MOFSET Q.sub.1 with sufficient gate drive to operate in the saturation region with low voltage drop (high efficiency) while eliminating excess gate charge which would cause high peak currents in the event of a load short.

Also relevant in the voltage control loop is the operation of transistor Q.sub.7. Transistor Q.sub.5 turns off transistor Q.sub.7 if timer circuit 40 times out. Timer circuit 40 also turns off transistor Q.sub.1 causing its drain voltage to rise until the entire supply voltage V.sub.cc is across its drain and source nodes. When this happens, transistor Q.sub.7 should be off to avoid damaging amplifier A.sub.v1 with large input voltages. The connection to transistor Q.sub.5 insures that transistor Q.sub.7 is turned off at the appropriate time to avoid this situation.

The second major control loop also includes a differential amplifier, namely amplifier A.sub.i1 and its associated error amplifier A.sub.i2. This second loop, the current control loop, provides load current interruption during fault conditions. The voltage across R.sub.s which is proportional to load current, is amplified by differential amplifier A.sub.i1. This amplified current signal is then used to provide an input for error amplifier A.sub.i2 as well as to provide a reference input for the voltage loop. Error amplifier A.sub.i2 compares the current signal to a fixed reference and controls MOSFET Q.sub.1 through buffer transistor circuit Q.sub.8. The voltage loop and the current loop both come together at the input of this buffer transistor Q.sub.8. The actual amplitude of the drive to the gate of Q.sub.1 cannot be higher than the current loop output, however, because diode CR.sub.1 does not allow the voltage loop to source current. Thus to maintain current limit control under fault conditions, the current loop is made to be dominant over the voltage loop. When the circuit breaker encounters limiting current conditions, a timer circuit including dual comparators A.sub.t1 and A.sub.t2 is activated. After a predetermined amount of time under limit current conditions, the breaker trips, and transistor Q.sub.1 is turned off. The allowable length of delay before tripping occurs is determined at design time by the power handling capacity of transistor Q.sub.1.

The reference voltage provided to amplifier A.sub.t1 in the timer subsystem is a voltage which is divided by resistors R.sub.4 and R.sub.18. This voltage is provided to timer mechanism 40 and is divided to make sure that noise variations do not continually trigger the unit. When capacitor C.sub.4 is charged, operational amplifier A.sub.t2 turns on, and through transistor Q.sub.2, causes the main power transistor Q.sub.1 to turn off. Resistor R.sub.21 in timer 40 provides a mechanism to limit the voltage since it is undesirable to have supply voltage V.sub.cc provided to the input of comparator A.sub.t2.

In current sensing means 30 capacitor C.sub.1, diodes CR.sub.5 and CR.sub.6, and operational amplifier A.sub.i2 function to regulate the current to a fixed level during fault conditions. This operational amplifier is therefore an error amplifier and operates when current is flowing normally.

In order to provide electrical isolation and also to provide signal level control and status indications for the present interrupter, input and output isolation circuits are provided as shown in FIGS. 2 and 3. In particular, both of these circuits employ opto-electrical isolation modules M1 and M2 (model number HCLP 2731 as supplied by Hewlett Packard). These devices typically employ light emitting diodes or other semiconductor devices optically connected to corresponding photo sensitive semiconductor diodes (or other devices) to provide electrical isolation. Additionally, it is seen that these electro-optical isolating units also employ Darlington transistor circuits as buffer devices, as shown in FIGS. 2 and 3. In particular, FIG. 2 shows optical isolator M.sub.1 where one of two input pairs is used to control whether or not the breaker is turned on or off. The other one of the input pairs is unused. The output of optical isolator module M.sub.1 is used to control the gate of small power FET device Q.sub.4 which switches voltage V.sub.cc to the other components of the circuit from BIAS supply. CR.sub.7 is preferably a precision Zener diode which provides the fixed voltage used by the current loop and the timer. R.sub.13 provides current for the Zener diode and C.sub.6 bypasses noise.

On the output side of the circuit, optoisolator module M.sub.2 provides electrical isolation between the circuit and several status indication signal lines. In particular, it is seen that the presence of a DC voltage across the load is indicated by current flowing through resistor R.sub.9 and diode CR.sub.8. Likewise, the other output signal line pair from optoisolator module M.sub.2 provides an over-current fault indicator. This signal is provided through transistor Q.sub.3 which is connected to the output of timer 40.

The regulation mechanism of the present invention, that is the control of the impedance as seen by the load, is effectuated by voltage comparison occurring in amplifier A.sub.v2 whose output is fed back through Darlington transistor Q.sub.8 and then through the gate of Q1 where the voltage is controlled in an analog fashion.

In a preferred embodiment of the present invention, the circuit design illustrated in FIGS. 1 through 3 is constructed using components having values as shown in Table I below:

From the above, it should therefore be appreciated that the circuit breaker of the present invention operates to electronically interrupt current to a circuit load when overcurrent conditions exceed a predetermined duration. It is also seen that the circuit of the present invention operates to provide a constant impedance as seen by the load during normal circuit operating conditions, including conditions of varying load. It should therefore be appreciated that the present invention achieves all of the objects stated above.

While the invention has been described in detail herein in accordance with certain preferred embodiments thereof, many modifications and changes therein may be effected by those skilled in the art. Accordingly, it is intended by the appended claims to cover all such modifications and changes as fall within the true spirit and scope of the invention.