Variable-Length Code Table and Variable-Length Coding Device

1. Field of the Invention

The present invention relates to a variable-length code table and a coding device for converting equal-length data, and in particular to a variable-length code table which is used in image compression processing for performing variable-length coding in a table look-up system as well as a variable-length coding device using the same.

2. Description of the Background Art

Image information contains a great quantity of information. For example, one frame (1/30 seconds) of television image requires image information of a quantity corresponding to that of test data for one copy of a book. Further, real time transmission is required for the image data in many cases, and it is very difficult to transmit in real time such a great quantity of information.

Accordingly, such a technique is used that image data is compressed prior to actual transmission, and the compressed data is transmitted and is expanded at a receiver side. Since this can reduce the quantity of transmitted signals, a larger quantity of information can be transmitted in the same time period via the same transmission path. Therefore, signal compression technique is very important in the field of image processing.

As a method for the above, there has been a so-called variable-length coding processing, according to which short codes are assigned to bit patterns frequently appearing in the image data to be transmitted and relatively long codes are assigned to less frequently appearing bit patterns. FIG. 1 shows an example of an image data compression processing device using such a variable-length coding processing. This device has been proposed in Japanese Patent Application No. 5-60335 (1993) by the same assignee as the present application. In this example, there is shown a processing diagram of the image compression using the coding system specified by the MPEG standard.

Referring to FIG. 1, image data ID to be compressed is supplied to a DCT (Discrete Cosine Transform) processing device 202 via a subtracter 200 and a selector 218. DCT processing device 202 converts the input signal into frequency components. The signal processed by DCT processing device 202 is further quantized by a quantizer 204. The quantization relatively reduces the components at a high-frequency region of the data converted into frequency components by the DCT processing. This does not cause remarkable reduction of the image quality for human eyes, and thus is performed for reducing the quantity of data to be transmitted by removing high-frequency components.

The quantized data (i.e., run length data) is supplied to a variable-length coding unit 206 which performs variable-length coding on the data. The coded data is output as compressed image data VD via a buffer 208.

An output of quantizer 204 is also supplied to an inverse quantizer 210 and an inverse DCT processing unit 212. Inverse quantizer 210 and inverse DCT processing unit 212 are provided for predicting motion which will be described later. An output of inverse DCT processing unit 212 is also supplied to an adder 214.

Image data ID is also supplied to a motion predicting unit 216. Motion predicting unit 216 predicts, for example, the motion of image between frames and transmits information related only to the moving image for flattening data and allowing further compression so as to reduce the transmission quantity. The data after processing of prediction is supplied to adder 214.

The output data of adder 214 is supplied to subtracter 200 and motion predicting unit 216 via a selector 220. Owing to selecting operation of selectors 218 and 220, image compression is performed taking the prediction of motion into account.

FIG. 2 is a schematic block diagram of variable-length coding unit 206 shown in FIG. 1. Referring to FIG. 2, run length data of, e.g., 8 bits supplied from quantizer 204 in FIG. 1 is converted into run data and level data by a run length converter 236. These data are equal-length data. The level data represents the level of run length data other than 0. The run data represents the number of data of 0 following the data other than 0. As described before, the high frequency component contains many 0's owing to the DCT processing and quantization. Therefore, compression can be performed efficiently using the run length conversion. The run data and level data are supplied to a data RAM (Random Access Memory) 238 for run length data, and are supplied to a run length data to variable-length code converting unit 240 after being converted into the form of (run, level). Run length data to variable-length code converting unit 240 converts the (run, level) data into variable-length codes for supplying the same to a multiplexer 242. Run length data to variable-length code converting unit 240 will be detailed later.

Meanwhile, control information including compression method and data size is supplied to a data RAM 232 for a header. Data which is read from header data RAM 232 using the above control information as an address is supplied to a header producing unit 234. Header producing unit 234 and run length data to variable-length code converting unit 240 supply control signals to data RAM 232 for header and data RAM 238 for run length data, and thereby read data therefrom, respectively.

Header producing unit 234 outputs the header of data, and run length data to variable-length code converting unit 240 outputs variable-length-coded data. Multiplexer 242 selects the output of header producing unit 234 and the output of run length data to variable-length code converting unit 240 in accordance with a select signal sent from a whole control circuit 230, and supplies the same to an FIFO buffer 244.

FIFO buffer 244 buffers the output of multiplexer 242 in the FIFO manner in response to the control signals sent from header producing unit 234 and run length data to variable-length code converting unit 240, and outputs the same in response to an output request signal sent from a parallel/serial (P/S) interface 246. FIFO buffer 244 is provided for making adjustment between a processing speed of variable-length coding unit 206 and a speed of external output of data.

Parallel/serial interface 246 is responsive to the control signal sent from buffer 208 shown in FIG. 1 and supplies the data to buffer 208 in accordance with the same clock signal.

The whole control circuit 230 is provided for controlling various portions and units in variable-length coding unit 206 so as to multiplex the header information and the data on a time axis in accordance with the standard used in variable-length coding.

FIG. 3 schematically shows a structure of run length data to variable-length code converting unit 240. Referring to FIG. 3, run length data to variable-length code converting unit 240 includes a memory 250 storing a variable-length code table which is accessed using the run data and the level data as an address for outputting the corresponding variable-length code and its code length, a variable-length code generating circuit 252 for generating a variable-length code based on the data read from memory 250, and a control circuit 254 which controls reading from memory 250 and operation of variable-length code generating circuit 252 in accordance with the control signal sent from whole control circuit 230 (FIG. 2), while supplying control signals to neighboring circuits.

Referring to FIG. 4, the variable-length code table in memory 250 includes a plurality of variable-length code data 266 arranged at corresponding addresses. Each variable-length code table 266 includes a variable-length code region 268 of a 17-bit width storing variable-length codes corresponding to combination of given (run, level), and a code length region 270 of a 5-bit width storing information which specifies a length of the variable-length code stored in variable-length code region 268.

Address 260 for accessing variable-length code data 266 includes a run region 262 of 6 bits and a level region 264 of 7 bits, and thus includes 13 bits. The address is produced from the run data and level data supplied from the preceding stage as shown in FIG. 3, and variable-length code table memory 250 is accessed with the produced address for outputting the corresponding variable-length code data.

In address 260, 6 bits are allocated to run 262 and 7 bits are allocated to level 264 because a range of the run is from 0 to 63 and a range of the level is between .+-.41 so that 6 bits and 7 bits are required for representing them, respectively. FIGS. 5 to 10 show DCT output coefficient variable-length code tables of MPEG1. These tables shows all the major data.

As can be seen from FIGS. 5 to 10, the variable-length code region 268 is formed of 17 bits and code length region 270 is formed of 5 bits because the maximum length of the variable-length code is 17 bits. Code length region 270 is required because the code length is required even for handling the variable-length code and the code length of the variable-length code must be output together with the variable-length code.

Combinations of the run and level not mentioned in the tables in FIGS. 5 to 10 are processed by a coding unit (not shown) other than the above variable-length coding unit.

FIG. 11 is a block diagram showing the variable-length coding device using the conventional variable-length code table and also showing variable-length code table memory 250 and control circuit 254. Referring to FIG. 11, conventional variable-length coding device 252 includes a register 282, a 40-bit barrel shifter 104, a shift register 118 for outputting the variable-length code, a zero generating circuit 120, a register 108, 5-bit adder 112 and a code length register 114. Shift register 118 includes five 8-bit registers 118a-118e.

Control circuit 254 supplies control signals a, b, d, f and g to variable-length code table memory 250, register 108, register 282, variable-length register 114 and shift register 118 for operating them, respectively.

In the initial state, shift register 118 outputting the variable-length code and variable-length register 284 both have been cleared to 0. Forty-bit barrel shifter 104 is operable to shift the input data by a value indicated by code length register 114 and store the same in shift register 118.

Initially, the variable-length code and the code length in variable-length code table are stored in registers 282 and 114, respectively. It is assumed that the variable-length code thus stored is "001010" and the code length thus stored is "6". These values are supplied from registers 282 and 108 to 40-bit barrel shifter 104 and 5-bit adder 112, respectively.

The content of variable-length register 284 is 0. Therefore, 40-bit barrel shifter 104 passes the input data therethrough without shifting it, and supplies the input data to shift register 118 for code output.

Five-bit adder 112 adds the input data "6" and the content "0" of code length register 114 together, and writes the result "6" into the code length register 114. Code length register 114 is operable to supply a control signal h to shift register 118 for shifting the same and also supplies it as a data enable signal to a circuit at a subsequent stage, when the value stored in register 114 increases to or above 8. In this case, however, the content is "6", so that shift signal h is not output.

Then, it is assumed that a coded variable-length code of "00001000" is supplied to 40-bit barrel shifter 104 via register 282, and a code length "8" is supplied to the input of 5-bit adder 112 via register 108.

The content of code length register 114 is "6". Forty-bit barrel shifter 104, therefore, shifts the variable-length code by 6 bits to the right, and stores the same in shift register 118. At this time, the stored content of shift register 118 for outputting the code is formed of the initially supplied variable-length code stored at 6 bits starting from the highest bit. The currently supplied (i.e., second) variable-length code is stored at 7th and succeeding bits.

Five-bit adder 112 adds the input data "8" and the content "6" of code length register 114 together, and writes the result "14" into code length register 114.

Code length register 114 outputs shift signal h and equally divides its own content into eight, because the content has increased to 8 or more. Shift register 118 for outputting the code responds to shift signal h by shifting its contents by 8 bits to the left and outputting the content of shift register 118a as coded data (bit stream) from its left end. Thus, the content of 8-bit register 118a is output as the data, and the contents of registers 118b, 118c, 118d and 118e are transferred to registers 118a, 118b, 118c and 118d, respectively. Also, 0's of 8 bits are supplied and written into register 118e from zero generating circuit 120.

As a result of the above processing, the content of code length register 114 goes to "6". In this case, the content of code length register 114 represents the bit number of variable-length code "001000" stored in 8-bit register 118a. Thus, code length register 114 stores a data length of effective data stored in code outputting shift register 118.

When a next variable-length code is input, the input variable-length code is shifted to the right by a bit number of the variable-length code stored in 8-bit register 118a, and then is stored in shift register 112, so that shift register 118 for outputting code stores the next variable-length code at places immediately succeeding those of the variable-length code already stored in shift register 118.

The above processing is repetitively performed on the variable-length code and its code length sent from memory 250, and a variable-length code train is produced in the form of a bit stream.

The image compressing device in a related art flattens the data itself by predicting motion, and further performs the DCT processing and quantization for removing high-frequency components. Therefore, image signals to be compressed contains a large number of 0's, and can be compressed efficiently by using the variable-length code tables, e.g., shown in FIGS. 5 to 10. Since the table look-up system is used, complicated processing is not necessary, and fast coding processing can be performed.

However, the variable-length coding device using the table look-up system described above suffers from a disadvantage that a large memory is required. As can be seen from FIGS. 5 to 10, the variable-length codes have code lengths in a range from 2 to 17 bits. However, when preparing the variable-length code tables in the memory, it is difficult to set the length of variable-length code region itself to an arbitrary bit length, so that a field of a fixed length fitted to the maximum code length must be assigned to each variable-length code data. In order to represent one variable-length code, therefore, data of 22 bits (variable-length code of 17 bits and code length of 5 bits) is required. In order to develop this variable-length code table on the memory, it is necessary to provide a memory of at least 8 kilowords (address space of 13-bit address).times.22 bits.

In particular, the variable-length code tables shown in FIGS. 5 to 10 provide only two hundred-odd kinds of combinations of the run and level to be processed, but the space of 8 kilowords is required for developing the tables on the memory. Therefore, the variable-length coding processing has been desired that can utilize the memory space more efficiently and can reduce the required memory.

A proposal for achieving the above object is disclosed in Japanese Patent Laying-Open No. 4-142163 (1992). According to the disclosure of this publication, attention is paid to the fact that a certain repetition pattern (e.g., of "0") is often found at a leading portion of the variable-length code, and the variable-length code is converted into a number of repetition of the repetitive pattern starting from the leading end, the remaining data and the length of remaining data for storing the same. When accessing the memory, the variable-length code is produced by adding certain characters (e.g., 0's) equal in number to the repetition number of repetitive pattern to the leading end of the remaining data.

According to this manner, the repeated 0's starting from the leading end can be represented by a small number of bits. For example, 2 bits can represent the repetition number from 0 to 3, 3 bits can represent the repetition number from 0 to 7, and 4 bits can represent the repetition number from 0 to 15. This reduces the total bit length required for representing the variable-length code. Since the required bit length per address of memory is reduced, the whole capacity of memory can be reduced.

Even if this technique is used, however, a large unused region still remains in the memory. It is desired to utilize such a region efficiently. Further, the unused region must be utilized without losing convenience of the table look-up system.

Accordingly, it is an object of the invention to reduce a capacity of a memory required for a variable-length code table.

Another object of the invention is to provide a variable-length code table allowing further reduction of a required capacity of a memory.

Still another object of the invention is to reduce a memory capacity required by a table for producing binary variable-length codes as compared with the prior art.

An additional object of the invention is to achieve a table, which is used for converting run data and level data into binary variable-length codes in the image compression coding standard MPEG, with a memory of a reduced capacity.

Another additional object of the invention is to achieve a table, which is used for converting run data and level data into binary variable-length codes in the image compression coding standard H261, with a memory of a reduced capacity.

It is also an object of the invention to provide a variable-length coding device requiring a memory of a reduced capacity.

It is further an object of the invention to provide a variable-length coding device requiring a memory of a further reduced capacity.

An additional object of the invention is to provide a variable-length coding device requiring a memory of a further reduced capacity and allowing fast production of a variable-length code.

A variable-length code table according to the invention is used for producing a variable-length code from data formed of one set of first and second equal-length components each taking a value in a given range. The variable-length code table stores at an address uniquely assigned by the one set of the equal-length components a corresponding variable-length code and a code length of the variable-length code. Combinations of the first and second equal-length components are predetermined in number and finite, and the manner of combination is preselected such that the maximum value of the absolute value of the first equal-length component increases as the absolute value of the second equal-length component combined therewith decreases. The second equal-length components are classified into a plurality of classes in accordance with the magnitude of the absolute value. Each address includes a first region having a value and a length uniquely specified based on the class including the second equal-length component, a second region storing the first equal-length component, and a third region storing the second equal-length component, and is constructed to have a fixed length as a whole. Region lengths of the second and third regions are determined correspondingly to the class including the second equal-length component, and each are specifically determined to have the minimum value required for storing the maximum values of the absolute values of the first and second equal-length components of the combinations of the equal-length components included in the corresponding class.

In this variable-length code table, comparison may be made between the first combination including the second equal-length component belonging to a given class and the second combination including the second equal-length component belonging to a class larger in absolute value than the above given class in connection with the size of the third region for the second equal-length component at each address, which shows the fact that the size in the second combination is larger than that in the first combination. However, the size of the second region for the first equal-length component can be small in the second combination. Therefore, the whole region length can be fixed. If such classification were not made, each of the second and third regions would be required to have a size enough to store the maximum value of the absolute value of the first equal-length component and the maximum value of the absolute value of the second equal-length component, so that the address length would increase as a whole. According to the invention, therefore, the address length required for table access is reduced. This allows reduction of the capacity of the memory for the variable-length code table.

Preferably, the variable-length code is formed of the number of given first characters continuing from the leading end and a remaining code, and the code length is the code length of the remaining code. Although the region representing the number of the leading and continuing first characters has the fixed length, the number of the characters equal to Nth power of 2 can be represented where N is the bit number. Therefore, in the variable-length coding system in which many of the variable-length codes contain the leading and continuing first given characters larger in number than the Nth power of 2, the data length representing the variable-length code stored at each address in the table can be reduced as compared with the case where the above construction is not employed. This effect becomes more remarkable in accordance with increase of the number of variable-length codes having the same leading and continuing characters which are larger in number than the Nth power of 2. This allows further reduction of the capacity of memory required for the variable-length code table.

If the variable-length code table is used in the image compression coding standard MPEG, the first equal-length component is run data, and the second equal-length component is level data. If the variable-length code table is used in the image compression coding standard H261, the first equal-length component is run data, and the second equal-length component is level data.

Another aspect of the invention provides a variable-length coding device for producing a variable-length code from data formed of one set of first and second equal-length components using the variable-length code table of the above aspect. The variable-length coding device further includes an address converting circuit for receiving one set of the equal-length components and performing conversion of the address correspondingly to the one set of the equal-length components based on a class of the second equal-length component included in the one set of the equal-length components and the one set of the equal-length components to supply the same to the variable-length code table.

According to this device, the address required for table access can be produced by the address converting circuit. Since the device uses the variable-length code table of the invention, the address length required for the table address can be short. Therefore, a required capacity of a memory can be small.

Still another aspect of the invention provides a variable-length coding device for producing a variable-length code from data formed of one set of first and second equal-length components using the variable-length code table of the above aspect. The variable-length coding device further includes an address converting circuit for receiving one set of the equal-length components and performing conversion of the address correspondingly to the one set of the equal-length components based on a class of the second equal-length component included in the one set of the equal-length components and the one set of the equal-length components to supply the same to the variable-length code table, and a character adding circuit operable based on the number of leading and continuing first characters of the variable-length code output from the variable-length code table, a remaining code of the same and a code length of the remaining code to output a variable-length code including the first characters equal in number to the first characters to the leading end of the remaining code.

According to this device, the address converting circuit can produce the address required for accessing the table, and can output the variable-length code based on the number of the leading and continuing given first characters, the remaining code and the code length of the remaining code which are obtained as a result of the table access. Since the device uses the variable-length code table of the above aspect of the invention, the address length required for the table address can be shorter than that in the prior art, and the data length stored at each address can be reduced. Therefore, a required capacity of a memory can be small.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

FIG. 1 is a process diagram of image compression processing;

FIG. 2 is a block diagram of a variable-length coding device;

FIG. 3 is a block diagram of a run length data variable-length coding device in a related art;

FIG. 4 schematically shows a construction of a variable-length code table in the related art;

FIGS. 5 to 10 show variable-length code tables of a DCT output coefficient of MPEG1;

FIG. 11 is a block diagram of a conventional variable-length code generating unit;

FIG. 12 is a graph showing distribution of combinations of run and level data of the DCT output coefficient of MPEG1;

FIG. 13 shows combinations of run and level data of the DCT output coefficient of MPEG1 in a form of a table in which the combinations are divided into classes based on the range of level;

FIG. 14 schematically shows an address construction for producing addresses for respective level ranges;

FIGS. 15 and 16 show variable-length code tables of a DCT output coefficient of H261;

FIG. 17 shows distribution of combination of run and level shown in FIG. 6;

FIG. 18 shows contents of distribution shown in FIG. 17 divided into classes based on the level range in a table form;

FIG. 19 schematically shows a method of producing an address;

FIG. 20 is a block diagram showing a run length data variable-length coding unit of an embodiment of the invention;

FIGS. 21 to 27 show variable-length code tables of a DCT output coefficient of MPEG1;

FIG. 28 is a block diagram of an address converting circuit in an embodiment of the invention;

FIG. 29 shows operation of a logic circuit;

FIG. 30 schematically shows a method of producing an address in an embodiment of the invention;

FIG. 31 is a block diagram of a variable-length code generating circuit in an embodiment of the invention;

FIGS. 32 to 34 are flow diagrams showing operation of the variable-length code generating circuit in an embodiment of the invention;

FIG. 35 shows an example of a series of data to be variable-length-coded; and

FIGS. 36 to 38 show change of contents of a shift register for outputting a code.

The present invention utilizes the fact that a particular relationship exists in combinations of run data and level data which are predetermined, for example, in connection with a DCT output coefficient of MPEG1. FIG. 12 shows distribution of the (run, level) combinations of the DCT output coefficient of MPEG1. The abscissa indicates the level, and the ordinate indicates the run. In an area of a small absolute value of the level, as can be seen from FIG. 12, the runs combined with such levels are distributed in a range from 0 to 31. As the absolute value of level increases, the number of runs combined with the levels decrease, and the absolute values thereof also decrease. In an area of a large absolute value of the level, the runs of only one value, i.e., "0" exist.

Combinations of level and run shown in FIG. 12 can be classified based on the range of level as show in a table of FIG. 13. According to the classification shown in FIG. 13, there are four divided ranges, i.e., ranges from -1 to 1, of -2 and 2, and from -6 to -3 and from +3 to +6, and a range other than these. Each of these ranges determined based on the level is referred to as a "class" in the present specification.

As can be seen from FIG. 13, in a range of level from -1 to +1, the maximum value of the run combined with the level is 31. The absolute values of the levels belonging to this class are 0 and 1. Therefore, the run data combined with the level belonging to this class can be represented with 6 bits, and the level data can be represented with 2 bits.

In a range of level of -2 and +2, runs combined with this level ranges from 0 to 16. The absolute value of the level is 2. Therefore, the run combined with the level belonging to this class can be represented with 5 bits, and the level can be represented with 3 bits. Likewise, in the level range from -6 to -3 and from +3 to +6, the run can be represented with 3 bits, and the level can be represented with 4 bits. In the case other than the above, the run can be represented with 2 bits, and the level can be represented with 7 bits.

Therefore, as shown in FIG. 14, one can change the construction of the address for accessing the variable-length code table in accordance with the range of level. More specifically, 6 bits and 2 bits are assigned to the run data and the level data in the level range from -1 to +1, respectively. In the range of level of -2 and +2, 5 bits and 3 bits are assigned to the run data and the level data, respectively. In the range from -6 to -3 and +3 to +6, 3 bits and 4 bits are assigned to the run data and the level data, respectively. In the range other than the above, 2 bits and 7 bits are assigned to the run data and the level data, respectively.

When the address is changed as described above, inconvenience arises if memory regions represented by the addresses overlap with each other. Therefore, the leading 2-bit region of the address is used as a flag 50, and 00, 01, 10 and 11 are assigned to the respective classes (level ranges). By preparing the addresses in this manner, the whole address length can be 11 bits at the most. If classification is not performed in this manner, 13 bits are required for the address as already described (see FIG. 4). Therefore, it can be understood that the address space can be reduced to approximately a quarter owing to the address construction shown in FIG. 14.

The foregoing can be similarly applied to another image coding standard. FIGS. 15 and 16 show variable-length code tables of a DCT output coefficient of H261. In FIGS. 15 and 16, "s" represents a sign. More specifically, s is "0" when the level data is positive, and is "1" when negative. Distribution of the combination of run and level is shown in a diagram of FIG. 17. In FIG. 17, the abscissa indicates the level, and the ordinate indicates the run. Also in the combination of DCT output coefficients of H261, as can be seen from FIG. 17, the maximum value of run data is large when the absolute value of level is small, and the absolute value of run data decreases as the absolute value of level combined therewith increases.

FIG. 18 shows a table in which the DCT output coefficients of H261 are classified. As can be seen from FIG. 18, there are classes corresponding to the level ranges of 0 and 1, between 2 and 7, and of 8 or more, in which case the bit numbers of 7, 7 and 8 are required for representing the combination of run and level.

FIG. 19 shows a manner of producing the address for accessing the DCT output coefficient table of H261 based on the result of FIG. 18. In this case, flag regions 52 are likewise provided for preventing overlapping of the regions for variable-length codes belonging to the respective classes. "00" is assigned to the class of the levels of 0 and 1, "01" is assigned to the class of the levels from 2 to 7, and "1" is assigned to the class other than the above. Thereby, the run and level in the classes of the levels of 0 and 1 and the levels from 2 to 7 can be represented with 7 bits. In the class other than the above, the run and level can be represented with 8 bits. Therefore, it can be understood that the variable-length codes in all the level ranges can be mapped with only 9 bits in total at ranges which do not overlap with each other.

The same concept can be applied also to processing for converting macro block address increment data and motion code into variable-length codes in image compression coding standards MPEG and H261 as well as processing for converting data of combination of (run, level) into variable-length codes in JPEG. Although the following description will be given on a device and a table construction for converting the combination data of (run, level) into variable-length codes in MPEG1, it will be readily understood to those skilled in the art according to the description of the present specification that tables for the respective kinds of conversion described above can be formed according to the similar concept and that variable-length coding devices can be formed using such tables.

A run length data variable-length code converting unit 60 shown in FIG. 20 can be used in variable-length coding unit 206 instead of run length data variable-length code converting unit 240 in the related art already described with reference to FIG. 2. Referring to FIG. 20, run length data variable-length code converting unit 60 includes an address converting circuit 62, a memory 64 storing a variable-length code table according to the invention, a variable-length code generating circuit 66 which is operable based on data indicating the number of leading and continuing 0's of the variable-length code supplied from memory 64, the remaining code thereof and the code length of the remaining code, to add the specified number of 0's to the leading end of the remaining code for outputting the variable-length code, and a control circuit 68 for controlling operation of address converting circuit 62, memory 64 and variable-length code control circuit 66.

Address converting circuit 62, of which specific structure will be described later, receives run data and level data for producing and supplying the address to memory 64 in the manner shown in FIG. 14. Address converting circuit 62 outputs an escape signal when it detects a combination of (run, level) other than those specified by MPEG1. When this escape signal is output, coding of the (run, level) data is performed in accordance with another manner. A unit for this purpose is not shown in the figure.

Contents of the variable-length code table stored in memory 64 are shown in FIGS. 21 to 27. FIGS. 21 and 22 show combinations of (run, level) belonging to the class of the level range from -1 to +1, FIG. 23 show combinations of (run, level) belonging to the class of the level range of -2 and +2, and FIG. 24 show combinations of (run, level) belonging to the classes of the level range from -6 to -3 and from +3 to +6. FIGS. 25 to 27 show combinations of (run, level) in the range other than the above.

For example, referring to FIG. 21, in the level range belonging to the class from -1 to +1, the whole bit width of address bits is 7 bits, among which bits from 7th to 2nd places represent the run data, and 1st and 0th bits represent the level data. Likewise, referring to FIG. 23, in the level range of -2 and +2, bits from the 7th to 3rd places of the address bits represent the run data, and bits from 2nd to 0th places represent the level data. In the level ranges from -6 to -3 and from +3 to +6, bits from the 7th to 4th places of the-address bits represent the run data, and bits from 3rd to 0th places represent the level data. In the range other than the above, bits at the 8th and 7th places of the address bits represent the run data, and bits from 6th to 0th places represent the level data.

Referring again to FIG. 21, data bits from 13th to 10th places represent the number of leading and continuing 0's in the variable-length code corresponding to the (run, level). Bits from 9th to 3rd places represent the remaining code, i.e., code from which the leading and continuing 0's are removed. Bits from 2nd to 0th places represent a code length of the remaining code. For example, referring to FIG. 5, when the run is 3 and the level is 1, the corresponding variable-length code is "001110". This can be expressed in the form according to the invention, in which case, as shown at the row of run of 3 and level of 1 in FIG. 21, the data bits from 13th to 10th places represent "0010" in binary and hence "2" in decimal, and the bits from 9th to 3rd places represent the remaining code of "1110". The code length of remaining code is 4, and can be represented in binary as "100" as shown in FIG. 21. Combinations of other runs and levels can be represented in a similar manner.

FIG. 28 specifically shows address converting circuit 62 in FIG. 20. Referring to FIG. 28, address converting circuit 62 includes an inverter circuit 72 for producing an absolute value of the level data, an 1-bit adder 74, a multiplexer 76, comparators 78, 80 and 82 for comparing a magnitude of the absolute value of level data supplied from multiplexer 76 with 2, 3 and 7, respectively, a logic circuit 84 which outputs a signal for determining the manner of combination of address production by performing a logical operation on the outputs of comparators 78, 80 and 82, and an address producing circuit 86 which produces an address based on the output of logic circuit 84 and received level data and run data. When level data outside the predetermined ranges is detected, logic circuit 84 outputs an error which is sent as an escape signal (see FIG. 20).

Inverter circuit 72 and 1-bit adder 74 are provided for the case where received level data is a negative number, and operate to produce a number by inverting the sign of the negative number. Multiplexer 76 outputs the output of adder 74 when the sign bit of level data is 1 (negative), and outputs the received level data when it is 0 (positive).

FIG. 29 shows the operation of logic circuit 84 shown in 28 in a form of table representing the output with respect to combination of inputs. In FIG. 29, sign bits 1, 2 and 3 represent the outputs of comparators 78, 80 and 82, respectively, and more specifically, represent the sign bits formed by subtracting 2, 3 and 7 from the absolute value of level data.

The case where all sign bits 1-3 are 1 means that the absolute value of level data is smaller than 2. This corresponds to the case where the level range is from -1 to +1 as shown in FIG. 14. In this case, the control output is set to 0. The case where sign bits 1-3 are 0, 1 and 1, respectively, corresponds to the case where the absolute value of level is 2, and the control output is set to 1. The case where sign bits 1-3 are 0, 0 and 1, respectively, corresponds to the level range from -6 to -3 and from +3 to +6, in which case the control output is set to 2. The case where all sign bits are 0 corresponds to the case where the absolute value of level is larger than 6. In this case, the control output is set to 3. These control outputs can be represented in binary as "00", "01", "10" and "11". These are equal to flags 50 shown in FIG. 14, so that flags 50 can be used as they are to produce addresses as shown in FIG. 30. Logic circuit 84 is constructed to set the error output to 0 when combination of sign bits in FIG. 29 belongs to any one of the above cases, and set the error output to 1 in the case other than the above.

FIG. 30 specifically shows a method of producing addresses by address producing circuit 86. Referring to FIG. 30, each leading region 90 of 3 bits is used such that the flag value is stored at flag region 50 of leading 2 bits as it is, and "0" is stored at the third bit if the flag value is between 0 and 2. The run data and level data are assigned to the succeeding bits in accordance with the class as shown in FIG. 30. Thereby, all possible combinations of (run, level) can be represented with 11 bits. The address space of 11 bits corresponds to 2 kilowords. The data at each address has a width of 13 bits. Therefore, memory 64 requires only 2 kilowords.times.13 bits. In the prior art, the memory of 8 kilowords.times.22 bits is required, so that the invention can reduce the required memory to a fraction smaller than 1/6. The construction using only the art disclosed in Japanese Patent Laying-Open No. 4-142163 requires 13 bits for the address, and requires the memory space of 8 kilowords. Even in comparison with this, the variable-length coding can be performed with the memory reduced into 1/4.

FIG. 31 shows variable-length code generating circuit 66 together with variable-length code table memory 64 and control circuit 68.

Referring to FIG. 31, variable-length code generating circuit 66 includes registers 102, 106 and 108, a multiplexer 110, a 5-bit adder 112, a variable-length code register 114, a 40-bit barrel shifter 104, a shift register 118 formed of 8-bit registers 118a-118e, and a zero generating circuit 120. In FIG. 31, the same parts and portions as those in FIG. 11 bear the same reference numbers. Names and functions of those bearing the same reference numbers are the same.

Variable-length code generating circuit 66 shown in FIG. 31 differs the conventional circuit 252 shown in FIG. 11 in that it additionally includes register 106 and multiplexer 110. Register 102 corresponds to register 282 shown in FIG. 11, but the required bit number thereof can be reduced because the code length of code sent from variable-length code table memory 64 is shorter than that in the prior art.

Register 106 is connected to receive data indicative of the number of leading and continuing 0's in the variable-length code from variable-length code table memory 64. Outputs of registers 108 and 106 are connected to two inputs of multiplexer 110. The output of multiplexer 110 is connected to one of inputs of 5-bit adder 112. Other input of 5-bit adder 110 is connected to the output of variable-length register 114.

Control circuit 68 sends control signals a-g to operate variable-length code table memory 64 and variable-length code generating circuit 66 as follows.

Referring to FIG. 32, signal a is assert at step 130. Thereby, the number of leading and continuing 0's stored at the converted address, the remaining code and the code length of remaining code are output from variable-length code table memory 64.

At step 132, signals b, c and d are asserted, and the remaining code, the code length of remaining code and the number of leading and continuing 0's are stored at registers 102, 106 and 108, respectively.

At step 134, signals e and f are asserted. In response to assertion of signal e, multiplexer 110 selects and supplies the content of register 106 to 5-bit adder 112. Therefore, 5-bit adder 112 adds the number of leading and continuing 0's and the content of code length register 114 together, and supplies the result to code length register 114. In response to assertion of signal f, code length register 114 stores the output of 5-bit adder 112.

At step 136, it is determined whether the content of code length register 114 is smaller than 8 or not. If it is smaller than 8, the control advances to step 142. When the content of code length register 114 is 8 or more, control signal h is asserted at step 138. This control signal h is externally output as the data enable signal for externally requesting take-in-of data. Eight-bit register 118a at the leading place in shift register 118 outputs 8-bit data as a variable-length code in response to control signal h.

Referring to FIG. 33, contents of registers 118b-118e are shifted to registers 118a-118d at step 140. The content of code length register 114 is reduced by 8. Register 118e is filled with 0's which are shifted thereto from zero generating circuit 120.

At step 142, control signal g is asserted. Shift register 118 stores the code which remains after 40-bit barrel shifter 104 shifts it by the value of code length register 114 to the right. It should be noted that, at this time, the content from the leading place to the place of the value of code length register is stored, and thereafter the remaining code is added.

At step 144, control signal e is deasserted, and control signal f is asserted. Thereby, multiplexer 110 adds the code length of remaining code stored at register 108 to 5-bit adder 112. Five-bit adder 112 adds the value of code length register 114 and the length of remaining code together and supplies the result to code length register 114. Code length register 114 stores the output of 5-bit adder 112 in response to assertion of control signal f.

At step 146, it is determined whether the content of code length register 114 is smaller than 8 or not. If smaller than 8, the variable-length coding processing of one data is finished. If it is 8 or more, the control advances to step 148 in FIG. 34. At step 148, control signal h is asserted, and take-in of coded data is externally requested. Shift register 118 outputs the value of leading 8-bit register 118a as coded data in response to the assertion of control signal h.

Further, at step 150, contents of registers 118b-118e are shifted to registers 118a-118d, and 0's sent from zero generating circuit 120 are shifted into register 118e. The content of code length register 114 is reduced by 8, and the control returns to step 146 in FIG. 33.

The above processing is repetitively performed on respective data, whereby the variable-length coding is performed.

Operation of the circuits shown in FIG. 31 will be specifically described below. All contents of code output register 118 and code length register 114 are zero at the initial state. First, it is assumed that the coded variable-length code is "001010". The number of leading and continuing 0's is "2", the remaining code is "1010", and the code length of remaining code is "4".

The number of leading and continuing 0's, i.e., "2" is supplied to 5-bit adder 112 via register 106 and multiplexer 110. Five-bit adder 112 adds the input data "2" and the content "0" of code length register 114 together. The result, i.e., "2" is stored in code length register 114.

Remaining code "1010" is supplied to 40-bit barrel shifter 104. Since the content of code-length register 114 is "2", the variable-length code is shifted by 2 bits to the right by 40-bit barrel shifter 104, and is supplied to shift register 118 provided for outputting the code. Thus, "001010" is stored at 1st to 6th bits in shift register 118 provided for outputting the code.

The length "4" of remaining code is supplied to 5-bit adder 112 via register 108 and multiplexer 110. Five-bit adder 112 adds the content of code length register 114, i.e., "2" and the output of multiplexer 110, i.e., "4" together and supplies the result to code-length register 114. Code length register 114 stores the supplied result of "6".

Description will now be given on the operation of circuit 66 which is performed when the coded variable-length code of "00001000" is supplied. In this case, the number of leading and continuing 0's is "4", the remaining code is "1000", and the length of remaining code is "4".

The number of leading and continuing 0's, i.e., is supplied to 5-bit adder 112 via register 106 and multiplexer 110. Five-bit adder 112 adds the input data "4" and the content "6" of code length register 114 together. The result of "10" is supplied to code length register 114 and is stored therein.

Remaining code "1000" is supplied to 40-bit barrel shifter 104 via register 102. The content of code-length register 114 is "10". Therefore, the remaining code is shifted by 10 bits to the right by 40-bit barrel shifter 104, and is supplied to shift register 118 for outputting the code. Shift register 118 stores the output of 40-bit barrel shifter 104 at the eleventh and succeeding bits. In this state, shift register 118 has stored at the 1st to 6th bits the variable-length code initially supplied. The second variable-length code "00001000" is stored at 7th to 14th bits.

The length "4" of remaining code is supplied to 5-bit adder 112 via register 108 and multiplexer 110. Five-bit adder 112 adds the input data "4" and the content of code length register 114, i.e., "10" together, and supplies the result of "14" to code-length register 114 for storing the same. Therefore, control signal h is asserted, and the variable-length code is output.

FIG. 35 shows a series of data supplied to variable-length code generating circuit 66 shown in FIG. 31. FIGS. 36 to 38 show change of contents of shift register 118 in FIG. 31 caused by these data.

Referring to FIG. 35, it is assumed that variable-length codes "110", "01000", "001010", "00001100", "001001100", "001000010" and "00000010100" are sequentially supplied. In these variable-length codes, the numbers of leading and continuing 0's are 0, 1, 2, 4, 2, 2 and 6, and the remaining codes are "110", "1000", "1010", "1100", "1001100", "1000010" and "10100". The remaining code lengths are 3, 4, 4, 4, 7, 7 and 5.

FIG. 36 shows at (a) the initial state. In the initial state, all contents of registers 118a-118e and variable-length code register 114 are 0.

At (b) in FIG. 36 is shown a state that data 1 is input. "110" is stored at 1st to 3rd bits in register 118a, and 3 is stored in the code-length register.

As shown at (c) in FIG. 36, since the number of leading (and continuing) 0 in the second data is 1, "0" at 4th bit in register 118a becomes valid as the leading end of the next code, and the content of code-length register goes to 4. Subsequently, as shown at (d) in FIG. 36, data 2 is input, and the remaining code "1000" of data 2 is stored at four bits starting from fifth place in register 118a. The code-length register takes the value of 8.

Thereafter, respective data are input as shown in FIGS. 36 to 38, and variable-length codes are output as shown at (e) in FIG. 36, (c) and (f) in FIG. 37, and (b), (e) and (f) in FIG. 38. The output variable-length code thus formed is:

It can be understood that the bit stream of the variable-length codes shown in FIG. 35 is output.

According to the invention, as described above, the variable-length code table can be constructed with a memory of a smaller capacity than that in the prior art, and the invention can be applied to the image compression coding standard of not only MPEG1 but also H261 and JPEG. Since intended variable-length codes can be formed by a simple structure formed of the shift register, 5-bit adder and registers, the variable-length codes can be produced fast by a simple circuit structure. Although the embodiments have been described in connection with the case where the number of leading and continuing 0's (or 0) is utilized, the invention is not restricted thereto, but may likewise be applied to the case where the number of leading and continuing 1's is utilized.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.