Self-Aligned Bump Bond Infrared Focal Plane Array Architecture

1. Field of the Invention

This invention relates to a method and structure for fabrication of infrared focal plane arrays (IRFPAs) with high quality photodiodes.

2. Brief Description of the Prior Art

Prior art techniques for fabrication of infrared focal plane arrays have utilized planar processing (VIP, vertical diodes) and bump bonded techniques (BLIMP, DLHJ). The planar processing is more appropriate for mass manufacturing techniques, however temperature restrictions after hybridization prevent use of preferable passivation methods. Bump bond techniques require difficult aligned hybridization with extremely tight mechanical tolerances. The bump bond techniques generally do not permit thinning and are not stable to temperature cycling, especially with large area formats. Both planar processing and bump bonded techniques display long process flows. It follows that a simpler process flow that can provide the same or similar results will provide an economic advantage.

In accordance with the present invention, there is provided a very rapid, simple and highly manufacturable fabrication process for IRFPAs with high quality photodiodes.

Briefly, in accordance with the present invention, advantage is taken of the property whereby vacancy doped or mobile extrinsic dopants in mercury cadmium telluride, preferably gold doped p-type mercury cadmium telluride (HgCdTe), when damaged in the lattice, forms an n-type region in the vicinity of the damage, thereby forming a diode with the adjacent p-type region. Accordingly, in accordance with the present invention, photodiodes are formed in the HgCdTe by pressing a surface of the HgCdTe against a readout integrated circuit with a damage creating feature on the surface of the integrated circuit, such as an electrically conductive bump that preferably also forms an ohmic contact with the HgCdTe. The bumps, which are preferably of tungsten or tin coated tungsten or tungsten coated with a mercury amalgam that will give up the mercury to the surrounding HgCdTe under conditions of elevated temperature or the like, are disposed on the surface of the readout integrated circuit and contact the surface of HgCdTe under pressure and preferably elevated temperature, in the range of 100.degree. to 140.degree. C., preferably about 110.degree. C., to damage the surface of the HgCdTe in the immediate vicinity of the contact. The damaged area of the HgCdTe is thereby converted from p-type to n-type to provide a diode. Thereby, ohmic contact as well as conductivity type conversion and diode formation is provided at the region of the damage on the HgCdTe surface in a single step. By arranging damage creating or inducing elements, such as electrically conductive bump contacts, preferably having a sharp edge which first contacts the HgCdTe surface, on the surface of the integrated circuit in an appropriate pattern, a pattern of diodes is formed in the HgCdTe with a conductor therefrom directly to the readout integrated circuit. Bumps can be formed, for example, in accordance with the procedures as set forth in "Physical properties of thin-film field emission cathodes with molybdenum cones", Journal of Applied Physics, Vol. 47, No. 12, December 1976, pp 5248-51 and the references cited therein. The created bondline also allows the HgCdTe to be thinned to allow temperature cycling to 77.degree. K. without damage with retention of most of the advantages of planar processing. Furthermore, the architecture of the present invention is amenable to both staring and scanning IRFPAs.

FIG. 1 is a schematic diagram of an infrared focal plane array in accordance with the present invention; and

FIGS. 2a to 2c are a process flow to fabricate the infrared focal plane array of FIG. 1.

Referring first to FIG. 1, there is shown an IRFPA 1 in accordance with the present invention. The IRFPA includes a processor 3 disposed in a semiconductor chip and having pads 5 for external connection. Disposed over the processor 3 is an epoxy bondline 7 which secures the processor to a HgCdTe substrate 9 having a cadmium telluride passivation layer 19 at the surface thereof opposing the processor. Electrically conductive spikes or bumps 11 are disposed on each of the pads 5 which corresponds to a detector pixel of the array, some of the pads 5 being available for connection to conductors other than the spikes. The region 13 of the substrate 9 around the spike which has been damaged due to entry of the spike 11 into the substrate as well as a region 14 in close proximity to the damage is converted from p-type to n-type due to the damage whereas the remainder of the substrate remains p-type. A standard antireflective coating 15 is disposed over the substrate 9 and includes vias therein for a conductor 17 which coupled the p-type portion of the substrate to the processor 3 via a pad 5 which is not associated with a pixel.

A process flow for fabrication of the IRFPA of FIG. 1 would be as follows:

Referring to FIG. 2a, a substrate of CdTe 21 is provided and a layer of vacancy doped or gold doped p-type HgCdTe 9 having a thickness of at least about 20 micrometers is deposited on a surface thereof by liquid phase epitaxy (LPE) or a thick layer of HgCdTe is provided in place of substrate 21 and layer 9. A passivating layer of CdTe 19 is then deposited over the HgCdTe layer 9.

A processor in the form of an integrated circuit 3 having pads 5, some of which are associated with pixels to be formed in the HgCdTe and some of which are for other connection is provided. Electrically conductive spikes 11 which are preferably formed from tungsten which can be coated with tin or coated with mercury amalgam and which are 3 to 5 micrometers in height are then formed only on those pads 5 which are associated with a pixel and may also be in other inert locations for leveling purposes. The active surface of the processor 3 is then coated with a bonding epoxy 7 having a thickness of 75 micrometers as shown in FIG. 2b.

The surface of the CdTe layer 19 of FIG. 2a is then forced against the spikes 11 under pressure and elevated temperature to bond the substrate 21 to the processor 3 and cause the spikes 11 to penetrate through the passivating layer 19 and enter into the substrate 9. This causes the region 14 of the substrate 9 around the spike 11 to be converted from p-type to n-type due to the damage to the lattice caused by penetration of the spike 11 into the substrate 9 as shown in FIG. 2c.

The CdTe substrate 21 is then removed, if initially provided, or the substrate of HgCdTe is thinned to a thickness of 10 micrometers, in either case by standard mechanical and chemical-mechanical etching techniques. A standard anti-reflective coating 15 is then formed over the remaining exposed HgCdTe 9 and an aperture is formed therein to the exposed HgCdTe with metallization 17 then formed from the exposed HgCdTe, through the aperture formed in the antireflective coating to a pad 5 on the processor 3. This provides the IRFPA as shown in FIG. 1.

Though the invention has been described with respect to a specific preferred embodiment thereof, many variations and modifications will immediately become apparent to those skilled in the art. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.