Quadrature Modulator With Integrated Distributed RC Filters

1) Field of the Invention

The invention relates to methods and apparatuses for the realization of frequency band-stop, band-pass and low pass filters as integrated circuit elements on a silicon chip for use in a quadrature modulator which can generate complex modulated radio signals.

2) Discussion of Related Art

The prior art for the construction of frequency selective filters includes: (1) passive inductor-capacitor filters; (2) passive resistor-capacitor filters; (3) active RC filters; (4) distributed RC filters; (5) gyrator-capacitor filters; (6) transmission line or waveguide filters; (7) switched capacitor filters; and (8) digital filters, each of which is discussed below.

The construction of inductor-capacitor filters on a silicon chip is constrained by the very small inductance values that can be achieved with spiral metallization patterns within a frequency range above about 2 GHz.

Passive resistor-capacitor filters can only synthesize a limited subset of the possible frequency responses that might be required, and at low frequencies are limited by the available RC product that can be made while also being limited at high frequencies by stray (parasitic) capacitance and resistance.

Active RC filters can provide useful performance up to a few megahertz, but are limited by the performance and bandwidth of amplifiers as well as the parasitic effects mentioned above. Unfortunately, the amplifiers consume power and limit the dynamic range.

Distributed RC filters are, on the other hand, inherently based on the parasitic capacitance and resistance parameters, such as described in "Tidskontinureliga Lagpass Filteri CMOS", by Katarina Hansson and Mats Torkelsson, LUTEDX/(TETE-7029)/pp. 1-26 (1987).

Gyrator-capacitor filters use an active impedance inverting circuit to make a capacitor function as an inductor, so that LC equivalent filters may be built. These circuits are useable for bandpass filters up to a few megahertz. The Gyrator-Capacitor filter can be classed as a form of active RC filter.

Transmission line or waveguide filters require elements that are typically a quarter wavelength long so their construction on a chip is limited to the micro-wavelengths above 2 GHz.

Switched capacitor filters operate according to a number of different principles, but all require transistor switches to operate at a very much higher frequency than the operating frequency range of the filter. This restricts their use to a few hundred kilohertz. Moreover, the dynamic range of switched-capacitor filters is limited by their high noise levels.

Digital filters are very flexible in the frequency response repertoire they can realize, and have the advantage of no tolerances. On the other hand, the signal to be filtered must first exist in digital form and the required analog-to-digital convertors restrict both the dynamic range and speed. Digital logic power consumption is also a factor which restricts such filters to the 300 kHz region or below in practical applications.

The frequency range upon which the present invention focusses is the 0.3 MHz to 300 MHz region. This is above the range of most of the techniques mentioned while being below the range for transmission line solutions. Hitherto there has been no practical silicon-integrable solution for these three decades of frequency, which encompass virtually the entire radio communications frequency spectrum. Accordingly, the present invention was conceived to address this important range of frequencies. The present invention makes use of concepts of the distributed RC techniques mentioned above.

The present invention relates to methods and apparatuses for the realization of frequency band-stop, band-pass and low pass filters as integrated circuit elements on a silicon chip.

The inventive method allows the manufacture of continuous-time, analog filters in frequency ranges not conveniently covered by other, known techniques. Such filters are typically required in the generation of complex-modulated radio signals with the aid of digital signal processors and quadrature modulators. The inventive filters are aimed to be suitable for construction as part of integrated circuits for analog or mixed analog/digital radio communications signal processing applications.

In the present invention, new distributed RC filter structures and applications are disclosed, and in particular, means to overcome the problems created by manufacturing tolerances in the resistive and dielectric layer properties. The distributed RC filter structure include means for selectively switching in and out of the circuit incremental RC lines and for selectively switching in and out of the circuit incremental nulling resistors. Several embodiments are disclosed.

The invention will now be described with reference to the accompanying drawings in which:

FIG. 1a is a partially schematic diagram of the structure of a distributed RC line in accordance with the present invention;

FIG. 1b is the circuit symbol for a distributed RC line filter such as shown in FIG. 1a;

FIG. 2 is a schematic diagram of a prior art distributed RC.sub.NULL device;

FIG. 3 is a schematic diagram of a prior art quadrature modulator arrangement for synthesizing an arbitrary modulated signal;

FIG. 4 is a schematic diagram of a quadrature modulator arrangement in accordance with the present invention;

FIG. 5 is a schematic diagram showing prior art Gilbert mixers as balanced modulators;

FIG. 6 is a schematic diagram of a section of a balanced filter in accordance with the present invention;

FIG. 7 is a schematic diagram of a complete balanced filter in accordance with the present invention;

FIG. 8 is a schematic diagram of a stepwise-adjustable RC line in accordance with the present invention;

FIG. 9 is a schematic diagram of a switched nulling resistor combinable with the switched RC line of FIG. 8 in accordance with the present invention;

FIG. 10 is a schematic diagram showing the use of an adjustable notch filter according to the present invention in a feedback loop for obtaining an adjustable bandpass amplifier response;

FIG. 11 is a schematic diagram of a preferred arrangement of a switched-tunable RC.sub.NULL device in accordance with the present invention;

FIG. 12 is one possible stepwise-adjustable nulling resistor for use with the switched-tunable RC.sub.NULL device shown in FIG. 11 in accordance with the present invention;

FIG. 13 is a schematic diagram of a preferred arrangement of a stepwise-adjustable nulling resistor for use with the switched-tunable RC.sub.NULL device shown in FIG. 11 in accordance with the present invention; and

FIG. 14 is a graph of the frequency response of the filter shown in FIG. 7.

The inventive filter construction includes a distributed RC line as shown in FIG. 1a which utilizes the sheet-resistivity properties of deposited conductive films such as a polysilicon film resistive filter 10, and the capacitance-per-unit-area properties between the resistive filter 10 and a conductive plate 14 (connected to a common by a connection point 14a) with a thin dielectric layer 12 interposed between the layers 10 and 14. The resistive filter 10 includes an input connection point 10a and an output connection point 10b.

In order of the layers' appearance from substrate to top level, the filter is composed of a substrate 13 comprising, e.g., silicon, alumina, gallium arsenide, sapphire or polyamide, an insulating film 11 comprising silicon dioxide, alumina, gallium arsenide, sapphire, polyamide, etc., a conductive plate 14 of heavily doped polysilicon, aluminum, gold or the like, a thin film dielectric layer 12, and a resistive filter 10 composed of polysilicon or the like.

Resistors formed by the polysilicon film 10 are treated as distributed over and insulated from a capacitor plate 14 and, thus, as a distributed RC line that may be described by the resistance per unit length, capacitance per unit length, and length.

The circuit symbol for a distributed RC line is shown in FIG. 1b.

Such RC lines have an inherent low-pass type of frequency response that attenuates higher frequencies, but the cut-off is rather gentle. Sharper cut-off low-pass filters generally achieve their characteristics with the aid of notches in the stop band.

A notch in the frequency response may be formed using a distributed RC line by connecting its capacitor plate 14' terminal to ground 22 through a resistor 21 of specific value, such as shown in FIG. 2. For uniform RC lines, the notch is complete when the resistor connected to ground has the approximate value 0.056 times the total through-resistance Rtot of the resistive filter 10', and the notch frequency is approximately 11.2/RC radians per second where Rtot is the total through-resistance and C is the total distributed capacitance.

Once a complete or partial notch can be formed, other frequency responses can be synthesized, such as bandstop, or bandpass, the latter by including the notch device in the feedback loop of an amplifier such as shown in FIG. 10, discussed below.

According to a first aspect of the invention, matched, balanced, low-pass filters are provided in conjunction with a so-called quadrature modulator for the purposes of synthesizing an arbitrarily modulated radio frequency signal.

According to a second aspect of the invention, means to overcome the high production process spreads (i.e., deviation from ideal values on resistive and dielectric layer properties) are provided. In some processes, typical spreads on the sheet resistivity and capacitance per unit area parameters can be up to 15% on capacitance and as much as 100% max/min ratio on sheet resistivity. Without the inventive means, the notch frequency given by the RC product could not be guaranteed to within an octave. The inventive means can be used to bring the notch frequency within a desired tolerance when such processes are used. The present invention achieves this by effectively providing a stepwise-variable line length that can be programmed in-circuit to set the filter frequency to a desired value.

FIG. 3 shows a prior art arrangement of a quadrature modulator for synthesizing an arbitrarily modulated signal. A digital signal processor (DSP) 30 calculates time-spaced samples of the real and imaginary parts of a desired complex modulation. The real part is given by the desired amplitude times the cosine of the desired phase angle, while the imaginary part is given by the amplitude times the sine of the phase angle. In this way both Amplitude Modulated (AM) signals or Phase Modulated (PM) signals can be generated, or signals comprising both, the result of which is generally known as complex modulated signals. The numerical samples calculated by the DSP 30 are transferred to a pair of Digital-to-Analog (D-to-A) convertors 31 that convert each numerical sample pair into a pair of analog voltages known as I (In-phase) and Q (Quadrature) signals. A sequence of such numerical samples generates I and Q waveforms but in a stepwise fashion.

The steps in the waveforms cause undesirable spectral components that would interfere with adjacent radio channels unless suppressed. Some techniques for D-to-A conversion provide interpolation between samples giving sloping waveforms between adjacent sample values, which reduces but does not sufficiently eliminate the undesired components. Consequently, I and Q smoothing filters 32 are necessary. These are low-pass filters that pass all modulation spectral components of interest but suppress the higher frequency components of the spectrum associated with the stepwise or piecewise linear I, Q waveforms from the D-to-A convertors 31.

The smoothed I, Q waveforms are applied to a pair of balanced modulators 33 together with cosine and sine carrier frequency signals, this arrangement being known as a quadrature modulator. The arrangement described so far and illustrated in FIG. 3 belongs to the well-known prior art.

It is important for accurate signal generation that (1) the two balanced mixers are accurately matched, (2) the levels of the I and Q signals are accurately controlled relative to each other, and (3) the balanced mixers have low carrier leakage or offset, that is, the output signal of a balanced modulator should be zero when its respective I or Q modulating signal is zero.

Since the I and Q signals vary from positive to negative, if a circuit is required to operate only from a single positive supply, then the zero point of an I or Q waveform cannot be defined to be zero voltage, but must be defined to be some positive reference voltage such as half the supply voltage. Then when an I or Q waveform swings below this reference voltage it will be interpreted as negative, and positive when it swings above.

Unfortunately, it is difficult to generate a reference voltage from the DSP 30 that is exactly equal to the voltage the D-to-A convertors supply with an input numerical value of zero. This problem is overcome in the invention by use of the balanced configuration shown in FIG. 4, which uses special D-to-A conversion techniques to generate I and Q signals as well as their complements I and Q.

In accordance with the present invention as shown in FIG. 4, the numerical I and Q signals from DSP 30' are transferred to a delta-sigma (.DELTA.-.SIGMA.) convertor 41. This device is built according to known art to generate a high bitrate stream of binary `1`s and `0`s having a short-term average value proportional to the numerical input value. With a maximum possible numerical input value the bit stream produced would be 11111 . . . (the voltage of a `1` condition being equal to the chosen supply voltage) while the minimum numerical input value will generate the bit pattern 00000 . . . A half-scale numerical input will produce the bit stream 1010101010 . . . having an average voltage equal to half the supply voltage. According to an aspect of the present invention, extra invertor gates 42 are provided at the output of each delta-sigma convertor 41 to additionally generate the complementary bitstreams. That means when delta-sigma convertors 41 produce a bit stream 100100100100 . . . having a mean of 1/3 the supply voltage, the complementary bit stream will be 011011011011 . . . having a mean of 2/3rds the supply voltage. The difference between these two is 1/3-2/3=-1/3 of the supply voltage. If the convertor produces 111011101110 . . . having a mean of +3/4 of the supply voltage then the complementary signal 000100010001 . . . will have the mean 1/4, so that the difference is 3/4-1/4=1/2 supply. Consequently, by using the difference between the convertor output signal and its complement to represent an I or Q signal, the value represented can be positive or negative even with a single positive voltage supply, and no reference voltage need be generated. The balanced mixers 43a and 43b are therefor provided with balanced, two-wire inputs rather than single-ended inputs, that are responsive to the difference in the signals on the two wires and unresponsive to the absolute or common-mode voltage (sum of the voltages) on the two wires.

High bitrate delta-sigma modulation bitstreams are simply converted to the analog voltage they represent by forming the moving average voltage over a large number of bits. This may be done using a continuous-time, low-pass filter having a bandwidth which is a small fraction of the bitrate, but still sufficient to pass all desired modulation components. For the balanced signal configuration developed in this invention, balanced filters 44 are interposed between the delta-sigma convertor outputs and the I, Q balanced modulators 43.

The balanced modulators 43 may include so-called Gilbert mixers 43a and 43b such as shown in FIG. 5. As shown in FIG. 5, the balanced I or Q inputs 50a and 50b of the Gilbert mixers is applied to the bases of two transistors 51a and 51b. The emitters of the two transistors 51a and 51b are commonly connected through respective resistors 52a and 52b to a common bias current source 53. Each of the collectors to the two transistors 51a and 51b are respectively connected to a pair of commonly connected emitters of two pairs of transistors 54a, 54b and 55a, 55b. The base of one transistor 54a, 55b from each of the transistor pairs 54 and 55 are commonly connected to one side of a cosine or sine signal generator 56, with the other base of one transistor 54b, 55a of each of the transistor pairs 54 and 55 being commonly connected to the other side of the cosine or sine generator 56. The collectors of one transistor of each of the two transistor pairs 54a and 55a are commonly connected to one output line 57a, with the other collectors of one FET of each of the two transistor pairs 54b and 55b being commonly connected to the other output line. These balanced modulators can be formed in the same substrate as the balanced low pass filters.

The outputs of the balanced modulators 43a and 43b of FIG. 4 are added together by an adder 43c, to result in a complex modulated radio signal.

The balanced I or Q input signals swing around a mean voltage of half the supply (e.g., around 2.5 volts for a 5 volt supply) but the amplitude of the peak-to-peak voltage excursions should be somewhat less, for example, +/-250 mV. The delta-sigma convertor output, however, can at its extremes swing between 0 and 5 volts on each output line or its complement, and therefore a 1/20 attenuation of the balanced mode signal is called for while no attenuation of the common mode voltage (2-5 volts) is required in this embodiment.

A basic filter section 44 according to the invention which accomplishes the appropriate attenuation of the balanced mode signal is shown in FIG. 6. Two identical RC.sub.NULL devices 61, 62 provide a low-pass filtering action to both balanced (push-pull) and common mode signals, with a notch in the frequency response.

The balanced filter includes two input terminals for I, I or Q, Q and two output terminals 50a and 50b, and a common terminal connected to ground. A series resistor Rs is connected between an input terminal I or Q and an output terminal 50a, and an identical resistor Rs is connected between a second input terminal Q or Q and a second output terminal 50b. Each of the resistors Rs can be formed by depositing a pattern of resistive material over respective conducting plates with an intervening dielectric layer, such as shown in FIG. 1, to provide distributed capacitance between the resistive pattern and the conductive plate.

A resistor or resistors R.sub.NULL are connected between each of the conducting plates to the common terminal, or between the conducting plates, or both. A shunt resistor Rp is connected between the output terminals of at least one of the filter sections (when cascaded, as discussed below with reference to FIG. 7).

This filter 44 has a common mode attenuation of unity at direct current and low frequencies, as there is no resistance to ground. In other words, the pair of balanced, lowpass filters attenuate to a different degree, or not at all, the common mode signal defined as the sum of the voltages on the two input lines or two output lines, compared to the balanced mode defined as the difference of the voltages on the two input or output lines. In the balanced mode, the attenuation is Rp/(2Rs+Rp) due to the resistor Rp connected between the output terminals. This may be set to 1/20 or other desired value less than unity by choice of the shunt resistor Rp relative to resistive filter Rs. The desired value is defined as the difference in voltages between the two input lines or the two output lines.

Another effect of the shunt resistor Rp is to emphasize the high frequency response in the balanced mode relative to the low frequency response, as the high frequency attenuation tends to unity. This has the desirable effect of sharpening up the rate of cutoff. The rate of cutoff may be further sharpened by exponential tapering of the RC line.

A complete filter design consisting of a cascade of such balanced sections is shown in FIG. 7. A series of balanced RC.sub.NULL devices 70, 71, 72, 73, each characterized by a starting line width, an exponential tapering factor (MAX/MIN width ratio), a total resistance Rtot and a total capacitance Ctot are cascade connected by depositing distributed RC lines having resistive patterns deposited over a conductive plate over an intervening dielectric film on a substrate, such as shown in FIG. 1. Shunt resistors Rp1, Rp2, Rp3, Rp4 are connected between the output terminals of each section to provide graduated attenuation. The total attenuation in the balanced mode is set to the desired value by choice of these shunt resistors, but there is a continuum of ways to do the ranging from all attenuation in the first section Rp1 to all attenuation in the last section Rp4. An optimum distribution of the attenuation between the sections can be found by trial and error using computer simulation which gives the sharpest rate of cutoff. Likewise, an optimum set of line widths and tapers can be found within constraints on minimum line width and maximum allowed filter area that gives the sharpest rate of cutoff. The values of a near optimum design for a cutoff frequency of 150 kHz are shown in Table 1 and its resulting frequency response is shown in FIG. 14.

A practical problem is how to control in mass production the resistivity of the deposited films to be equal to the target value assumed in the design. If the resistivity varies, the whole frequency response scales proportionally. For example, double the resistivity would halve the cutoff and null frequencies while half the resistivity would double all frequencies. In the case where practical production tolerances are too wide to permit the frequency response to be held within desired limits, the second aspect of the invention may be applied to adjust the frequency response to be within limits after manufacture. This is done by means of an inventive means for stepwise variation of the line length.

A first configuration according to this aspect the invention is shown in FIG. 8. It is to be understood that the circuit of FIG. 8 can replace any of resistive lines of the balanced null devices 70, 71, 72, 73 shown in FIG. 7.

The step-wise-adjustable line or notch frequency filter includes at least one input 70a, at least one output 70b and a common terminal 70c. A number of resistive elements 80, 81, 82 and 83 may be formed as thin films deposited over a corresponding number of conducting plates with an intervening dielectric layer, such as shown in FIG. 1. The resistive elements are connected in series between the input 70a and output 70b terminals.

A number of switches 85, 87, 89 are arranged to be able to selectively bypass or shortout a respective resistive element. A corresponding number of switches 84, 86, 88 are arranged to be able to selectively connect together respective conducting plates with resistive elements which have not been bypassed and hence through a resistance connected to common terminal 70c. The value of the series connected resistances is changed according to which of the resistive elements is bypassed.

An RC line 80 of a normalized length of one unit is permanently in circuit, while other RC lines 81, 82, 83 of lengths, for example, 1/2, 1/4, 1/8, etc., units may be switched in or out of circuit by switching selected paris of switches 84, 85; 86, 87; and 88, 89. The effective line length may thus be switched between the values 1, 1.125, 1.25, 1.375, 1.5, 1.625, 1.75, and 1.875 in this example. Since increasing the length increases both the total through-resistance and capacitance, the RC product follows the square of these values, and thus is controlled over almost a 4:1 range.

If it is only desired to vary the RC product over a 2:1 range, the maximum line length need only be root(2)=1.414 times the minimum line length and this is achievable with switched sections of length 0.207, 0.1035, 0.052 units, etc. With only three such switched sections, 5% line-length steps corresponding to 10% frequency steps are achievable, and if the nearest frequency step to a desired value is selected, the error is only .+-.5%.

To create a tunable notch filter with the above arrangement, the resistor from the capacitor plate to ground is also varied to maintain a certain fraction (e.g., 0.056) of the through-resistance. Thus, a switched resistor to ground is also used, such as shown in FIG. 9 for example. It is to be understood that the switched nulling resistor circuit of FIG. 9 can replace one or more of the resistors R.sub.NULL71 through R.sub.NULL74 of FIG. 7.

As shown in FIG. 9, the switched nulling resistor usable in conjunction with the circuit of FIG. 8 includes a first, non-switchable null resistor 90 with a relative value R.sub.NULL, to which is connected one end of three series connected null resistances 91, 92, and 93. The three null resistances 91, 92, 93 having relative values of, e.g., 1/2 R.sub.NULL, 1/4 R.sub.NULL and 1/8 R.sub.NULL, respectively. The three resistances 91, 92 93 are selectively switchable into and out of the circuit by parallel connected switches 94, 95 and 96.

While the circuits shown in FIG. 8 and FIG. 9 may be manufacturable using field effect transistor switches, there can be problems with the capacitance and resistance of the switches, as well as limitations on the dynamic range of signal voltage swing through the filter imposed by the switch transistor characteristics.

The preferred implementation of a tunable notch filter in accordance with the present invention, such as shown in FIGS. 11 and 13, largely eliminates these problems and gives a notch filter that can operate with a rail-to-rail signal swing.

It will be appreciated that once a notch filter can be formed on a desired frequency, low-pass filters can be constructed by the cascade connection of such devices to position notches in the stop band so that all frequencies above a certain range are suppressed to a desired extent. Such filters may not have the same sharpness of cutoff as, for example, LC filters, but the present invention does allow practical and useful filters to be made in the frequency range 0.3 to 300 MHz, and such a filter has been successfully fabricated that passes frequencies up to about 3 MHz with little attenuation but has high attenuation at 12 MHz and above by the positioning of notches at 12.5 MHz, 35 MHz, 52 MHz and 300 MHz. Because tolerances on the higher frequency notches further away from the passband have little effect on the passband, it was determined that in this instance they did not need to be tunable, and that only the filter having its notch frequency nearest the passband had to be tunable to remove the effect of process spreads.

FIG. 10 shows how an adjustable notch filter can be used to obtain a bandpass amplifier response suitable for frequency-selective, intermediate frequency amplification in radio systems of appropriate bandwidth. A tunable notch device 102 according to the invention is connected as the feedback path around an amplifier 101 such that the gain is suppressed outside the notch frequency when the filter 102 allows a strong, negative feedback signal through, while the gain is high around the notch frequency when the negative feedback effect is reduced. A cascade of such tunable selective amplifiers can be used to form an integrated circuit intermediate frequency strip for small, portable radio receivers. The "tuning bits" shown in FIG. 10 refer to control signals which operate switches 125-132 of FIG. 11 and 140-143 of FIG. 13.

A preferred arrangement for an adjustable notch filter that does not suffer loss of dynamic range due to the transistor switches is described below.

Adjustment of the notch frequency is provided by means of a stepwise adjustable line length using an advantageous, inventive configuration. This is used with a matching stepwise adjustable resistor to form the adjustable notch device.

A preferred implementation of the adjustable RC line is shown in FIG. 11. A main, permanently in-circuit line section 110 is cascade-connected with switchable sections 111,112, 113, 114 on either side. Two switchable sections 111, 112 on the left hand side as shown in FIG. 11 have linelengths that are a first fraction dL of the main line length L. The two switchable sections 113, 114 on the right hand side have fractional lengths 3dL. Thus, various effective line lengths can be achieved by switching by corresponding switches 115, 116, 117, 118, 119, 130, 131, 132 the switchable sections in or out of circuit in the following combinations:

An important feature achieved by the above arrangement is that the line sections switched into circuit are always contiguous, i.e., no combination of lines such as "in out in" is used. This enables simplification of the switching so that the capacitor plates only of the lines need to be switched. In other words, the switching is thereby simplified as it is only necessary to switch the capacitor plate terminals of the line sections, and not the series resistive part. To switch a line section dL or 3dL to add to the main line length, its capacitor plate is connected to the capacitor plate of the main line (e.g., by switch 115). To prevent the line section adding to the main line length, its capacitor plate is either left unconnected or connected to ground (e.g., by switch 119). The switched out sections therefore appear as separate, short RC lines or series resistors that are in cascade with the device and not additive to the effective main line length L. Thus, when the main line terminal is connected to ground via the nulling resistor of FIG. 13, for instance, the frequency to the null in the frequency response so created is not affected by the switched-out sections.

To provide a matching, stepwise-adjustable nulling resistor, the arrangement of FIG. 12 could in principle be used. This has a main resistor R.sub.NULL 123 of nominal value 0.056 of the resistance of the main RC line total resistance. Two switchable sections (126, 127) of fraction dL/L times the main nulling resistor R.sub.NULL and two switchable sections (124, 125) of value 3dL/L are provided, enabling the same control signals that select the line sections to be used to select corresponding switchable parts of the nulling resistor of FIG. 12.

A disadvantage of the arrangement of FIG. 12 is that the resistance of the switch transistors that can be fabricated on a silicon chip is appreciable compared to the switched resistance. Therefore, the improved arrangement of FIG. 13 is disclosed.

In FIG. 13, adjustment of the total effective resistance R is accomplished by switched shunt resistors of high value instead of switched series resistors of low value. The main resistor value R in FIG. 12 is now shown in FIG. 13 divided into a fraction aR and a fraction (a-1)R. In parallel with the first fraction aR are connected two resistors R1 and R2 switchable into and out of the circuit by two transistors 135, 136. Switching in R1 will reduce the effective value aR to aR-dR where dR is equal to (aR).sup.2 /(aR+R1), while switching in both R1 and R2 will reduce the effective value aR to aR-2dR. Likewise, the two additional resistors R3 and R4 connected in parallel to (1-a)R and switchable into and out of the circuit by two additional transistors 137, 138 allow the resistance (a-1)R to be reduced to (a-1)R-3dR or (a-1)R-6dR. Thus, all values of total resistance from R to R-8dR in steps of -dR can be achieved.

Since the adjustment of R is in the downward direction, the value of R must initially be set to 8dR ohms higher than in FIG. 13, and the switching transistors 135-138 must be operated by inverse control signals to those of the switches 115 to 118 of FIG. 11. The value of the fraction "a" may be chosen so that smallest of the four switchable resistors R1, R2, R3 and R4 is as great as possible in order to minimize the influence of series switch resistance. If "a" is too small, then R1 and R2 will be unnecessarily small while R3 and R4 are large, and vice versa if "a" is too large. Therefore, an optimum exists that can be found by calculation.

The construction of the notch filters and adjustable notch filters and their applications has been described here under the assumption that integration on a silicon integrated circuit is the aim, but one skilled in the art can readily adapt the invention to other forms of fabrication or applications, such adaptations nevertheless being considered to be within the scope of the invention as set forth in the claims. The above discussion of the exemplary embodiments is for purposes of explanation and not limitation. The scope of the invention should be determined by reference to the appended claims.