Method of Making Buried Bit Line ROM With Low Bit Line Resistance

The present invention relates to a buried bit line ROM with a low bit line sheet resistance and a high punch-through voltage and a process for making such a ROM.

As the memory density of a ROM increases, the cell dimensions decrease, resulting in high sheet resistance (R.sub.s) of buried bit lines in the ROM. This is because a decrease in cell dimension causes a decreased width in the bit line which increases bit line sheet resistance. The reduced spacing between the bit lines also results in an unacceptably low punch-through voltage between adjacent bit lines.

FIG. 1 illustrates a buried bit line ROM 20. The ROM 20, for illustrative purposes, comprises a P-type silicon substrate 21. Of course, the ROM could alternatively have an N-type substrate. In this example, a plurality of N.sup.+- type buried bit lines 22 are formed in the ROM 20. Each bit line 22 has a width W and the spacing, or channel, between adjacent bit lines has a length S. A plurality of polysilicon word lines 24 are also formed on the surface of the substrate 21. The ROM 20 comprises a plurality of cells. One such cell 30 is shown in dashed lines in FIG. 1. A cross-sectional view of cell 30 of FIG. 1 taken along the line AA' is shown in FIG. 2.

As seen in FIG. 2, the cell 30 comprises two adjacent buried bit lines 22 which form source and drain regions for the cell. A channel 32 of length S is formed between the two bit lines in the cell 30. A gate oxide layer 36, 37 is formed on top of the substrate 11. The oxide layer is thicker at portions 36 located above the bit lines 22 and thinner at portion 37 located above the channel 32. The thick oxide layer portions 36 are known as field oxide (FOX) regions and the thinner layer portions 37 are known as gate oxide regions. A polysilicon word line 24 is formed over the gate oxide layer 36.

As indicated above, when the bit line width W is too small, the bit line sheet resistance is unacceptably high. In addition, when the bit line spacing S, or channel, is too small, the punch-through voltage between adjacent bit lines is unacceptably low.

Co-pending application Ser. No. 08/092,189 filed on Jul. 14, 1993 and now U.S. Pat. No. 5,430,673 to the same inventors and assigned to the same assignee discloses a buried bit line ROM with low bit line resistance. That memory device and method for making it relate to a memory cell having either the source or drain at the sides and bottom of a trench. Thus, each trench forms either a single source or drain. Also, the fabrication process for the device disclosed therein is different than the process disclosed below.

A buried bit line memory device is also disclosed in U.S. Pat. No. 4,912,535 to Okumura. Okumura discloses a RAM type memory cell having a diffusion region on one side of a trench.

It is an object of the present invention to provide a buried bit line structure and a method for making a buried bit line structure which eliminates the sheet resistance and punch-through voltage problems in high density buried bit line ROMs having small bit line width and spacing.

The present invention uses a trench filled either with polysilicon or spin-on-glass (SOG) and polysilicon to form the buried bit lines in a ROM. This reduces bit line resistance and increases punch-through voltage.

FIG. 1 illustrates a conventional buried bit line ROM array;

FIG. 2 illustrates a cross-sectional view of one ROM cell in the array of FIG. 1;

FIGS. 3-10 illustrate one method of fabricating buried bit lines according to the present invention; and

FIGS. 11-14 illustrate a second method of formulating buried bit lines according to the present invention.

FIGS. 3-10 illustrate one method for forming a memory cell having buried bit lines in accordance with the present invention.

As seen in FIG. 3, the starting point is a silicon substrate 21 which illustratively is of P-type and is doped with boron atoms. The substrate has a dopant concentration of about 1.0 E15/cm.sup.3. A dielectric layer 50, for example a silicon nitride layer (Si.sub.3 N.sub.4), preferably having a thickness of about 1000 .ANG.ngstroms, is deposited on top of the substrate 21.

A layer of photo-resist is then deposited on top of the first insulation layer 50. The photo-resist layer is patterned to form photo-resist stripe portions 52, which stripes are separated by the openings 54, which leave portions of the insulation layer 50 exposed.

Using the photo-resist stripes 52 as a mask, the portions of the insulation layer 50 exposed by the opening 54 and the underlying substrate 21 are etched using a dry etch to a predetermined depth, preferably 1 micron. The photo-resist portions 52 are then removed. The resulting trenches 56 are seen in FIG. 4.

A dielectric, such as SiO.sub.2, is then deposited or thermally oxidized on the exposed surfaces, including the side walls and bottom of the trenches 56, forming a second dielectric layer 58, preferably having a thickness between 500.about.2000 .ANG.ngstroms.

As seen is FIG. 5, the trenches are filled with a first polysilicon material (poly 1) 60. The poly 1 material 60 is doped to be the opposite conductivity of the substrate 21, in this example, to be N.sup.+ type. The doping can be accomplished using POCl.sub.3 at 800.degree..about.950.degree. C. for 10-30 minutes. Alternatively, arsenic atoms can be implanted using ion implantation at 50 KeV with a dose of 1.times.10.sup.15 /cm.sup.2 -1.times.10.sup.16 /cm.sup.2. As seen in FIG. 6, after the poly 1 material 60 is doped, it is etched back to expose an upper portion 61 of the dielectric-covered trench walls. Next, as seen in FIG. 7, the exposed dielectric layer 58 is etched back. The buried strap depth B, preferably 0.05-0.2 microns, is controlled by the etch back depth of the polysilicon trench 60 fill and the removal of the exposed insulator 58.

As seen in FIG. 8, the unfilled portion of the trench is filled with a second layer of polysilicon (poly 2) 62. This layer 62 is heavily doped to be the opposite conductivity of the substrate 21, in this example to be N.sup.+ type. The doping can be accomplished using POCl.sub.3. Alternatively, As or phosphorus ions may be implanted using ion implantation. The poly 2 layer 62 is then etched back or CMP (chemical mechanical polished) back.

The heavily doped poly 2 layer 62 is the source of dopant (or impurities) which diffuse by side diffusion, and in this example N.sup.+ side diffusion, through the portions of the trench wall not having an insulation layer 58. This side diffusion forms regions 64 and 66 in the two bit lines in the cell 30. Regions 64 and 66, along with region 62 to which each is electrically connected, form the source and drain regions, of the memory cell 30. Thus, the source is formed by one set of regions either 64 and 62, or 66 and 62 of one bit line 22 and the drain is formed by another set of regions either 64 and 62, or 66 and 62 of an adjacent bit line 22. The spacing, or channel, S is the distance between the bit lines, that is, the distance between region 64 and region 66.

As seen in FIG. 9, the remainder of the first insulation layer 50 is etched off and an oxide layer is then thermally grown on the substrate 21. The oxide layer preferably has a thickness of 100-200 .ANG.ngstroms at the gate oxide region 37 and a thickness of 200-500 .ANG.ngstroms at the oxide region 36. On top of the oxide layer 36, 37 is formed the polysilicon word line 24.

As seen in FIG. 10, a layer of photoresist 68 is positioned on top of the polysilicon word line 24 to mask the device for ROM coding. The ROM code implant is performed in any well known conventional manner. For example, it can be performed by ion implantation at 50 KeV, with a dose of dopant being, for example, boron at 150 KeV and 1.multidot.10.sup.14 /cm.sup.2.

The photoresist layer 68 is removed. The rest of the processes for completing the ROM array are entirely conventional back-end processes including BPSG, contacts, metallization, and ROM coding.

FIGS. 11-14 illustrate a second method for forming a memory cell having buried bit lines in accordance with the present invention. These steps replace those disclosed in FIGS. 5-9. Beginning with the structure shown in FIG. 4, the trench is partially filled with a deposition of spin-on-glass (SOG) 70. FIG. 12 shows an anisotropic over-etch of the SiO.sub.2 using plasma etch with F.sub.2 -based or Cl.sub.2 -based gases.

As seen in FIG. 13, after the second dielectric layer 58 etch, the trenches are filled with a first layer of polysilicon 72 (poly 1'). Before the poly 1' layer 72 is deposited in the trench, the SOG can optionally be etched off by BOE (buffer HF oxide etch). The poly 1' material is doped to the opposite conductivity of the substrate 21, in this example to be N.sup.+ type. This doping is performed in the same way as the doping described for the polysilicon material 60, described above. Side diffusion, in this example N.sup.+ side diffusion, for the portions of the trench wall not having an insulation layer 58 is utilized in the regions 64' and 66' of each of two bit lines in the cell 30, along with region 72 to which they are each electrically connected, form the source and drain regions of the memory cell 30. Thus, the source is formed by one set of regions 64'/72, or 66'/72 of one bit line 22 and the drain is formed by another set of regions 64'/72, or 66'/72 of an adjacent bit line 22.

As seen in FIG. 14, the first insulation layer 50 is etched off and a oxidation layer 36, 37 is then formed on substrate 21. The polysilicon word line 24 is then formed on top of the oxide layer 36. This layer is heavily doped to the opposite conductivity as the substrate 21 and etched to the appropriate pattern. The remainder of the process is performed as described in relation to FIG. 10.

The buried bit lines formed by either of the above described poly trench methods result in low bit line sheet resistance and good bit line-to-bit line punch-through voltage. Therefore, the bit line pitch (bit line width plus spacing between adjacent bit lines) can be reduced for a high density ROM array.

The above described embodiments of the invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the spirit and scope of the following claims.