US 5,528,201 AGrant
Pierce Crystal Oscillator Having Reliable Startup for Integrated Circuits
Issue Date:1996-06-18
•12 Claims
•3 Drawing Sheets
Abstract
A Pierce crystal oscillator circuit for a digital integrated circuit has a capacitance element (such as a field effect capacitor) of an appropriate capacitance value disposed on-board the integrated circuit. One lead of the capacitance element is coupled to the input lead of the gain stage of the Pierce oscillator circuit whereas a second lead of the capacitance element is coupled to the output lead of the gain stage. Providing the capacitance element facilitates oscillator startup and reliability by effectively eliminating the upper gain limit for oscillation. Specific circuit embodiments are also disclosed.
Metadata
Assignee
- National Semiconductor Corporation
Inventor
- Timothy D. Davis
Application Information
Application Number:US 4144643
Filing Date:1995-03-31
Priority Date:1995-03-31
Art Unit:252
Classifications
IPC:
H03B 536
Field of Search:
331116 FE;117 FE;107 R;108 R;117 R;109;115;116 R
Patent Drawings (3 sheets)
Description
Field of the Invention
This invention relates to crystal oscillator circuits for integrated circuits.
Background Information
Low-power crystal oscillator circuits are commonly used on digital integrated circuits to generate relatively low frequency digital clock signals. Typically the gain stage of the oscillator circuit is disposed on the integrated circuit whereas the crystal of the oscillator circuit is external to the package containing the integrated circuit.
FIG. 1 (Prior Art) is a circuit diagram of a low-power crystal oscillator circuit called a Pierce oscillator. Pierce oscillator 1 of integrated circuit 2 includes an inverting gain stage 3, a first resistor 4, a second resistor 5, a stray capacitance 6 and two terminals 7 and 8. The dashed line 9 indicates the boundary of the integrated circuit 2. A crystal 10 and two discrete capacitors 11 and 12 external to the integrated circuit are connected to terminals 7 and 8 in a pi configuration. The ability of the oscillator circuit to startup is dependent upon the magnitude of the stray capacitance 6. Moisture, terminal placement, package type and socket type affect the magnitude of the stray capacitance and therefore tend to make the oscillator circuit unreliable.
Summary
A Pierce crystal oscillator circuit for a digital integrated circuit has a capacitance element (such as a field effect capacitor) of an appropriate capacitance value disposed on-board the integrated circuit. One lead of the capacitance element is coupled to the input lead of the gain stage of the Pierce oscillator circuit whereas a second lead of the capacitance element is coupled to the output lead of the gain stage. Providing the capacitance element facilitates oscillator startup and reliable operation. The capacitance element has a value C.sub.Badded given by the following equation: ##EQU1## Specific circuit embodiments are also disclosed. This summary does not purport to define the invention. The invention is defined by the appended claims.
Brief Description of the Drawings
FIG. 1 (Prior Art) is a simplified diagram of a Pierce crystal oscillator circuit.
FIG. 2 is a simplified diagram of an oscillator circuit in accordance with an embodiment of the present invention.
FIG. 3 illustrates a circuit model of a crystal.
FIG. 4 illustrates a circuit model for modeling operation of the circuit of FIG. 2.
FIG. 5 is a simplified transistor level diagram in accordance with another embodiment of the present invention.
Detailed Description of the Preferred Embodiments
FIG. 2 is a simplified diagram of an oscillator circuit 100 in accordance with an embodiment of the present invention. Oscillator circuit 100 includes an inverting gain stage 101 of gain -A, a first resistance element 102 of resistance R.sub.S, a second resistance element 103 of resistance R.sub.B, a capacitance element 104 of capacitance C.sub.Badded, an external crystal 105, a first external capacitor 106 of capacitance C.sub.o1, and a second external capacitor 107 of capacitance C.sub.02. Dashed line 108 indicates the boundary of the integrated circuit 109 upon which the inverting gain stage is formed. Terminals 110 and 111 are terminals of the integrated circuit 109. The stray capacitance 112 of magnitude C.sub.Bstray inherently exists between the input lead and the output lead of the inverting gain stage.
Integrated circuit 109 is assumed to be packaged (in, for example, a plastic package a ceramic package). The portion of the connections between the integrated circuit 109 and the external circuit components below dashed line 108 due to packaging (for example, wire bonds) are considered to be part of the illustrated connections to terminals 110 and 111 below dashed line 108. Resistance elements 102 and 103 may be realized as any suitable structure including thin film metal resistors, thin film polysilicon resistors, and resistors made of diffusion. Inverting gain stage 101 may be either a single stage or a multi-stage amplifier. External capacitors 106 and 107 may be discrete capacitors of any suitable construction including mica, ceramic, tantalum, and mylar. Generally C.sub.o1 .apprxeq.C.sub.o2.
Capacitance element 104 is provided in the oscillator circuit to provide an adequately large capacitance C.sub.B to facilitate oscillator startup by effectively eliminating the upper gain limit for oscillation (C.sub.B =C.sub.Bstray +C.sub.Badded). The value of capacitance C.sub.Badded may be determined as explained below in connection with equations 2-20.
FIG. 3 illustrates a model of a quartz crystal. The admittance Y.sub.c of the modeled crystal is given by the equation: ##EQU2##
FIG. 4 illustrates a circuit model for modeling operation of the circuit of FIG. 2. The circuit model is developed by substituting the model of FIG. 3 for crystal 105 of FIG. 2, by modeling the gain stage 101 of FIG. 2 as a dependent voltage source -AV.sub.i, and by providing a noise current source I.sub.s. The node voltage matrix of the circuit model of FIG. 4 is: ##EQU3##
The system transfer function therefore is: ##EQU4## It is understood from control system theory that the necessary and sufficient condition that a feedback system be stable is that all the poles of its transfer function have negative real parts. This condition implies that the roots of: ##EQU5## must have at least one positive real part in order for the described system to start oscillating. The polynomial represented by equation 5 can be obtained by expanding the determinant and substituting for Y.sub.c. This yields:
where:
The Routh-Hurwitz criterion indicates that the system is stable if and only if all the elements in the first column of the array (i.e., P.sub.4, P.sub.3, Q.sub.1, T.sub.1) all have the same algebraic sign. Because the system is to be unstable (i.e., to oscillate), relationships are developed for circuit parameters that cause a change in algebraic sign for P.sub.4, P.sub.3, Q.sub.1, or T.sub.1. From inspection of equations 6B and 6C, it is seen that P.sub.4 and P.sub.3 will always be positive for all positive values of circuit parameters (i.e., A, R.sub.B, C.sub.o, L . . . ). The system will therefore oscillate if Q.sub.1 or T.sub.1 are made negative. Because useful information is generally not obtained by attempting to make Q.sub.1 negative, attention is focused upon T.sub.1. It is observed that: ##EQU8##
Because the objective is to minimize or eliminate the upper gain limit for oscillation, the problem is simplified by looking at Q.sub.1 and T.sub.1 as A.fwdarw..infin.. Dividing each coefficient by A and letting A.fwdarw..infin. yields: ##EQU9## Substituting the P' values for Q.sub.1 reveals: ##EQU10##
Substituting circuit parameters and simplifying yields: ##EQU11##
The inequality of equation 14 is not, however, generally maintained when typical circuit values are employed. Q.sub.1 is therefore assumed to be positive. Assuming that Q.sub.1 is positive, equation 10 becomes: ##EQU12## Substituting circuit parameters and simplifying yields: ##EQU13## If, R.sub.B >>R.sub.s and C.sub.o >>C.sub.B, equation 17 becomes: ##EQU14## Solving for C.sub.B yields: ##EQU15##
Accordingly, making C.sub.B meet the condition of equation 19B effectively eliminates the upper gain limit for oscillation. To ensure that C.sub.B is adequately large in the embodiment of FIG. 2 despite the variable capacitance C.sub.Bstray, capacitance element 104 is sized so that: ##EQU16## Component values in accordance with a specific embodiment which oscillates at frequency 32,768 Hz are set forth in Table I below:
FIG. 5 is a simplified transistor level diagram of a specific embodiment realized on an integrated circuit. Terminal X1 200 and terminal X2 201 of FIG. 5 correspond with terminals 110 and 111 of FIG. 2. Inverting gain stage 202 of FIG. 5 corresponds with inverting gain stage 101 of FIG. 2. Resistance element 203 of FIG. 5 corresponds with resistance element 102 of FIG. 2. Capacitance element 204 of FIG. 5 corresponds with capacitance element 104 of FIG. 2. Input lead VDDLPO 205 provides a supply voltage in the range of 1.6-6.0 volts to the oscillator circuit. Input lead ENAZ 206 is an active low enable input lead. When the enable signal on input lead ENAZ is at a digital high, N-channel field effect transistor 207 is conductive and P-channel field effect transistor 208 is nonconductive. The high voltage supply to the stage made up of transistors 209 and 210 is disconnected and the output lead 211 is coupled to ground. The inverting gain stage 202 is therefore disabled.
Input lead 212 is coupled to a current mirror (not shown) to provide a voltage bias to P-channel field effect transistors 213 and 214. The supply current through transistors 213 and 214 is therefore controlled by the voltage on lead 212. The gate of P-channel transistor 215, on the other hand, is grounded and the supply current through this transistor is not controlled. Unless the voltage on input lead VDDLPO 205 is high, N-channel transistor 216 is nonconductive thereby preventing current flow through the stage made up of transistors 217 and 218. It is therefore seen that the inverter gain stage 202 is in turn made up of a first gain stage including transistors 219 and 220, a second gain stage including transistors 217 and 218, and a third gain stage including transistors 209 and 210. Resistor 221 is provided to limit the bandwidth of the oscillator circuit.
Hysteresis is provided by P-channel transistor 222 and inverter 223. When the voltage on the input lead 224 of the second stage falls to the voltage at which transistors 217 and 218 cause the voltage on output lead 225 to rise to the switching voltage of inverter 223, inverter 223 switches and forces the voltage on lead 226 low. The low voltage on lead 226 turns P-channel transistor 222 on thereby pulling the voltage on output lead 225 upward for the same voltage on input lead 224. To pull the voltage on output lead 225 down to the switching voltage of inverter 223, the voltage on input lead 224 must be adequately high that N-channel transistor 218 is adequately conductive that it overcomes the pullup effect of both transistors 217 and 222.
Inverters 227 and 228 buffer the oscillator clock signal and supply the clock signal onto output lead RTCCLKZ 229. In some embodiments, a resistor corresponding roughly with resistance element R.sub.B is provided external to the integrated circuit and is coupled to terminals 200 and 201. In other embodiments, a resistance element corresponding with resistance element R.sub.B is provided on the integrated circuit, one lead being coupled to the input lead of inverting gain stage 202, the other lead being coupled either to the output lead of inverting gain stage 202 or to terminal 201.
Although certain specific exemplary embodiments are described above in order to illustrate the invention, the invention is not limited to the specific embodiments. The present invention does not depend upon the specific derivation presented above. The derivation is presented only for informational purposes. Any suitable structure having a capacitance can be used to implement capacitance element C.sub.Badded. Accordingly, various modifications, adaptations and combinations of various features of the specific embodiments are within the scope of the claimed invention as set forth in the appended claims.
Claims
I claim:
1. A circuit, comprising: an integrated circuit, said integrated circuit comprising: an inverting gain stage having an input lead and an output lead; a first resistance element having a first lead and a second lead, said first lead of said first resistance element being coupled to said output lead of said inverting gain stage; a first terminal of said integrated circuit coupled to said input lead of said inverting gate stage; a second terminal of said integrated circuit coupled to said second lead of said first resistance element; a second resistance element having a first lead and a second lead said first lead of said second resistance element being coupled to said input lead of said inverting gain stage, said second lead of said second resistance element being coupled to said output lead of said inverting gain stage; and a capacitance element having a first lead and a second lead, said first lead of said capacitance element being coupled to said input lead of said inverting gain stage, said second lead of said capacitance element being coupled to said output lead of said inverting gain stage; and a first external capacitor having a lead coupled to said first terminal of said integrated circuit; a second external capacitor of capacitance C.sub.o having a lead coupled to said second terminal of said integrated circuit; and a crystal having a first lead and a second lead, said first lead of said crystal being coupled to said first terminal of said integrated circuit, said second lead of said crystal being coupled to said second terminal of said integrate circuit, wherein said first resistance element has a resistance R.sub.S, said second resistance element has a resistance R.sub.B, and said capacitance element having a capacitance C.sub.Badded, wherein: ##EQU17## f.sub.c being the series resonance frequency of the crystal, f.sub.c being less than 1 MHz.
2. The circuit of claim 1, wherein said capacitance element is a field effect capacitor having a first plate and a second plate, said first plate being a layer of polysilicon, said second plate being a diffusion region, said layer of polysilicon being insulated from said diffusion region by a layer of oxide.
3. The circuit of claim 1, wherein said capacitance element has a capacitance of at least 2 pF.
4. The circuit of claim 1, wherein said inverting gain stage comprises: a first inverting gain stage having an input lead and an output lead; a second inverting gain stage having an input lead and an output lead, said input lead of said second inverting gain stage being coupled to said output lead of said first inverting gain stage; a third inverting gain stage having an input lead and an output lead, said input lead of said third inverting gain stage being coupled to said output lead of said second inverting gain stage; and a resistance element having a first lead and a second lead, said first lead of said resistance element of said inverting gate stage being coupled to said output lead of said third inverting gain stage, said second lead of said resistance element of said inverting gate stage being said output lead of said inverting gain stage of said integrated circuit.
5. The circuit of claim 4, wherein said resistance element of said inverting gain stage has a resistance in the range of 160-240 k.OMEGA..
6. The circuit of claim 1, wherein said inverting gain stage has an enable input lead.
7. The circuit of claim 1, wherein said inverting gain stage has a hysteresis characteristic.
8. The circuit of claim 1, wherein said first resistance element comprises a diffusion region.
9. The circuit of claim 8, wherein said first resistance element has a resistance in the range of 80-160 k.OMEGA..
10. A pierce oscillator circuit disposed on an integrated circuit, comprising: a first oscillator terminal; a second oscillator terminal; an inverting gain stage having an input lead and an output lead, said input lead of said inverting gain stage being coupled to said first oscillator terminal; and means for facilitating start up oscillation in said oscillator circuit by providing a capacitance of at least 2 pF between said input lead of said inverting gain stage and said output lead of said inverting gain stage, wherein said start up oscillation has a frequency of less than 1 MHz.
11. The pierce oscillator circuit of claim 10, wherein said means for facilitating start up oscillation is a field effect capacitor.
12. An oscillator circuit comprising: a first terminal of an integrated circuit; a second terminal of said integrated circuit; a crystal having a first lead and a second lead, said first lead of said crystal being coupled to said first terminal, said second lead of said crystal being coupled to said second terminal; a first capacitor of capacitance C.sub.o having a first lead and a second lead, said first lead of said first capacitor being coupled to said first terminal; a second capacitor having a first lead and a second lead, said first lead of said second capacitor being coupled to said second terminal; a first resistance element having a first lead and a second lead, said first lead of said first resistance element being coupled to said second terminal; an inverting gain stage having an input lead and an output lead, said input lead of said inverting gain stage being coupled to said first terminal, said output lead of said integrated circuit being coupled to said second lead of said first resistance element; a second resistance element of resistance R.sub.B having a first lead and a second lead, said first lead of said second resistance element being coupled to said first terminal, said second lead of said second resistance element being coupled to said second terminal; and a capacitance element of capacitance C.sub.Badded having a first lead and a second lead, said first lead of said capacitance element being coupled to said input lead of said inverting gain stage, said second lead of said capacitance element being coupled to said output lead of said inverting gain stage, wherein the oscillating frequency of the oscillator circuit is less than 1 MHz, C.sub.Badded .gtoreq.1 pF, C.sub.o .ltoreq.30 pF, and R.sub.B .gtoreq.1 M.OMEGA..
Patent Citations (4)
Non-Patent Literature (4)
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