Phase Locked Loop With Reduced Phase Noise

The present invention relates to locking one frequency signal to another frequency signal, and more particularly to a phase locked loop with reduced phase noise that shifts the energy of the phase noise to higher frequencies.

The conventional way to lock a f*N voltage controlled oscillator (VCO) to an f*M frequency reference, where N and M are integers and f is a common frequency component, is to divide the two frequency signals by the integers N and M respectively and phase lock the resulting f frequency outputs together. If N and M are large, however, this approach may not provide sufficient loop bandwidth to overcome phase noise in the VCO. The loop bandwidth should not be much over f/10.

One prior art way of addressing this loop bandwidth problem is to synthesize an approximation of f*M/P using hardware running on the f*N frequency clock. Here P is a small integer such that M/P<N. For example if f=1 Hz, N=1000, M=1007 and P=4, a 1007/4 (f*M/P)=251.75 Hz approximation is synthesized from the 1000 Hz (f*N) source as follows. On every 1000 Hz clock an accumulator is incremented by 1007. If the result is positive, the accumulator is decremented by P*N=4000 and an output pulse is generated. The 1007 Hz (f*M) clock is divided by 4 and used to lock the 251.75 Hz approximation just generated. With a slow enough loop filter, this gives the desired results. However the phase noise of the 251.75 Hz approximation has significant low frequency energy requiring the slow loop response.

Another prior art way for addressing this loop bandwidth problem is to synthesize a sine wave of frequency f*M/P using hardware running on the f*N frequency clock. In this case P is such that M/P<N/2. The sine wave is synthesized using a read only memory (ROM) look-up table on the upper (or all) bits of a first (only) accumulator, followed by a digital to analog converter and a narrow band pass filter at the frequency f*M/P. The sine wave is squared up and used in a phase comparator as in the above prior art method. This method allows a fast loop response, but requires more analog parts and the phase alignment is very sensitive to the accuracy of the band pass filter components.

What is desired is a phase locked loop with reduced phase noise that allows a fast loop response.

Accordingly the present invention provides a phase locked loop with reduced phase noise by shifting the energy of the phase noise to a higher frequency. An accumulator-based phase locked loop generates an approximation frequency from a clock signal generated by a voltage controlled oscillator (VCO). The approximation frequency is phase compared with a comparable frequency derived from a reference signal to generate an error control signal. The error control signal is used to control the frequency of the clock signal. A second accumulator circuit is inserted between the first accumulator circuit of the phase locked loop and a pulse generator from which the approximation frequency is obtained to integrate the phase error from the first accumulator circuit. The integration serves to shape the phase noise so that the energy is moved to higher frequencies.

The objects, advantages and other novel features of the present invention are apparent from the following detailed description when read in light of the appended claims and attached drawing.

FIG. 1 is a block diagram of a first embodiment for a phase locked loop according to the present invention.

FIG. 2 is a partial block diagram of a second embodiment for the phase locked loop according to the present invention.

FIG. 3 is a block diagram of a third embodiment for the phase locked loop according to the present invention.

Referring now to FIG. 1 a first accumulator 10 includes a first summing circuit 12 with a fixed integer M as one input. The output of the first summing circuit 12 forms one input to a second summing circuit 14, the other input to the second summing circuit being an integer -P*N. The outputs of the first and second summing circuits 12, 14 are input to a multiplexer 16. The output of the multiplexer 16 is clocked into a first register 18, with the output of the register being the other input to the first summing circuit 12.

A reference frequency signal f*M is input to a divider 20 having an integer divisor of P. The output of the divider 20 provides one input to a phase comparator 22. The output of the phase comparator 22 is input to a lowpass loop filter 24, the output of which provides a control voltage for a voltage controlled oscillator (VCO) 26 having an output signal at frequency f*N. The output of the VCO 26 is used to clock the first register 18, and to clock a pulse generator 28 when the pulse generator is enabled. The output of the pulse generator 28 provides the second input to the phase comparator 22. If the sign bit from the output of the first summing circuit 12 is used as the select signal for the multiplexer 16 and the enable signal for the pulse generator 28, then the circuit behaves as the prior art accumulator-based phase locked loop circuit described above.

However the present invention adds a second accumulator circuit 30 having a third summing circuit 32 to which the output of the first summing circuit 12 is input. The output of the third summing circuit 32 is clocked into a second register 34 that is clock enabled by the sign bit of such output and clocked by the output of the VCO 26. This sign bit from the third summing circuit 32 output provides the select signal for the multiplexer 16 and the enable signal for the pulse generator 28. The output of the second register 34 provides the second input to the third summing circuit 32.

Typical phase comparators 22 have a non-linear region near zero in their voltage to delta-phase transfer characteristics. For best results it is desirable to operate in the linear region of the transfer characteristic, so long as the linear region is greater than twice the clock period of the VCO 26. Therefore a d.c. offset may be added to the phase comparator to move the center of the operating region from zero to the middle of one of the linear regions above or below zero. Although this d.c. offset shows up as a phase offset, this is readily compensated for digitally, as is well known to those of ordinary skill in the art.

In operation the present invention shapes the phase noise of the f*M/P approximation from the pulse generator 28 to have more high frequency and less low frequency energy. This allows a higher frequency loop filter 24 to still reject a sufficient amount of phase noise. The second accumulator 30 accumulates the output of the first accumulator 10. The second accumulator 30 is clocked only when the output of the third summing circuit 32 is positive. The decrement by P*N of the first accumulator 10 and the output pulse generation from the pulse generator 28 are both determined by the clocking of the second accumulator 30 rather than the sign of the first accumulator 10. The second accumulator 30 serves to integrate the phase error before it is quantized. Since the quantization introduces white shaped noise on the integral of the phase error, the phase noise is blue shaped, i.e., the phase noise is proportional to frequency, analogous to the noise shaping performed in high speed Sigma Delta analog to digital converters (ADCs). The analog integrator in the phase locked loop, together with the frequency in to phase out integration inherent in a VCO, form a two pole filter that effectively filters out the blue shaped phase error. It should be noted that the output of the accumulator 10 may be taken from either summing circuit 12 or register 18 within the accumulator.

It is possible to use a second order filter in place of the single integrator shown in FIG. 1 to do the noise shaping. This is accomplished as shown in FIG. 2 by adding a third accumulator 40 having a fourth summing circuit 42 and a third register 44 to the circuitry of FIG. 1. The output of summing circuit 32 within the second accumulator 30 is one input to the fourth summing circuit 42 and the output of the third register 44 is the other input. The output of the fourth summing circuit 42 is clocked into the third register 44 by the clock from the VCO 26 when the third register is clock enabled by the sign bit of such output. The sign bit also serves as the switch control for the multiplexer 16, the enable signal for the pulse generator 28 and the clock enable signal for register 34. The operation is the same as for the circuitry of FIG. 1 except that a second integration operation is performed on the phase noise. This results in some more of the phase noise energy being shifted to the higher frequencies. However the linear region of phase comparator 22 must be four times the period of the clock from the VCO 26.

An alternative embodiment to that shown in FIG. 1 is shown in FIG. 3. In this embodiment, using the values disclosed in the Background of the Invention above, a 250 Hz approximation is generated from the f*M reference signal for phase comparison with the output of the VCO 26'. The basic elements are the same as those in FIG. 1, with the identifying numerals primed. The differences are that the inputs to the first accumulator 10' are N at summing circuit 12' and -P*M at summing circuit 14'. Further the clock signal for the two accumulators 10', 30' and the pulse generator 28' is the reference signal f*M, while the output of the VCO 26' is input to the divider 20'. The operation of this circuit is the same as that of FIG. 1, only the approximation frequency that is compared by the phase comparator 22' is different.

Thus the present invention provides a phase locked loop with reduced phase noise by shifting the phase noise energy to a higher frequency through integration using additional accumulator circuits in an accumulator-based phase locked loop.