Pulse Generator

1. Field of the Invention

The present invention relates generally to a pulse generator generating a short pulse having high voltage and a large amount of current. Specifically, the present invention relates to such a pulse generator including a semiconductor switch and a saturable transformer.

2. Description of the Background Art

Generally, apparatus for pulse laser excitation, pulse plasma generation or pulse denitration, is well known as a pulse generator. In order to obtain a desired pulse, discharging switches are used, such as thyratron and trigatron switches, to directly switch high voltage and a large amount of current. A combination of a semiconductor switch and a saturable reactor which functions as a magnetic switch is also utilized.

Additionally, one saturable transformer for raising voltage concurrently with pulse compressing to reduce the load of a switching device is also utilized for pulse generation.

FIG. 5 illustrates a conventional circuit including a saturable reactor. A wave form generated from the circuit is also illustrated in the figure. A plurality of thyristors TH, which function as a semiconductor switch at high voltage, are connected in series. A condenser C.sub.11 connected to the circuit is charged by high voltage. A reactor L is located at the upstream of the condenser C.sub.11. A first current I.sub.1 is generated by a short-circuit from the series circuit including the condenser C.sub.11 and the reactor L. Polarity of the condenser C.sub.11 is inverted thereby to generate voltage twice as that obtained from LC inversion via the series connection of condensers C.sub.11 and C.sub.12. A second current I.sub.2 of pulse compressed is generated by this high voltage, at a circuit including a saturable reactor SR.sub.1, condensers C.sub.11, C.sub.12 and C.sub.2 which are connected in series. Then, A third current I.sub.3 of pulse compressed is generated by the voltage of the condenser C.sub.2, at a circuit including a saturable reactor SR.sub.2, condensers C.sub.3 and C.sub.2 which are connected in series. Finally, a compressed pulse I.sub.4 having large amount of current and high voltage is generated at the circuit including a saturable reactor SR.sub.3 and a discharge tube DT.

However, in the conventional pulse generator including discharging switch devices, the lifetime of the switch devices is very short, i.e., 10.sup.7 to 10.sup.8 pulse. Therefore, when the circuit is operated repeatedly, duration of the switch devices is limited.

Furthermore, in the conventional pulse generator including the combination of the semiconductor switch and the saturable reactor, the withstand voltage of the switch devices is smaller than that of the discharging switch device. Therefore, a plurality of semiconductor switches must be connected in series in order to generate high voltage. This causes the switch circuit to be enlarged because a drive circuit and a snubber circuit are added to each switch device corresponding to the number of series connection. In addition, voltage shared by respective switch becomes unequal if switches timing is upset. On the other hand, the switches may be connected in parallel, however, excess current flows through the switch if switch timing is upset or any one of switches is failed. This causes other switches to be failed.

Utilizing a pulse transformer for voltage raising to reduce the number of the switch device, and reducing the switching voltage to about 1/2 of that of output voltage by a LC inversion circuit are both available, however, the number of the switch device and the number of magnetic pulse compressed are not minimized. This enlarges the circuit compared with that including the discharging switch.

Minimization of the circuit may be done by utilizing single saturable transformer to unite function of voltage raising and magnetic pulse compression. However, the number of turns of the secondary winding of the saturable transformer becomes larger to raise the voltage raising ratio because one transformer unites two functions. This increases inductance causing LC resonance time during pulse compression to be lengthened. Thus, generation of a short pulse is limited. On the other hand, the turns ratio of the winding must be reduced to decrease inductance at the secondary area of the saturable transformer. This causes voltage raising ratio to be reduced and load on the switch device to be increased.

It is therefore a principal object of the present invention to provide a pulse generator which can generate a pulse having high voltage and a large amount of current.

It is another object of the present invention to provide a pulse generator including a semiconductor switch device of which control voltage is reduced.

It is a further object of the present invention to minimize a size of such a pulse generator.

In order to accomplish the aforementioned and other objects, a pulse generator is composed of switch means to switch supply of a first current through a circuit, a first condenser connected to the switch means in series and primarily charged by the first current, voltage raising means having a primary winding serially connected to the first condenser and a secondary winding to obtain voltage output by the first current, magnetic switch means of switchable current flow having a primary winding serially connected to the secondary winding of the voltage raising means and a secondary winding, a second condenser connected to the secondary winding of the magnetic switch means and charged by the output therefrom, and discharging means connected to the second condenser to generate pulse discharge when charged voltage of the second condenser is applied thereto by switching the magnetic switch means.

The switch means can be formed of a series or a parallel connection of plurality of semiconductor switches.

When the switch means is formed of the series connection, the voltage raising means can be formed of a voltage raising transformer. On the other hand, when the switch means is formed of the parallel connection, the voltage raising transformer can be formed of plurality of pulse transformers or saturable transformers corresponding to each connection of the semiconductor switches. The primary and secondary windings of the voltage raising means may be wound at a turns ratio such that high voltage raising ratio is obtainable, wherein the voltage raising means is a voltage raising transformer.

The magnetic switch means can be a saturable transformer having a core which is saturable when the second condenser is completely charged. The number of turns of the secondary winding of the magnetic switch means is reduced to reduce voltage raising ratio thereat.

The present invention will be understood more fully from the detailed description given herebelow and from the accompanying drawings of the preferred embodiments of the invention. However, the drawings are not intended to imply limitation of the invention to a specific embodiment, but are for explanation and understanding only.

In the drawings:

FIG. 1 is a schematic diagram illustrating a circuit of a first embodiment according to the present invention;

FIG. 2 is a schematic diagram illustrating a circuit of a second embodiment according to the present invention;

FIG. 3 is a schematic diagram illustrating a circuit of a third embodiment according to the present invention;

FIG. 4 is a schematic diagram illustrating a circuit of a fourth embodiment according to the present invention; and

FIG. 5 is a schematic diagram illustrating a circuit and a wave form generated therefrom according to prior art.

Referring to FIG. 1, showing a schematic diagram of a first embodiment according to the present invention, a semiconductor switch SW is arranged as an initial step switch including a semiconductor switch device, such as a GTO thyristor, a SI thyristor and a IGBT, and a gate control circuit and a snubber circuit of the switch device. A first saturable reactor SI.sub.1, a first condenser C.sub.0 and a primary winding of a voltage raising transformer T for raising voltage of a circuit, are connected in series. The circuit is connected to the semiconductor switch SW in series. A primary winding of a saturable transformer ST.sub.1 is connected in series to a secondary winding of the voltage raising transformer T, then a secondary winding of the saturable transformer ST.sub.1 is parallelly connected to a series circuit between a second condenser C.sub.1 and a condenser C.sub.p. A discharge tube DT and a second saturable reactor SI.sub.2 are respectively parallelly connected to the condenser C.sub.p.

The first and second saturable reactors SI.sub.1 and SI.sub.2 include magnetic cores having large effective magnetic flux density (.DELTA. B), e.g., a magnetic core formed of ferro-amorphous alloy, ferro-ultramicrocrystal alloy, or cobalt amorphous alloy. The first reactor SI.sub.1 functions as a magnetic assistant to assist operation of the semiconductor switch SW, on the other hand, the second reactor SI.sub.2 functions as means for decreasing pre-pulse generation by bypassing current charged at the second condenser C.sub.1 through the discharge tube DT. Thus, discharge of the condenser C.sub.1 is blocked to prevent generation of pre-pulse at the discharge tube DT. The second reactor SI.sub.2 also supplies current toward the discharge tube DT by blocking discharging current from the condenser C.sub.1. The second saturable reactor SI.sub.2 can be substituted by an air-core.

The first saturable transformer ST.sub.1 includes a magnetic core having high rectangular ratio, e.g., a magnetic core formed of ferro-amorphous alloy, ferro-ultramicrocrystal alloy or cobalt amorphous alloy. The primary winding and the secondary winding of the transformer ST.sub.1 are wound such that the winding ratio is regulated to slightly raise voltage or to decrease voltage. For example, the winding ratio of the transformer ST.sub.1 is prefer to be determined at 1:2.

The condensers C.sub.0, C.sub.1 and C.sub.p can be formed of materials having low inductance and high voltage resistance to generate a short pulse of high voltage. A ceramic condenser or an oil condenser is prefer red to use.

The secondary winding of the voltage raising transformer T is regulated to have larger number of turns than that a of the primary winding thereof such that high voltage raising ratio can be obtained.

The aforementioned embodiment operates as follows.

The first condenser C.sub.0 is charged at the high voltage by D.C. power source DC. Then, the semiconductor switch SW switches current ON to supply the primary current I.sub.0 from the condenser C.sub.0 toward the primary winding of the voltage raising transformer T via the first saturable reactor SI.sub.1 and the semiconductor switch SW.

According to current flow of I.sub.0, the voltage raising transformer T transforms voltage raised corresponding to the turns ratio, e.g., 1:6, toward the secondary winding thereof. The saturable reactor SI.sub.1 functions as a magnetic assistant of the semiconductor switch SW to reduce the switching loss of the switch SW. Thus, the switch SW can be used at current peak higher than that of switching done without the magnetic assistant.

Current I.sub.1 flows at the secondary area of the voltage raising transformer T from the secondary winding thereof toward the first winding of the saturable transformer ST.sub.1. According to current flow of I.sub.1, the saturable transformer ST.sub.1 is operated in non-saturation area. The raised voltage corresponding to the turns ratio of the winding is obtained at the secondary winding of the saturable transformer ST.sub.1. The condenser C.sub.1 is charged by current I.sub.2 in the non-saturation area. During charging, the saturable reactor SI.sub.2 is magnetized in the direction of the current I.sub.2, which is easily flowable. The saturable transformer ST.sub.1 is designed such that the core thereof is saturated when flow of current I.sub.2 is ended. Thus, when flow of current I.sub.2 is ended, the saturable transformer ST.sub.1 is operated in the saturation area. Then, the primary area and the secondary area of the transformer ST.sub.1 are unconnected. Electric charge charged at the condenser C.sub.1 is saturated by the saturable transformer ST.sub.1, therefore, reversed current I.sub.2 ' flows, then electric charge transforms to the condenser C.sub.p. Thus, voltage at the discharge tube DT reaches to the level of generation. The saturable transformer ST.sub.1 does not function as the transformer but as the magnetic switch, i.e., the saturable reactor, to supply current I.sub.2 ' of pulse compressed from the condenser C.sub.1 toward the secondary winding of the transformer ST.sub.1. Short-circuit current is supplied to the discharge tube DT by this current I.sub.2 ', i.e., short pulse having high voltage and large amount of current is supplied to the tube DT.

According to the aforementioned embodiment, the voltage raising transformer T and the saturable transformer ST.sub.1 form a cascade connection. Thus, the voltage raising transformer T exclusively operates as a voltage raising device to raise voltage raising ratio, therefore, desired raised voltage can be obtained. The saturable transformer ST.sub.1 decreases the voltage raising ratio and number of turns of the secondary winding thereof to reduce inductance after saturation. Therefore, the saturable transformer ST.sub.1 exclusively operates as a pulse compressor to raise compressing ratio of pulse length.

Therefore, the semiconductor switch SW can be operated at the lower voltage. Furthermore, high voltage and pulse compressed current can be provided to the loaded area.

Referring now to FIG. 2, showing a second embodiment of the present invention, the same character illustrates the same component as the first embodiment. A plurality of semiconductor switches SW are connected in parallel, wherein each circuit respectively has a condenser C.sub.0 and a saturable reactor SI.sub.0 via a pulse transformer PT having a turns ratio of E1/2:E2/2. The switch can be substituted by GTO. The condensers C.sub.0 are charged and the pulse transformers PT raise pulse voltage of the condensers C.sub.0. The secondary area of pulse transformers are connected in series. A saturable transformer ST, which raises and compresses voltage obtained from the series connection, is connected to the circuit at the downstream of the pulse transformers PT. A second condenser C.sub.1 is connected to the circuit at the downstream of the saturable transformer ST to charge voltage generated at the secondary area of the transformer ST.

When operated, the switches transform electric charge charged at the first condensers C.sub.0 to the second condenser C.sub.1 to supply high voltage pulse to the loaded area connected to the secondary area of the saturable transformer ST. The saturable transformer ST is designed such that the core thereof can be saturated when charging the second condenser C.sub.1 is finished.

Generally, generation of excess voltage and current is caused by timing upset of the semiconductor switches parallelly connected. According to the second embodiment, such problems can be avoided by location of respective pulse transformer against corresponding semiconductor switch. Furthermore, because the circuit is connected in series at the secondary area of the saturable transformer ST, a pulse having high voltage and a large amount of current can be generated from the circuit.

Referring now to FIG. 3, showing a third embodiment of the present invention, the same character illustrates the same component as the first embodiment. A plurality of semiconductor switches SW are connected in parallel via respective saturable transformer ST having a turns ratio of E1/2:E2/2. Each circuit includes a first condenser C.sub.0 and a saturable reactor SI.sub.0. The switch SW can be substituted by GTO. The condensers C.sub.0 are charged and the saturable transformers ST raise or compress pulse voltage of the condensers C.sub.0. The secondary area of saturable transformers ST are connected in series. A second condenser C.sub.1 is connected to the circuit at the downstream of the saturable transformers ST to charge voltage generated at the secondary area of the transformer ST.

When operated, the switches transform electric charge charged at the first condensers C.sub.0 to the second condenser C.sub.1 to supply a high voltage pulse to the loaded area connected to the secondary area of the saturable transformer ST. The saturable transformers ST are designed such that the cores thereof can be saturated when charging the second condenser C.sub.1 is finished.

According to the third embodiment, problems caused by switch timing upset can be avoided by location of respective saturable transformer against corresponding semiconductor switch. Furthermore, because the circuit is connected in series at the secondary area of the saturable transformer ST, pulse a having high voltage and a large amount of current can be generated from the circuit.

Referring now to FIG. 4, showing a fourth embodiment of the present invention, the same character illustrates the same component as the first embodiment. A plurality of semiconductor switches SW are connected in parallel via respective pulse transformer PT having a turns ratio of E1/2:E2/2. Each circuit includes a first condenser C.sub.0 and a saturable reactor SI.sub.0. The switch SW can be substituted by GTO. The condensers C.sub.0 are charged and the pulse transformers ST raise pulse voltage of the condensers C.sub.0. The secondary area of pulse transformers PT are connected in series. A saturable transformer ST, which raises or compresses voltage obtained from the series connection, is connected to the circuit at the downstream of the pulse transformers PT. A second condenser C.sub.1 is parallelly connected to the circuit at the downstream of the saturable transformer ST to charge voltage generated at the secondary area of the transformer ST.

When operated, the switches transform electric charge charged at the first condensers C.sub.0 to the second condenser C1 to supply a high voltage pulse to the loaded area connected to the secondary area of the saturable transformer ST. The saturable transformer ST is designed such that the core thereof can be saturated when charging the second condenser C.sub.1 is finished.

According to the fourth embodiment, problems caused by switch timing upset can be avoided by location of respective pulse transformer against corresponding semiconductor switch. Furthermore, because the circuit is connected in series at the secondary area of the saturable transformer ST, a pulse having high voltage and a large amount of current can be generated from the circuit.

According to the present invention, pulse voltage generated by the semiconductor switch SW and the first condenser C.sub.0 can be raised by location of the voltage raising transformer T or the pulse transformer PT or the saturable transformer ST. The raised voltage is compressed by the saturable transformer ST having smaller number of turns of secondary winding to obtain a short pulse. Therefore, control voltage of the primary step switch can be decreased by the raised voltage of the transformer. Then voltage load on the semiconductor switch can also be reduced. Therefore, connection steps of the semiconductor switch devices can be minimized. Thus, the switch circuit and the adjacent circuit thereof can be simplified and minimized.

Additionally, the pulse voltage raised by the transformer is compressed by the saturable transformer. Therefore, the voltage raising ratio of the saturable transformer and the number of turns of the secondary winding can be minimized. Thus, the core volume of the saturable transformer can be reduced to allow minimization of the saturable transformer.

While the present invention has been disclosed in terms of the preferred embodiment in order to facilitate better understanding of the invention, it should be appreciated that the invention can be embodied in various ways without depending from the principle of the invention. Therefore, the invention should be understood to include all possible embodiments and modification to the shown embodiments which can be embodied without departing from the principle of the inventions as set forth in the appended claims.