Non-Volatile Semiconductor Memory Device Capable of Checking the Threshold Value of Memory Cells

1. A non-volatile semiconductor memory device comprising: a plurality of row address lines; a plurality of digit lines; means for sensing and amplifying signals on said digit lines and outputting said amplified signals; a plurality of memory cells each having a current path with a plurality of terminals, one end of said current path connected to an associated one of said digit lines and having a gate connected to an associated one of said row address lines; and means for discriminating said memory device as a defect by detecting, as an electrically over-erased memory cell, any and all memory cells which will become improperly conductive by parasitic capacitance between a drain of said memory cell and said gate during normal read or write cycles, said discriminating means comprising: read means for applying a same predetermined voltage, which is a positive voltage less than a power source voltage and substantially equal to a minimum normal operating threshold value of those of said memory cells which are electrically erased, to all of said row address lines to read out stored data from said memory cells.

2. The semiconductor memory device according to claim 1, wherein said read means applies the predetermined voltage to all of said row address lines to detect whether or not there is an electrically erased memory cell whose threshold value is lower than the predetermined voltage, thereby to detect if there is an electrically over-erased memory cell.

3. The semiconductor memory device according to claim 2, wherein each of said plurality of memory cells has a floating gate and a current path, and said predetermined value is a value which can prevent non-selected memory cells from erroneous turn on due to parasitic capacitance between a terminal electrode of the current path and the floating gate of the memory cells.

4. The semiconductor memory device according to claim 1, wherein said read means includes: selecting means for sequentially selecting said digit lines; and means for applying the predetermined voltage to control gates of said memory cells commonly connected to the digit line which is selected by said selecting means to read out stored data from said memory cell, and detecting whether or not there is an electrically erased memory cell whose threshold value is lower than the predetermined voltage in order to detect if there is an electrically over-erased memory cell.

5. The semiconductor memory device according to claim 1, wherein said read means includes: selecting means for selecting a digit line; and means for applying said predetermined voltage to control gates of said memory cells commonly connected to said selected digit line to detect if a voltage on said selected digit line drops.

6. The semiconductor memory device according to claim 1, wherein said read means includes: generating means for outputting the predetermined voltage; and means, connected to said row address lines, for applying a read voltage to a selected row address line in read mode, applying a write voltage to a selected row address line in write mode, and applying said predetermined voltage, supplied from said generating means, to all of said plurality of row address lines to detect if there is any electrically over-erased memory cell, when said means receives an address code defining the row address line to be selected and said predetermined voltage.

7. The semiconductor memory device according to claim 1, further comprising erasing means for electrically erasing said plurality of memory cells, after electric erasure of said plurality of memory cells by said erasing means is complete, said read means detects whether or not there is an electrically erased memory cell whose threshold value is lower than said predetermined voltage in order to detect if there is an electrically over-erased memory cell.

8. The semiconductor memory device according to claim 7, wherein said erasing means includes means for repeating electric erasure of all of said plurality of memory cells until all the threshold values of said plurality of memory cells become equal to or smaller than a given value.

9. A non-volatile semiconductor memory device comprising: a plurality of memory cells each for storing data by a change in a threshold value; write means, connected to said plurality of memory cells, for writing predetermined data in a selected memory cell by setting the threshold value of said selected memory cell higher than a predetermined value; erasing means, connected to said plurality of memory cells, for electrically erasing said plurality of memory cells; and means for discriminating said memory device as a defect by detecting, as an electrically over-erased memory cell, any and all memory cells which will become improperly conductive by parasitic capacitance between a drain of said memory cell and said .gate during normal read or write cycles, said discriminating means comprising: checking means, connected to said plurality of memory cells, for checking if the threshold values of those memory cells electrically erased by said erasing means are equal to or greater than a predetermined reference value which is a positive voltage less than a power source voltage and substantially equal to a minimum normal operating threshold value of those of said memory cells which are electrically erased.

10. The semiconductor memory device according to claim 9, wherein said checking means detects whether or not there is an electrically erased memory cell whose threshold value is lower than the reference value in order to detect if there is an electrically over-erased memory cell.

11. The semiconductor memory device according to claim 10, wherein each of said plurality of memory cells has a floating gate and a current path, and said predetermined value is a value which can prevent non-selected memory cells from erroneous turn on due to parasitic capacitance between a terminal of the current path and the floating gate of the memory cells.

12. The semiconductor memory device according to claim 9, wherein said checking means applies a voltage equal to the predetermined reference value to gates of said plurality of memory cells to check if there is a memory cell which is turned on in order to detect if there is an electrically over-erased memory cell.

13. The semiconductor memory device according to claim 9, wherein said erasing means includes means for repeating electric erasure of all of said plurality of memory cells until all the threshold values of said plurality of memory cells become equal to or smaller than a given value.

14. A memory cell checking method comprising: an erasing step of electrically erasing a plurality of memory cells of a memory chip; a checking step of checking if threshold values of said memory cells are equal to or above a reference value to detect an electrically over-erased memory cell, said checking step being performed after completion of said erasing step; and a step of discriminating said memory chip as a defect when a memory cell whose threshold value is below said reference value, which is a positive voltage less than a power source voltage and substantially equal to a minimum normal operating threshold value of those of said memory cells which are electrically erased, is detected in said checking step.

15. The memory cell checking method device according to claim 14, wherein each of said plurality of memory cells has a floating gate and a current path, and the reference value is a value which can prevent non-selected memory cells from erroneous turn on due to parasitic capacitance between a terminal of the current path and the floating gate of the memory cells.

16. A memory cell checking method comprising: a writing step for writing data in a plurality of memory cells to be electrically erased, to set a threshold value of each of said memory cells equal to or greater than a predetermined value, said plurality of memory cells being included in a memory chip and storing data by changing the threshold values; an erasing step of electrically erasing said plurality of memory cells to be erased to which data are electrically written by said writing step; an erase verify step for checking the threshold values of said electrically erased memory cells and repeating said erasing step until the threshold value of all of said plurality of memory cells to be erased become equal to or below a first positive value; a checking step to be performed after detecting that said threshold value of all of said plurality of memory cells to be erased have become equal to or below said first positive value, to check if the threshold values of said plurality of memory cells are equal to or above a second positive value substantially equal to a minimum normal operating threshold value of those of said memory cells which are electrically erased and smaller than the first positive value to detect an electrically over-erased memory cell; and a step of discriminating said memory chip as a defect when a memory cell whose threshold value is below said second positive value is detected as electrically over-erased in said checking step.

17. The memory cell checking method device according to claim 16, wherein each of said plurality of memory cells has a floating gate and a current path, and the reference value is a value which can prevent non-selected memory cells from erroneous turn on due to parasitic capacitance between a terminal of the current path and the floating gate of the memory cells.

18. A memory cell checking method comprising the steps of: providing an electrically erasable and programmable non-volatile semiconductor memory device which includes a plurality of MOS transistor memory cells each having a source, a drain, a control gate and a floating gate, the control gate of each of said MOS transistor memory cells being connected to an associated one of address lines and the drain of each of said MOS transistor memory cells being connected in common to a digit line, one of said MOS transistor memory cells being in a data-write operation supplied with a set of writing voltages through an associated one of said address lines and said digit line while applying a first voltage to the control gate of each of remaining ones of said MOS transistor memory cells through remaining ones of said address lines, said one of said MOS transistor memory cells being thereby changed to have a first threshold value higher than a predetermined threshold value, and each of said remaining ones of said MOS transistor memory cells thereby receiving a second voltage at the floating gate thereof due to capacitance-coupling between the drain and the floating gate, said second voltage being higher than said first voltage; writing a data into each of said MOS transistor memory cells by supplying said set of writing voltages thereto, each of said MOS transistor memory cells being thereby changed to have said first threshold value; performing an erasing-verifying operation in which each of said MOS transistor memory cells is applied with a set of erasing voltages, simultaneously, for a predetermined time period, and each of said MOS transistor memory cells is then supplied with a set of verifying voltages to check if all said MOS transistor memory cells have a second threshold value smaller than said predetermined threshold value, said erasing-verifying operation being repeated until all the MOS transistor memory cells have said second threshold value; and supplying a third voltage that is substantially equal to said second voltage to the control gate of each of said MOS transistor memory cells through an associated one of said address line to thereby check if said MOS transistor memory cell is made conductive by said third voltage.