Programmable Microcomputer Oscillator Circuitry With Synchronized Fast and Slow Clock Output Signal

1. In a CMOS integrated circuit microcomputer, circuitry adapted to solving a problem of high power dissipation in the CMOS integrated circuit microcomputer, the circuitry including: fast clock oscillator circuitry having a programmed stop input and providing a fast clock signal of a first frequency on a fast clock output; slow clock oscillator circuitry, unsynchronized with the fast clock oscillator, and providing a slow clock signal of a second frequency that is unsynchronized with and substantially lower in frequency than the fast clock signal on a slow clock output; a synchronizing circuit having a first input connected to the fast clock output of the fast clock oscillator circuit and a second input connected to the slow clock output of the slow clock oscillator, a clock select input, and a clock enable output conductor and adapted to produce a clock enable signal on the clock enable output conductor, the clock enable signal being synchronized with the fast clock signal produced by the fast clock oscillator circuit if the clock select input is at a first logic level, the clock enable signal being synchronized with the slow clock signal produced by the slow clock oscillator if the clock select input is at a second logic level; and a logic gating circuit coupled to the clock enable output conductor and responsive to the clock enable signal and coupled to the fast clock output of the fast clock oscillator and the slow clock output of the slow clock oscillator and adapted to produce a selectable frequency clock signal that has the first frequency and is synchronized with the fast clock signal produced by the fast clock oscillator circuit if a clock select signal on the clock select input is at a first logic level and has the second frequency and is synchronized with the slow clock signal produced by the slow clock oscillator if the clock select signal is at a second logic level, switching of the selectable frequency clock signal from the first frequency to the second frequency occurring so that a delay between a last pulse of the first frequency an a first pulse of the second frequency is less than approximately half of a period of the second frequency, the programmed stop input allowing the fast clock oscillator circuitry to be stopped under program control during low frequency, lower power operation of the CMOS integrated microcomputer to reduce power consumed by the fast clock oscillator circuitry, to thereby effectuate switching the CMOS integrated circuit microprocessor from high frequency, high power operation to low frequency, low power operation in response to the clock select signal and in response to the programmed stop input.

2. The oscillator circuitry of claim 1 wherein the synchronizing circuit includes four gated latch circuits connected in series to allow an internal signal propagation in response to the fast clock signal to undergo enough transitions to occupy one time interval at least equal to the width of a pulse of the slow clock signal.