Data Conversion Method and Recording and Reproduction Apparatus

1. Field of the Invention

The present invention relates to a data conversion method for converting digital data into signals suitable for a recording or transmission system used for recording or transmitting the digital data, and also relates to a magnetic recording and reproduction apparatus employing the same data conversion method.

2. Description of the Related Art

Generally, when transmitting data through a transmission channel, it is required to use the transmission channel effectively and transmit data with minimum data degradation during transmission. The achieve this, various data conversion methods have been proposed, depending on the kind of the information source and the characteristics of the transmission channel. On the other hand, the characteristics required of the data conversion method vary according to the characteristics of the transmission channel. One example is a transmission channel system having a band-pass characteristic, one such system being a magnetic recording and reproduction system.

Specifically, in a magnetic recording and reproduction apparatus such as a rotary head type VTR, since signals for recording or reproduction are passed through a rotary transformer, head amplifier capacitors, etc., the DC component and low-frequency components are cut off. If the DC component and low-frequency components cannot be recorded or reproduced, waveform distortion and fluctuations in the DC level will be caused in the reproduced digital signal, which tends to result in digital signal errors. To avoid this, data conversion is performed on the digital signal to be recorded so that the digital signal, when recorded or reproduced, contains as little DC component and low-frequency components as possible. Such a data conversion method is generally known as a DC-free data conversion method. Examples of the DC-free conversion method include an 8-10 modulat on method, such as described in Japanese Patent Application Laid-Open Nos. 56-19506(1981) and 60-48646(1985), "THE DAT CONFERENCE STANDARD" (issued in June 1987), etc., and an 8-14 modulation method, such as disclosed in Japanese Patent Application Laid-Open Nos. 61-30818 (1986) and 3234146(1991), etc.

The 8-10 modulation method is a data conversion method for converting 8-bit digital data (dataword) into 10-bit digital data (codeword), and the 8-14 modulation method is a data conversion method for converting an 8-bit dataword into a 14-bit codeword. These DC-free data conversion methods convert data so that the DSV (digital sum variation) becomes zero.

The DSV represents the value of the integral of binary levels of 1 (high level) and 0 (low level) which are represented by +1 (positive) and -1 (negative), respectively. The DSV has a value taken over a given period at a given time. When the DSV is obtained for a continuing binary signal, if the DSV increases or decreases infinitely, the binary signal has a DC component, and if the DSV is finite, then the binary signal does not have a DC component. A CDS (codeword digital sum) represents a DSV from the beginning to the end of a codeword.

There are three kinds of codewords: a codeword with CDS<0, a codeword with CDS=0, and a codeword with CDS<0. For example, in the data conversion method disclosed in Japanese Patent Application Laid-Open No. 59-123343(1984), codewords with CDS=0 are mapped in one-to-one corresponding relationship to datawords, while codewords with CDS>0 and CDS<0 are paired together and each pair is mapped in corresponding relationship to one dataword. By monitoring the DSV, a codeword with CDS.ltoreq.0 is selected when DSV>0, and a codeword with CDS.gtoreq.0 is selected when DSV<0. When DSV=0, an appropriate codeword is selected.

For magnetic recording and reproduction apparatus such as rotary head type VTRs, it is desirable that Tw.times.Tmin be large and yet high-density recording be made possible (Tw is the detection window width that represents the margin against symbol errors when the time base for the reproduced signal becomes unstable due to jitter, and Tmin is the minimum spacing between magnetic reversals that corresponds to the resolution of the recording system). Furthermore, it is desirable that the peak shift due to intersymbol interference be small and also that Tmax/Tmin (where Tmax is the maximum spacing between magnetic reversals) be small for improved overwrite characteristics due to signal overwriting. It is also desired that Tmin be large in order to minimize the high-frequency components. FIG. 1 shows the values of Tmin, Tmax, Tmax/Tmin, Tw, Tw.times.Tmin, and DSVmax in 8-10 modulation and 8-14 modulation.

FIG. 2 is a diagram showing the configuration of a modulation circuit employing the 8-10 modulation method, FIG. 3 is a diagram for explaining the operation of the same, and FIG. 4 is a diagram showing a part of a data conversion table. In FIG. 2, the reference numeral 70 designates an encoder which accepts 8-bit digital data and a 1-bit table selection signal (Q') at its inputs and which bit signal (Q) for selecting the table for the next codeword; and 71 indicates a flip-flop for delaying the codeword table selection signal by one dataword. The encoder 70 includes a read-only memory (ROM) or the like that holds the contents of the data conversion table shown in FIG. 4; in the table, codewords with CDS=0 are mapped in one-to-one corresponding relationship to 256 datawords from "00" to "FF" hex, while in the case of codewords of CDS.noteq.0, pairs of codewords, one with CDS=+2 and the other with CDS=-2, are each mapped in corresponding relationship to one dataword, the table for Q'=-1 consisting of codewords with CDS =+2 and the table for Q'=+1 consisting of codewords with CDS=-2. The table selection signal Q is used to select the CDS (the table) of the direction that suppresses the divergence of charges in the code sequence.

Next, the operation of the above circuit will be described with reference to FIGS. 2 and 3. As shown in FIG. 3, an 8-bit dataword "FF" first input to the encoder 70 has a table selection signal Q'=-1, and consequently, the encoder 70 outputs a 10-bit codeword "1111101010" with CDS=+2 corresponding to "FF" for Q'=-1. At the same time, the table selection signal Q=-1 is outputted for table selection for the next codeword. This 10-bit parallel signal is then converted to a serial signal with MSB as the leading bit, after which the signal is NRZI-modulated. As a result, the DSV value at the end of the codeword becomes +2.

Next, when "00" is inputted to the encoder 70, the encoder 70 outputs Q=1 together with a 10-bit signal "101010101" with CDS=0 corresponding to "00" for Q'=-1 delayed by one symbol from the immediately preceding output Q=-1. As a result, the DSV value at the end of the codeword after NRZI modulation remains at +2. Then, when "FF" is inputted to the encoder 70, the encoder 70 outputs Q=-1 together with a 10-bit signal with CDS=-2 corresponding to "FF" for Q'=1. As a result, the DSV at the end of the codeword after NRZI modulation becomes zero. In this manner, for each 8-bit dataword inputted to the encoder 70, a codeword to be output is selected from the table for either Q'=-1 or Q'=1 corresponding to the dataword on the basis of the immediately preceding table selection signal output. Consequently, the value of the DSV at the end of each codeword after NRZI modulation is limited to 0, +2 or -2 . This indicates that the DSV divergence is suppressed, thus realizing DC-free data conversion that has no DC component.

In the data conversion method of the prior art, as described above, codewords with CDS=0 are mapped in one-to-one corresponding relationship to datawords; the problem here is that when DSV>0 or DSV<0, if a dataword corresponding one-to-one to a codeword with CDS=0 is input, the DSV cannot be converged fast enough.

In the prior art 8-10 modulation method, since Tmin is as small as 0.8 data clock cycle (T), the intersymbol interference is large, and since Tw.times.Tmin shows a relatively small value of 0.64, there remains some problem in realizing high-density recording. On the other hand, in the prior art 8-14 modulation method, since Tmax/Tmin shows a relatively large value of 3.5, the prior art has had the problem that the peak shift due to intersymbol interference tends to occur and the signal overwrite characteristics tend to degrade.

It is an object of the present invention to provide a data conversion method capable of further suppressing the low-frequency components by reducing the probability of occurrence of codewords whose DSV in absolute value terms is large.

It is another object of the invention to provide a data conversion method capable of preventing the occurrence of peak shift due to intersymbol interference, having good overwrite characteristics and achieving high-density recording, and a recording and reproduction apparatus for recording codewords generated by same data conversion method and for reproducing the original datawords from the recorded codewords.

According to the first data conversion method of the invention, for codewords with CDS=0, codewords with CDS>0 and codewords with CDS<0 are paired together, and when converting a dataword into a codeword, the matching codeword is selected while monitoring the condition of the DSV. More specifically, instead of mapping codewords with CDS=0 in one-to-one relationship to datawords, as many codewords with CDS.noteq.0 as the number of codewords allows are paired between opposite polarities and are mapped to datawords corresponding to the codewords with CDS=0, and the codewords are selected so that the DSV after NRZI modulation becomes zero. This enables the DSV to be converged fast enough, reduces the DC component and low-frequency components after encoding, and realizes transmission with minimum probability of symbol error even with a transmission channel and recording apparatus that are not capable of transmitting DC component.

According to the second data conversion method of the invention, a codeword to be generated for output is selected, based on the least significant bit of the codeword generated immediately preceding the current dataword about to be converted and also on the current dataword about to be converted and the next dataword to be converted. In the second data conversion method, a conversion table in which a plurality of codewords having different CDSs or different least significant bits are mapped to a single dataword is provided, and the DSV expected at the end of a codeword corresponding to the next dataword to be converted is calculated for each of two cases, i.e. a case where a first codeword in the conversion table is selected and a case where a second codeword in the conversion table is selected, and based on the thus calculated DSV, a codeword corresponding to the current dataword is selected from the conversion table. Alternatively, in the second data conversion method, different conversion tables are used for codeword selection, depending on the DSV at the end of a codeword corresponding to the immediately preceding dataword and on the level at the end of the immediately preceding codeword.

Thus, according to the second data conversion method, the DSV is finite and DC-free modulation is realized; furthermore, Tmax and Tmax/Tmin are smaller than those obtained with the prior art 8-14 modulation method, while Tmin and Tw.times.Tmin are larger than those obtained with the prior art 8-10 modulation method. Accordingly, this data conversion method of the invention is much less likely to cause a peak shift due to intersymbol interference, provides good overwrite characteristics, and permits high-density recording.

The recording and reproduction apparatus of the invention employs the second data conversion method described above. With this apparatus, if errors occur in the reproduction signal, the DSV value in the reproduction signal can be restored to the correct value, and codewords generated by the second data conversion method can be decoded into the original datawords.

The above and further objects and features of the invention will more fully be apparent from the following detailed description with accompanying drawings.

FIG. 1 is a diagram showing a comparison of modulation parameters between a prior art 8-14 modulation method, a prior art 8-10 modulation method, and a data conversion method of the present invention;

FIG. 2 is a block diagram showing a prior art, data conversion apparatus;

FIG. 3 is a diagram for explaining the operation of the prior art data conversion apparatus;

FIG. 4 is a diagram showing a conversion table used in the prior art data conversion apparatus;

FIG. 5 is a diagram showing a table in which 10-bit codewords are classified by CDS;

FIG. 6 is a diagram showing a table in Embodiment 1;

FIG. 7 is a diagram showing a table in Embodiment 1;

FIG. 8 is a diagram showing a table in Embodiment 1;

FIG. 9 is a diagram showing a table in Embodiment 1;

FIG. 10 is a diagram showing a table in Embodiment 1;

FIG. 11 is a diagram showing a table in Embodiment 1;

FIG. 12 is a diagram showing a table in Embodiment 1;

FIG. 13 is a diagram showing a table in Embodiment 1;

FIG. 14 is a diagram showing a DSV change during data conversion;

FIG. 15 is a diagram showing the relationship between Q1/Q2, input/output polarity after NRZI, and CDS in group A;

FIG. 16 is a diagram showing the relationship between Q1/Q2, input/output polarity after NRZI, and CDS in group B;

FIG. 17 is a diagram showing the relationship between Q1/Q2, input/output polarity after NRZI, and CDS in group C;

FIG. 18 is a diagram showing the relationship between Q1/Q2, input/output polarity after NRZI, and CDS in group D;

FIG. 19 is a diagram showing the configuration of a data conversion apparatus for implementing the data conversion method of Embodiments 1 and 2;

FIG. 20 is a diagram showing a table in Embodiment 2;

FIG. 21 is a diagram showing a table in Embodiment 2;

FIG. 22 is a diagram showing a table in Embodiment 2;

FIG. 23 is a diagram showing a table in Embodiment 2;

FIG. 24 is a diagram showing a table in Embodiment 2;

FIG. 25 is a diagram showing a table in Embodiment 2;

FIG. 26 is a diagram showing a table in Embodiment 2;

FIG. 27 is a diagram showing a table in Embodiment 2;

FIGS. 28A and 28B are diagrams showing the numbers of codewords in Embodiment 3;

FIG. 29 is a diagram showing the numbers of codewords according to the state at codeword end in Embodiment 3;

FIG. 30 is a diagram showing the numbers of codewords according to the state at codeword end in Embodiment 3;

FIG. 31 is a diagram showing the numbers of codewords according to the state at codeword end in Embodiment 3;

FIG. 32 is a diagram showing the numbers of codewords according to the state at codeword end in Embodiment 3;

FIG. 33 is a diagram for deriving a conversion table T0 in Embodiment 3;

FIG. 34 is a diagram for deriving a conversion table T1 in Embodiment 3;

FIG. 35 is a diagram for deriving a conversion table T2 in Embodiment 3;

FIG. 36A and 36B are diagrams for deriving a conversion table T3 in Embodiment 3;

FIG. 37 is a diagram for deriving a conversion table T01 in Embodiment 3;

FIG. 38 is a diagram for deriving a conversion table T11 in Embodiment 3;

FIG. 39 is a diagram for deriving a conversion table T21 in Embodiment 3;

FIG. 40 is a diagram for deriving a conversion table T31 in Embodiment 3;

FIG. 41 is a diagram showing the conversion tables T0 and T1 in Embodiment 3;

FIG. 42 is a diagram showing the conversion tables T0 and T1 in Embodiment 3;

FIG. 43 is a diagram showing the conversion tables T0 and T1 in Embodiment 3;

FIG. 44 is a diagram showing the conversion tables T0 and T1 in Embodiment 3;

FIG. 45 is a diagram showing the conversion tables T0 and T1 in Embodiment 3;

FIG. 46 is a diagram showing the conversion tables T0 and T1 in Embodiment 3;

FIG. 47 is a diagram showing the conversion tables T2 and T3 in Embodiment 3;

FIG. 48 is a diagram showing the conversion tables T2 and T3 in Embodiment 3;

FIG. 49 is a diagram showing the conversion tables T2 and T3 in Embodiment 3;

FIG. 50 is a diagram showing the conversion tables T2 and T3 in Embodiment 3;

FIG. 51 is a diagram showing the conversion tables T2 and T3 in Embodiment 3;

FIG. 52 is a diagram showing the conversion tables T2 and T3 in Embodiment 3;

FIG. 53 is a diagram showing the conversion tables T01 and T11 in Embodiment 3;

FIG. 54 is a diagram showing the conversion table T21 in Embodiment 3;

FIG. 55 is a diagram showing the conversion table T31 in Embodiment 3;

FIG. 56 is a diagram showing a conversion table selection method in Embodiment 3;

FIG. 57 is a diagram showing the configuration of a data conversion apparatus for implementing the data conversion method of Embodiment 3;

FIG. 58 is a diagram showing the configuration of a dummy code discriminator in the data conversion apparatus shown in FIG. 57;

FIG. 59 is a diagram showing the configuration of a subcode selection determiner in the data conversion apparatus shown in FIG. 57;

FIG. 60 is a timing chart for explaining in detail the operation of the data conversion apparatus shown in FIG. 57;

FIG. 61 is a timing chart for explaining in detail the operation of the data conversion apparatus shown in FIG. 57;

FIG. 62 is a timing chart for explaining in detail the operation of the data conversion apparatus shown in FIG. 57;

FIG. 63 is a timing chart for explaining in detail the operation of the data conversion apparatus shown in FIG. 57;

FIG. 64 is a diagram showing the configuration of a decoding system in a recording and reproduction apparatus of Embodiment 4 in which the data conversion method of Embodiment 3 is employed;

FIG. 65 is a diagram showing the configuration of a decoding system in a recording and reproduction apparatus of Embodiment 5 in which the data conversion method of Embodiment 3 is employed;

FIG. 66 is a diagram showing the configuration of another data conversion apparatus (Embodiment 6) for implementing the data conversion method of Embodiment 3;

FIG. 67 is a diagram showing the configuration of a table determiner in the data conversion apparatus shown in FIG. 66;

FIG. 68 is a diagram showing the configuration of a DSV reset data discriminator in the data conversion apparatus shown in FIG. 66;

FIG. 69 is a timing chart for explaining in detail the operation of the data conversion apparatus shown in FIG. 66;

FIG. 70 is a timing chart for explaining in detail the operation of the data conversion apparatus shown in FIG. 66;

FIG. 71 is a timing chart for explaining in detail the operation of the data conversion apparatus shown in FIG. 66;

FIG. 72 is a timing chart for explaining in detail the operation of the data conversion apparatus shown in FIG. 66;

FIG. 73 is a diagram showing an example of a block format of a codeword sequence in the data conversion apparatus of Embodiment 6;

FIG. 74 is a diagram showing an example of DSV reset data in the data conversion apparatus of Embodiment 6;

FIG. 75 is a diagram for explaining the method of using the DSV reset data in the data conversion apparatus of Embodiment6;

FIG. 76 is a diagram showing the configuration of a decoding system in a recording and reproduction apparatus of Embodiment 7 in which the data conversion method of Embodiment 6 is employed;

FIG. 77 is a timing chart for explaining in detail the operation of the recording and reproduction apparatus shown in FIG. 76;

FIG. 78 is a timing chart for explaining in detail the operation of the recording and reproduction apparatus shown in FIG. 76;

FIG. 79 is a diagram showing the configuration of a decoding system in a recording and reproduction apparatus of Embodiment 8 in which the data conversion method of Embodiment 6 is employed;

FIG. 80 is a diagram showing the configuration of another data conversion apparatus (Embodiment 9) for implementing the data conversion method of Embodiment 3;

FIG. 81 is a diagram showing an example of a block format of a codeword sequence in the data conversion apparatus of Embodiment 9;

FIG. 82 is a diagram showing an example of ID1 codeword data in the data conversion apparatus of Embodiment 9;

FIG. 83 is a timing chart for explaining in detail the operation of the data conversion apparatus shown in FIG. 80;

FIG. 84 is a timing chart for explaining in detail the operation of the data conversion apparatus shown in FIG. 80;

FIG. 85 is a timing chart for explaining in detail the operation of the data conversion apparatus shown in FIG. 80;

FIG. 86 is a diagram showing the configuration of a decoding system in a recording and reproduction apparatus of Embodiment 10 in which the data conversion method of Embodiment 9 is employed;

FIG. 87 is a diagram showing the configuration of a reset, data generator in the decoding system of the recording and reproduction apparatus shown in FIG. 86;

FIG. 88 is a timing chart for explaining in detail the operation of decoding in the decoding system of the recording and reproduction apparatus shown in FIG. 86;

FIG. 89 is a timing chart for explaining in detail the operation of decoding in the decoding system of the recording and reproduction apparatus shown in FIG. 86;

FIG. 90 is a diagram showing the configuration of a decoding system in a recording and reproduction apparatus of Embodiment 11 in which the data conversion method of Embodiment 9 is employed.

The present invention will now be described in detail below with reference to the drawings illustrating the preferred embodiments.

Embodiment 1 of the invention hereinafter described concerns an example in which NRZI modulation is performed for conversion of a dataword of m=8 bits into a codeword of n=10 bits. There are two types of NRZI modulation: one involving a reversal of polarity at the center of a bit cell and the other involving a reversal of polarity at the start of a bit cell. In NRZI modulation, the polarity reversal bears significance, and the level during the interval between polarity reversals is constant. Embodiment 1 can be applied to either type of NRZI modulation. The following description deals with the type of NRZI modulation wherein a polarity reversal occurs at the start of a bit cell.

Ten-bit codewords are classified according to the CDS. Here, in order to suppress the low-frequency components, the number of successive 0s is limited to 3, with a maximum sequence of two 0s at the start of a codeword and a maximum sequence of one 0 at the end of a codeword. It is also assumed that the polarity of the NRZI waveform immediately preceding any given codeword is negative. When classified according to the above condition, there are six codewords with CDS=+6, 55 codewords with CDS=+4, 151 codewords with CDS=+2, 192 codewords with CDS=0, 125 codewords with CDS=-2, 33 codewords with CDS=-4, and one codeword with CDS=-6. Further, a maximum or a minimum value of the DSV change within each codeword is determined. The results are shown in FIG. 5.

We will now explain how the codewords are mapped in correspondence with the datawords. There are 256 datawords of m=8. First, all the codewords with CDS=0 are mapped one-to-one to datawords. Then, the codewords with the smaller CDS in absolute value terms, i.e. codewords with CDS=+2 and codewords with CDS=-2, are paired together and are sequentially mapped to the remaining 64 datawords. Now, there remain 87 codewords with CDS=+2 and 62 codewords with CDS=-2. From these codewords whose CDS is 2 in absolute value terms, 62 pairs of codewords of opposite polarity are formed. Of these pairs, the pair containing the codeword with CDS=-2 and having a maximum DSV value of 3 is discarded. The remaining 61 pairs are further paired with codewords with CDS=0. In this case, the 61 pairs are paired with codewords with CDS=0 in decreasing magnitude of the DSV change. As can be seen from FIG. 5, the DSV changes within a codeword even if its CDS is 0. That is, the 61 pairs are sequentially paired with the codewords having larger maximum or minimum values of the DSV change in absolute value terms, that is, in the order of 4, 3, and 2. The results of the codeword mapping thus performed are shown in FIGS. 6 to 13.

In FIGS. 6 to 13, group A is a group that is selected when the DSV immediately preceding the codeword to be selected is 0 and the polarity of the NRZI-modulated word immediately preceding the codeword is negative, while group B is a group that is selected when the DSV immediately preceding the codeword to be selected is 0 and the polarity of the NRZI-modulated word immediately preceding the codeword is positive. Group C is a group that is selected when the DSV immediately preceding the codeword to be selected is -2 and the polarity of the NRZI-modulated word immediately preceding the codeword is negative or when the DSV is +2 and the polarity is positive, while group D is a group that is selected when the DSV immediately preceding the codeword to be selected is -2and the polarity of the NRZI-modulated word immediately preceding the codeword is positive or when the DSV is +2 and the polarity is negative.

Next, we will explain the change of the DSV value. Refer to FIG. 14, where datawords are successively converted to codewords. Here, when a codeword corresponding to a dataword a -1 is outputted and the CDS of that codeword is -2, if the DSV at the time of outputting a codeword corresponding to the next dataword a is 0 and the polarity after NRZI modulation is negative, then a codeword j in group A is selected as the codeword corresponding to the dataword a. For any codeword in group A, the CDS is 0 or +2. If the CDS of the codeword j is 0 and the polarity at the end of the codeword j after NRZI modulation is negative, then group A is selected when selecting a codeword j+1 corresponding to a dataword a +1; if the CDS of the codeword j is 0 and the polarity is positive, then group B is selected. On the other hand, if the CDS of the codeword j is +2 and the polarity at the end of the codeword j after NRZI modulation is negative, then a codeword in group D is selected as the codeword j+1; if the CDS of the codeword j is +2 and the polarity is positive, then group C is selected.

In other words, when the DSV is 0, a codeword with CDS =0 is selected with a probability of 192/256, and a codeword with CDS=2 or CDS=-2 is selected with a probability of 64/256. When DSV is +2, a codeword with CDS=-2 is selected with a probability of 125/256, and a codeword with CDS=0 is selected with a probability of 131/256. When DSV is -2, a codeword with CDS=+2 is selected with a probability of 125/256, and a codeword with CDS=0 is selected with a probability of 131/256. As a result, the change of the DSV is limited to within the range of -2.ltoreq.DSV.ltoreq.2 between codewords, which enables the DSV to converge to 0 fast enough.

Next, explanation will be given of Q1 and Q2. Group A is selected when the polarity of the previous codeword after NRZI modulation is positive and the DSV is 0; that is, the DSV and the polarity at the end of a selected codeword determine the codeword group from which the next codeword is selected. The DSV value at the end of a selected codeword is obtained by adding the CDS of the selected codeword to the DSV preceding the selection of the codeword. Accordingly, when the CDS of the selected codeword is 0 and the polarity is negative, group A is selected for the next codeword, and when the CDS is 0 and the polarity is positive, group B is selected. On the other hand, when the CDS is 2 and the polarity is positive, group C is selected, and when the CDS is 2 and the polarity is negative, group D is selected. This is summarized in FIG. 15. The situation is the same for group B, group C, and group D, which are summarized in FIGS. 16 to 18, respectively.

FIG. 19 is a block diagram showing an example of an encoding circuit used for dataword-to-codeword conversion as described above. In FIG. 19, the numeral 1 indicates a data input terminal via which 8-bit parallel data as a dataword is inputted. The parallel data is fed via the data input terminal 1 to a ROM table 2 that contains a conversion table. To the ROM table 2 is connected a delay circuit 3 for delaying Q1, Q2 by one dataword. The ROM table 2 outputs 10-bit parallel data, a codeword corresponding to the input dataword, which is fed to a parallel-serial converter 4. The parallel-serial converter 4 converts the input parallel data into serial data which is fed to an NRZI modulator 5. The NRZI modulator 5 NRZI-modulates the input data before it is output through an outputted terminal 6.

Next, the circuit operation for encoding will be described. In FIG. 19, 8-bit parallel data a (dataword) is inputted via the data input terminal and applied to address terminals of the ROM table 2. At the same time, the outputs Q1, Q2 from parallel data a -1 (the immediately-preceding dataword) are applied via the delay circuit 3 to address terminals of the ROM table 2. Ten-bit parallel data (codeword) corresponding to the dataword a is outputted from the ROM table 2 and fed to the parallel-serial converter 4, while at the same time, two bits, Q1 and Q2, are fed into the delay circuit 3. The 10-bit codeword is outputted as serial data from the parallel-serial converter 4, and is fed to the NRZI modulator 5 where it is NRZI-modulated and then outputted through the output terminal 6.

For decoding in Embodiment 1, the circuit configuration will not be described here, but it will suffice to say that an 8-bit dataword is outputted for each 10-bit codeword, the dataword being determined uniquely for each codeword.

Embodiment 2, as in Embodiment 1, concerns an example in which an 8-bit dataword is converted to a 10-bit codeword and NRZI modulation is performed. In Embodiment 2, of the codewords classified by CDS as shown in FIG. 5, all the codeword is that fall within -4.ltoreq.CDS.ltoreq.4 are used.

We will explain how the codewords are mapped. First, all the 192 codewords with CDS=0 are mapped to datawords. For the remaining 64 datawords, codewords with CDS=2 and codewords with CDS=-2 are paired together and mapped to these datawords. Of the codewords that fall within 4.gtoreq.CDS.gtoreq.2, 142 codewords are mapped to the datawords to which the codewords with CDS=0 were mapped. Furthermore, of the codewords that fall within -4.ltoreq.CDS.ltoreq.-2, 95 codewords are mapped to the datawords to which the codewords with CDS=0 were mapped. The codewords thus mapped are shown in FIGS. 20 to 27. In FIGS. 20 to 27, group A, group B, group C, and group D are selected in the same manner as described in Embodiment 1. The encoding and decoding circuits used are the same as those for Embodiment 1.

Embodiment 3 hereinafter described deals with the construction of a codeword, with dataword m=8 bits, codeword n=14 bits, and Tmax/Tmin=3.0. In this case, d=1 (d is the minimum number of 0s between an arbitrary "1" and the next "1"), and k=5 (k is the maximum number of 0s between an arbitrary "1" and the next "1"). The NRZI(F) rule is used to construct the codeword.

To achieve such data conversion, for each codeword the maximum number of successive 0s ("0" run length) on the LSB (least significant bit) side is set to 2, and within the codeword, the minimum number of successive 0s is set to 1 and the maximum number is set to 5. In this case, the "0" run length condition for the MSB (most significant bit) side that can satisfy d=1 and k=5 is provided in two ways: the "0" run length of 0 at minimum and 3 at maximum that allows codeword connection when the LSB of the immediately-preceding codeword is "0", and the "0" run length of 1 at minimum and 5 at maximum that enables codeword connection when the LSB of the immediately-preceding codeword is "1". The codewords are obtained in the numbers shown in FIGS. 28A and 28B.

To form DC-free codewords by controlling and suppressing the DSV divergence at each codeword end, codewords of opposite CDS polarities are paired together to provide 2.sup.8 pairs (256 pairs) corresponding to 8-bit data. The codewords thus obtained are divided into two groups to construct respective conversion 'tables. When forming a codeword sequence, the conversion tables are selected appropriately so that the CDSs of the selected codewords are in the direction that reduces the DSV value. Here, the codewords with CDS=0 can be used in either of the two groups.

To construct the codewords as described above, codewords with CDS.gtoreq.0 and codewords with CDS.ltoreq.0 are selected in pairs to form 256 pairs from each of the codeword groups shown in FIGS. 28A and 28B: FIG. 28A shows a group of codewords, with the MSB-side "0" run length of 3 at maximum, that can be used when the LSB of the immediately-preceding codeword is "0", and FIG. 28B shows a group of codewords, with the MSB-side "0" run length of 1 at minimum and 5 at maximum, that can be used when the LSB of the immediately-preceding codeword is 1. More specifically, in the case of FIG. 28A, of the codewords with CDS=+2, 100 codewords are selected and paired with the 100 codewords with CDS=-2; of the codewords with CDS=+4, 37 codewords are selected and paired with the 37 codewords with CDS=-4; of the codewords with CDS=+6, six codewords are selected and paired with the six codewords with CDS=-6; and the 147 codewords with CDS=0 are used in both groups to form 147 pairs; also, of the codewords with CDS.noteq.0, the codewords with CDS>0 and the codewords with CDS<0 are used in pairs, while the codewords with CDS=0 are used in both groups. The total number of codeword pairs in this case is 147+100+37 +6=290, which is enough to cover the 256 pairs to handle 8-bit data.

On the other hand, in the case of FIG. 28B, of the codewords with CDS=-2, 71 codewords are selected and paired with the 71 codewords with CDS=+2; of the codewords with CDS=-4, 27 is selected and paired with the 27 codewords with CDS=+4; of the codewords with CDS=-6, three codewords are selected and paired with the three codewords with CDS=+6; and the 100 codewords with CDS=0 are used in both groups to form 100 pairs; also, of the codewords with CDS.noteq.0, the codewords with CDS>0 and the codewords with CDS<0 are used in pairs, while the codewords with CDS=0 are used in both groups. The total number of codeword pairs in this case is 100+71+27+3=201, which is 55 pairs short of the 256 pairs necessary to handle 8-bit data. To fill the shortage, the remaining 55 codewords with CDS=-2, -4, -6, and -8 are used in both groups of codewords with CDS.gtoreq.0 and CDS.ltoreq.0, and by suppressing the DSV divergence in the manner described below, DC-free codewords (codewords with finite DSV value) are constructed.

First, the suppression of the DSV divergence is accomplished in two ways: one is by controlling the suppression of the DSV divergence at each codeword end, and the other is by performing control so that the DSV is in the converging direction at the end of the next codeword to be connected. For this purpose, of the codeword pairs that are used when the LSB of the immediate]y-preceding codeword is 1, two codewords with CDS<0 (hereinafter called NG codewords) forming each codeword pair used to fi]]the shortage are each selected to have "0" as the LSB. That is, by selecting a codeword whose LSB is "0" as an NG codeword, the codeword succeeding the NG codeword always has a codeword with CDS.gtoreq.0 and a codeword with CDS>0 as a pair and is therefore selected from among the codewords that are made to correspond to 8-bit data and are used when the LSB of the immediately-preceding codeword is "0". As a result, the DSV divergence at the end of the codeword succeeding the NG codeword can be converged or suppressed.

Second, when a codeword other than an NG codeword is Followed by an NG codeword, and when the DSV at the end of the NG codeword becomes larger than the DSV at the start of the non-NG codeword or the absolute value of the DSV exceeds a predetermined value, a codeword whose CDS is opposite in polarity to the CDS of that codeword is added as a subcode. As the subcode, a codeword is used which has the characteristic that there cannot be a case where the subcode is followed by an NG codeword whose DSV is in the diverging direction, and that, after the use of the subcode, the DSV at the codeword end temporarily moves in the diverging direction, but at the end of the next codeword to be connected, the DSV tending toward the diverging direction is converged to the same value as the DSV at the start of the subcode or to a value closer to 0 than it. For this purpose, the codeword to be connected after the subcode, that is, a codeword selected from the other conversion table containing codewords corresponding to the same 8-bit data as the NG codewords, is chosen to have the CDS of such a value as to bring the DSV, tending toward the diverging direction because of the subcode, back to its original value or to make the DSV smaller in absolute value terms than the DSV at the start of the subcode.

FIGS. 29 to 32 show the numbers of codewords, shown in FIGS. 28A and 28B, broken down by codeword LSB in relation to the CDS and the codeword end state (denoted by P) in a codeword sequence to consider the CDS to be selected for the next codeword to be connected. In each figure, P indicates the state transition within a codeword and the codeword end state after NRZI modulation; assuming that NRZI modulation is started at the low level, when the level at the end of a codeword is high, the state is indicated as P=-1 (which means the level at the end is opposite in polarity to that at the start of the codeword), and when the level at, the end of a codeword is low, the state is indicated as P=+1 (which means the level at the end is the same in polarity as that at the start of the codeword). FIGS. 29 and 30 show the numbers of codewords, with the MSB-side "0" run length of 3 at maximum, that are used when the LSB of the immediately-preceding codeword is "0", and FIGS. 31 and 32 show the numbers of codewords, with the MSB-side "0" run length from 1 to 5, that are used when the LSB of the immediately preceding codeword is 1.

Of the codewords, shown in FIGS. 29 and 30, that are used when the LSB of the immediately-preceding codeword is "0", the 72 codewords with CDS<0 in the codeword group of LSB "0", the 49 codewords with CDS=-2 in the codeword group of LSB "1", 42 codewords out of the codewords with CDS =0, and the 17 codewords with CDS=-4 and P=-1, a total of 180 codewords, are selected, and likewise, the 119 codewords with CDS>0 in the codeword group of LSB 0, 50 codewords out of the codewords with CDS=+2 in the codeword group of LSB "1", and 11 codewords out of the codewords with CDS=+4 and P=-1, a total of 180 codewords, are selected. These codewords are paired between CDS.ltoreq.0 and CDS.gtoreq.0, and the 76 codewords with CDS=0 in the codeword group of LSB "0" are used for both, which gives 180+76=256 pairs which can be made to correspond to 8-bit data. On the other hand, of the codewords, shown in FIGS. 31 and 32, that are used when the LSB of the immediately-preceding codeword is "1", 10 codewords out of the codewords with CDS=-2 in the codeword group of LSB "0", the 11 codewords with CDS=-6, and the 77 codewords with CDS<0 in the codeword group of LSB "1", a total of 98 codewords, are selected, and likewise, the 52 codewords with CDS>0 in the codeword group of LSB "0", and 46 codewords out of the codewords with CDS>0 in the codeword group of LSB "1", a total of 98 codewords, are selected. These codewords are paired between CDS<0 and CDS>0, and the 100 codewords with CDS=0 in both codeword groups of LSB "0" and "1" are used for both, which gives 98+100=198 pairs. To fill the shortage 256-198=58 pairs, the remaining 34 codewords with CDS=-2 in the codeword group of LSB "0" and the 24 codewords with CDS=-4, a total of 58 codewords, are used for both CDS<0 and CDS>0. As a result, the codewords with CDS=-2 and -4 in the codeword group of LSB "0 " and used for CDS>0 correspond to the previously-mentioned NG codewords; since the LSB of the codeword is "0", the next codeword to be connected is always a pair of a codeword with CDS.gtoreq.0 and a codeword with CDS.ltoreq.0, described above, selected from the codeword group used when the LSB of the immediately-preceding codeword is "0".

To construct a codeword conversion table for implementing the above method of suppressing the DSV divergence, a function k for the DSV (DSV') at the end of the immediately-preceding codeword and the state (Pe) at the end of the immediately-preceding codeword in a codeword sequence is obtained, which is expressed as k=DSV'.times.Pe, and codewords are selected on the basis of the polarity of k and the LSB of the immediately preceding codeword. Here, Pe is related to the previously-mentioned P, i.e., Pe=-1 when the level at the codeword end is high, and Pe=+1 when it is low. At this time, for the codeword to be selected, DSV'>0 and Pe=+1 or DSV' <0 and Pe=-1 when k>0, so that it provides CDS.ltoreq.0 that works in the direction of converging the DSV; conversely, when k<0, DSV'>0 and Pe=-1 or DSV'<0 and Pe=+1, resulting in CDS.gtoreq.0 that works in the direction of converging the DSV. When k=0, the polarity of the CDS to be selected is not significant; in this case, whether the LSB of the immediately-preceding codeword is "0" or "1", there are as many codewords as can match 8-bit data, and a codeword with CDS<=0 where no NG codewords are used is selected.

From the above, the codeword pairs between CDS.gtoreq.0 and CDS<0, classified by the LSB value of the immediately preceding codeword, can be divided into the following four groups according to the value of k at the end of the immediately-preceding codeword and the LSB of the immediately-preceding codeword.

(1) T0 group consisting of codewords with CDS.ltoreq.0 that are selected when the LSB of the immediately preceding codeword is "0" and k.gtoreq.0.

(2) T1 group consisting of codewords with CDS.gtoreq.0 that are selected when the LSB of the immediately preceding codeword is "0" and k<0.

(3) T2 group consisting of codewords with CDS.ltoreq.0 that are selected when the LSB of the immediately preceding codeword is "1" and k.gtoreq.0.

(4) T3 group consisting of codewords with CDS.gtoreq.0 that are selected when the LSB of the immediately preceding codeword is "1" and k<0.

Groups of (1) and (2) are used as a pair and groups of (3) and (4) are used as a pair according to the LSB of the immediately-preceding codeword.

Within each of the above groups the codewords are classified by the connection condition for the next codeword. The classification within the respective groups and the correspondence with 8-bit data in the conversion table are shown in FIGS. 33 to 36. In the figures, the data are given in hexadecimal. As shown, the codewords are classified as follows:

(a) Codewords whose LSB is "0" and that can be connected to a codeword of MSB "1". (Connected to a codeword in T0 or T1 group)

(b) Codewords whose LSB is "1" and that cannot be connected to a codeword of MSB "1" but, are connected to a codeword in T2 group. (Not connected to an NG codeword when k.gtoreq.0 at codeword end)

(c) Codewords whose LSB is "1" and that cannot be connected to a codeword of MSB "1" (but are connected to a codeword in T2 or T3 group) and that has the characteristic that even when the next codeword is an NG codeword, the absolute value of the DSV at the end of the NG codeword does not exceed a predetermined value n. In this case, the codewords are constructed with the predetermined value n that is set at 8.

(d) Codewords whose LSB is "1" and that cannot be connected to a codeword of MSB "1" (but are connected to a codeword in T2 or T3 group) and that has the characteristic that if the next codeword is an NG codeword, the absolute value of the DSV at the end of the NG codeword may exceed the predetermined value n.

In T3 group shown in FIGS. 36A, 36B, NG codewords are made to correspond to data "C6"-"FF", and in the other groups, codewords the absolute value of whose CDS is 2 or larger and that fall in the above class (a) or (c) are made to correspond to these data. For the codewords of class (d) in the above classification, subcodes such as described previously are provided. FIGS. 37 to 40 show the LSB, CDS, and P for the subcode codewords provided for the codewords of class (d) in the respective groups.

The codewords shown in FIG. 37 are used as the subcode for T0 group, and this subcode group is designated as T01 group. This subcode group consists of codewords that fall into T1 group in the class where CDS=+2 and P=+1, and corresponds to the same 8-bit data. If any of these codeword is used when k>0 at the end of the immediately preceding codeword (in this case, k=0 at the end of the immediately-preceding codeword and there is no need to use a subcode), then k>0 at the end of the current codeword and the LSB of the codeword is "1"; therefore, it is connected to a codeword corresponding to the data to which an NG codeword in T2 group corresponds. As a result, the absolute value of the DSV at the end of the codeword connected after the subcode is smaller than the predetermined value n=8. Similarly, the codewords shown in FIG. 38 are used as the subcode for T1 group, and this subcode group is designated as T11 group. This subcode group consists of codewords that fall into T0 group in the class where CDS=0 and P=-1 and CDS=-2 and P=-1, and corresponds to the same 8-bit data. If any of these codewords is used when k<0 at the end of the immediately preceding codeword, then k>0 at the end of the current codeword and the LSB of the codeword is "1"; therefore, it is connected to a codeword corresponding to the data to which an NG codeword in T2 group corresponds. As a result, the absolute value of the DSV at the end of the codeword connected after the subcode is smaller than the predetermined value n=8.

The codewords shown in FIG. 39 are used as the subcode for T2 group, and this subcode group is designated as T21 group. This subcode group consists of codewords that fall into T3 group, and of these codewords, the codewords of LSB "1", CDS=+2, and P=+1 and the codewords of LSB "0", CDS=+2, and P=+1, corresponding to data "69"-"6E", correspond to the same 8-bit data to which the equivalent codewords in T3 group correspond. When any codeword in T21 group is used when k at the end of the immediately preceding codeword is of the polarity (k>0 or k=0) that provides the condition for the selection of codewords in the main T2 group, the LSB of the codeword is "0", so that the codeword is connected to a codeword in T0 group or T1 group, or k>0 at the end of the current codeword and the LSB of the codeword is 1, so that the codeword is connected to a codeword corresponding to the data to which an NG codeword in T2 group correspond. As a result, the absolute value of the DSV at the end of the codeword connected after the subcode is smaller than the predetermined value n=8. Similarly, the codewords shown in FIG. 40 are used as the subcode for T3 group, and this subcode group is designated as T31 group. This subcode group consists of codewords that fall into T2 group, and of these codewords, the codewords of LSB "1", CDS =-2, and P=-1, corresponding to data "54"-"5C", correspond to the same 8-bit data to which the equivalent codewords in T2 group correspond. When any codeword in T31 group is used when k<0 at the end of the immediately-preceding codeword, then k>0 at the end of the current codeword and the LSB of the codeword is "1", so that the codeword is connected to a codeword corresponding to the data to which an NG codeword in T2 group correspond, or k<0 and the LSB of the codeword is "0", so that the codeword is connected to a codeword corresponding to the data to which an NG codeword in T1 group correspond. As a result, the absolute value of the DSV at the end of the codeword connected after the subcode is smaller than the predetermined value n=8.

The conversion tables and subcode tables are constructed as described above. The codewords that are the same between T2/T21 group and T3/T31 group but are mapped to different data are distinguished from one another by the polarity of k at the end of the immediately preceding codeword. The polarity provides the condition for selecting T2 (or T21) or T3 (or T31).

The above-explained codeword conversion tables are shown in FIGS. 41 to 46 (for T0 and T1 groups) and FIGS. 47 to 52 (for T2 and T3 groups). FIGS. 53 to 55 show the subcode tables. In the figures, "+" designates P=+1 and "-" designates P=-1, and for the codewords corresponding to the 8-bit data not shown in the subcode tables, there are no subcode data; for such codewords, the same codewords as the codewords corresponding to the same data in the main conversion tables are used.

Referring now to FIG. 56, we will explain how codewords are selected using the conversion tables. First, based on the LSB and k (=DSV'.times.Pe) at the end of the immediately preceding codeword, the dataword to be converted is tentatively converted to a dummy codeword by using the conversion tables T0/T1 and T2/T3 shown in FIGS. 41 to 52, and the LSB and k' are obtained From the DSV and Pe at the end of that dummy codeword. Next, based on the LSB and k' at the end of the dummy codeword, the conversion table used for the conversion of the next dataword is determined; if the next codeword (next dummy codeword) to be connected after the first dummy codeword is selected from the conversion tables T0, T1, or T2, the conversion table used for the conversion into the first dummy codeword is determined as the selection table to be used for converting the current dataword into a codeword. On the other hand, if the next dummy codeword to be connected after the first dummy codeword is selected from the conversion table T3, then the DSV at the end of the next dummy codeword is obtained from the LSB and the DSV and Pe at the end of the first dummy codeword; if the absolute value of the thus obtained DSV is equal to or smaller than the predetermined value n=8, the conversion table used for the conversion into the first dummy codeword is determined as the selection table, which is used for converting the current dataword into a codeword. If the absolute value of the DSV is larger than the predetermined value n=8, an appropriate conversion table for subcode selection is selected from among the conversion tables T01, T11, T21, and T31 shown in FIGS. 53 to 55 and determined as the selection table, to be used for converting the current dataword into a codeword.

By using the above conversion method, data conversion can be achieved wherein the number of successive 0s between an arbitrary "1" and the next "1" is 1 at the minimum and 5 at the maximum, i.e., Tmax/Tmin is 3.0. Furthermore, Tw.times.Tmin is 0.653 which is the same as the value achieved by the prior art 8-14 modulation method and is larger than 0.64 achieved by the prior art 8-10 modulation method, and thus, high-density recording is made possible. Moreover, the diverging range of the DSV (the separation between the minimum and maximum values of the DSV) is finite, that is, .+-.12 at codeword end and .+-.14 within the codeword sequence, which means DC free.

FIG. 57 is a diagram showing an example of a circuit configuration for an apparatus for implementing the data conversion method of Embodiment 3. In the figure, the numeral 11 designates a flip-flop circuit for delaying input 8-bit data (c) by one dataword and for outputting the thus delayed 8-bit data (d) to a dummy code discriminator 12. The dummy code discriminator 12 converts the input 8-bit data (d) into a dummy codeword, based on the DSV and the Pe signal at the end of the immediately-preceding codeword, delayed through a latch circuit 13, and a table selection signal determined on the basis of the DSV and Pe. The dummy code discriminator 12 then outputs the DSV and Pe signal at the end of the dummy codeword and also a signal designating the conversion table to be used for the selection of the next dummy codeword following the first dummy codeword; these signals are inputted to a subcode selection determiner 14. Based on the outputs of the dummy code discriminator 12, the subcode selection determiner 14 converts the input 8-bit data (c) into a codeword as the next dummy codeword, and based on the DSV at the end of the next dummy codeword and the signal designating the conversion table used for the conversion into the next dummy codeword, the subcode selection determiner 14 determines whether to use or not to use the subcode and supplies the result of the decision to a selection table decider 15. Based on the output of the subcode selection determiner 14 and the table selection signal from the latch circuit 13, the selection table decider 15 determines the conversion table to be used for the conversion of the current input data, and supplies a signal designating the conversion table to an encoder 16.

The encoder 16, in which data conversion tables such as shown in FIGS. 41 to 55 are stored, converts the 8-bit data (d), outputted from the flip-flop circuit 11, into a 14-bit codeword by using the conversion table selected in accordance with the signal fed from the selection table decider 15, and supplies the resulting codeword to a parallel-serial converter 17 as well as to a table determiner 21. The encoder 16 also outputs 3-bit data as CDS information associated with the 14-bit codeword to a DSV calculator 19, and a one-bit P signal indicating the state at the end of the codeword ("1" when P=+1, and "0" when P=-1) to a Pe determiner 20.

The 14-bit codeword outputted as a parallel signal from the encoder 16 is loaded into the parallel-serial converter 17 by a symbol clock (a), and converted into a serial signal in synchronism with a channel clock (b), the serial signal then being transferred to an NRZI modulator 18. The NRZI modulator 18 introduces a state transition (from high to low or from low to high) when the input signal is a "1".

The CDS information from the encoder 16 and the signals from the latch circuit 13, representing the DSV and Pe at the end of the immediately-preceding codeword, are inputted to the DSV calculator 19 which then calculates the DSV at the end of the current codeword and supplies the result of the calculation to the latch circuit 13 and also to the table determiner 21. The Pe determiner 20 determines the Pe signal which shows the state at the end of the converted current codewords on the basis of the P signal supplied from the encoder 16 and the Pe signal at the end of the last converted codeword supplied from the latch circuit 13, and outputs the result to the latch circuit 13 and the table determiner 21. The table determiner 21 is supplied at its inputs with the DSV from the DSV calculator 19, the Pe signal from the Pe determiner 20, and the LSB of the 14-bit codeword outputted from the encoder 16, and determines the conversion table to be used for the selection of the next codeword following the current codeword, and supplies a 2-bit table selection signal designating the conversion table to the latch circuit 13. The respective outputs from the DSV calculator 19, Pe determiner 20, and table determiner 21 are thus supplied to the latch circuit 13, where they are delayed by one symbol by using the symbol clock (a), to provide information for the conversion of the next dataword that follows the current codeword.

FIG. 58 is a diagram showing an example of a circuit configuration for the dummy code discriminator 12. The dummy code discriminator 12, in which the LSB, CDS information and P signal for each codeword in the conversion tables of FIGS. 41 to 52 are stored in corresponding relationship to 8-bit data, has: a dummy code converter 121 that outputs the codeword LSB, CDS information, and P signal when the 8-bit data (d) fed from the flip-flop circuit 11 is converted into a dummy codeword in accordance with the table selection signal fed from the latch circuit 13; a DSV calculator 122 that calculates the DSV at the end of the dummy codeword on the basis of the CDS information supplied From the dummy code converter 121 and the DSV and Pe at the end of the immediately preceding codeword supplied from the latch circuit 13; a Pe determiner 123 that determines the state at the end of the dummy codeword on the basis of the P signal supplied from the dummy code converter 121 and the Pe signal at the end of the immediately preceding codeword supplied From the latch circuit 13, and that outputs a Pe signal indicating the result of the decision; a k calculator 124 that obtains a value k (k=DSV.times.Pe), which provides the condition for the selection of the conversion table for the conversion of the next codeword following the first dummy codeword, on the basis of the DSV and Pe signal at the end of the dummy codeword supplied from the DSV calculator 122 and the Pe determiner 123, and that outputs a signal indicating the polarity of the obtained value; and a next dummy code table determiner 125 that determines the conversion table to be used for the conversion of the next codeword (next dummy codeword) following the first dummy codeword, on the basis of the LSB of the first dummy codeword supplied from the dummy code converter 121 and the signal indicating the polarity of k supplied from the k calculator 124, and that outputs a signal indicating whether the next dummy codeword is to be selected from the conversion table T3 (FIGS. 47 to 52) containing NG codewords or from another conversion table T0, T1, or T2 (FIGS. 41 to 46, 47 to 52). The respective outputs from the DSV calculator 122, Pe determiner 123 and next dummy code table determiner 125 are supplied to the subcode selection determiner 14.

FIG. 59 is a diagram showing an example of a circuit configuration for the subcode selection determiner 14. The subcode selection determiner 14, in which CDS information for the codewords in the conversion table T3 in FIGS. 47 to 52 is stored in corresponding relationship to 8-bit data, has: a next dummy code converter 141 that outputs CDS information for a codeword (next dummy codeword) when the input 8-bit data (c) is converted using the conversion table T3 in accordance with the select signal supplied from the next dummy code table determiner 125 in the dummy code discriminator 12 indicating whether or not the next dummy codeword is to be selected from the conversion table T3; a DSV calculator 142 which, only when the next dummy codeword is selected from the conversion table T3, calculates the DSV at the end of the next dummy codeword on the basis of the CDS information supplied from the next dummy code converter 141 and the DSV and Pe signal at the end of the dummy codeword supplied from the dummy code discriminator 12; and a subcode discriminator 143 to which the DSV at the end of the next dummy codeword and the select signal indicating the conversion table for the conversion of the next dummy codeword are inputted from the DSV calculator 142 and the dummy code discriminator 12 respectively, and which obtains the absolute value of the DSV at the end of the next dummy codeword when the next dummy codeword is a codeword generated using the table T3, and outputs a signal to select the current codeword from the subcode if the absolute value exceeds the predetermined value n=8, or a signal indicating not to use the subcode if the absolute value is equal to or smaller than the predetermined value or if the next dummy codeword is to be selected from other conversion tables than T3. The signal indicating whether to use or not to use the subcode is transferred to the selection table decider 15.

FIGS. 60 to 63 are timing diagrams for explaining in further detail the operation of the circuits described with reference to FIGS. 57, 58, and 59. In the figures, the signs (a) to (t) correspond to the points indicated by the same signs in the input/output sections of the circuits shown in FIGS. 57 to 59.

The operation of each circuit will be described in detail below. The 8-bit data (c) from an error-correction encoding circuit is inputted to the flip-flop circuit 11 and the subcode selection determiner 14. The flip-flop circuit 11 delays the input 8-bit data (c) by one dataword by using the symbol clock (a); the resulting delayed data (d) is supplied as a parallel signal to the dummy code discriminator 12 as well as to the encoder 16. In the dummy code discriminator 12, the 8-bit data (d) from the flip-flop circuit 11 and the table selection signal (e) from the latch circuit 13 are inputted to the dummy code converter 121, which then converts the 8-bit data (d) into a dummy codeword on the basis of the table selection signal (e), and outputs the CDS information, P signal, and codeword LSB of the resulting dummy codeword. The latch circuit 13 also supplies the DSV (g) and Pe signal (f) at the end of the immediately-preceding codeword to the dummy code discriminator 12, where the DSV value (g) at the end of the immediately-preceding codeword is inputted to the DSV calculator 122 and the Pe signal (f) at the end of the immediately-preceding codeword is inputted to the Pe determiner 123. Based on the DSV value (g) thus inputted and the CDS information supplied from the dummy code converter 121, the DSV calculator 122 calculates the DSV at the end of the dummy codeword and outputs the result (i). Based on the P signal from the dummy code converter 121 and the Pe signal at the end of the immediately-preceding codeword, the Pe determiner 123 determines the Pe signal at the end of the dummy codeword and outputs the result (h). Suppose here that, at time 1 in FIG. 60, the table selection signal (e) from the latch circuit 13 indicates the conversion table T0 while the Pe signal at the end of the immediately-preceding codeword is +1 and DSV(g) is 0. In this case, when the data (d) "8C" outputted from the flip-flop circuit 11 is converted by the dummy code converter 121 into a dummy codeword, the CDS, P signal, and codeword LSB for the dummy codeword are outputted as "0", "+1", and "1" respectively The output of the DSV calculator 122, i.e. the DSV (i) at the end of the dummy codeword and the output (h) of the Pe determiner 123 are "0" and "+1", respectively.

The DSV (i) at the end of the dummy codeword, outputted from the DSV calculator 122, and the Pe signal at the end of the dummy code, outputted from the Pe determiner 123, are supplied to the k calculator 124 as well as to the subcode selection determiner 14. The k calculator 124 calculates k =DSV.times.Pe from the DSV (i) and Pe signal (h), obtains its polarity, and outputs a signal (j), representing "1" if k.gtoreq.0 and "0" if k<0, which is fed to the next dummy code table determiner 125. Based on the LSB of the dummy codeword from the dummy code converter 121 and the signal (j) indicating the polarity of k at the end of the dummy codeword, the next dummy code table determiner 125 determines the conversion table to be used for the conversion of the next dummy codeword that follows the first codeword, and outputs a signal (1) indicating, for example, a high level when the conversion table T3 is to be used, and a low level when another conversion table is to be used. More specifically, when the LSB of the first dummy codeword is 1 and k<0, then the next dummy codeword is selected from the conversion table T3; otherwise (when the dummy codeword LSB is "1" and k.gtoreq.0 or when the LSB is "0"), a conversion table other than the conversion table T3 is used. At time 1 in FIG. 60, k=0 and the dummy codeword LSB is "1", and the conversion table T2 is selected for the next dummy codeword, so that the output (1) of the next dummy code table determiner 125 is a low level signal. The output (1) of the next dummy code table determiner 125 is supplied to the subcode selection determiner 14.

Next, the operation of the subcode selection determiner 14 will be described in detail. In the subcode selection determiner 14, the input 8-bit data (c) is inputted to the next dummy code converter 141 to which the signal (1) indicating whether or not the next dummy codeword is to be selected from the conversion table T3 is inputted from the next code table determiner 125. When the conversion table T3 is to be used, the next 8-bit data (c) "81" is converted as the next dummy codeword, and the associated CDS information is fed to the DSV calculator 142. Based on the CDS information associated with the next dummy codeword supplied from the next dummy code converter 141 and the DSV (i) and Pe signal (h) at the end of the first dummy codeword supplied from the dummy code discriminator 12, the DSV calculator 142 calculates the DSV at the end of the next dummy codeword, and outputs the result (o) which is supplied to the subcode discriminator 143. The DSV calculator 142 is required to perform the calculation only when the next dummy codeword is selected from the conversion table T3; the output (1) of the next dummy code table determiner 125 is applied to control the operation of the DSV calculator 142.

Based on the signal (1) supplied from the next dummy code table determiner 125 and the DSV (o) at the end of the next dummy codeword supplied from the DSV calculator 142, the subcode discriminator 143 determines whether to use or not to use the subcode for the conversion of the current input dataword, and outputs a signal (r) which is, for example, a high level signal when the subcode table is to be used, and a low level signal when the main code is to be used. The decision as to whether to use or not to use the subcode is made, first on the basis of the signal (1) indicating whether or not the next dummy codeword is to be selected from the conversion table T3; when the signal (1) is at the low level, the subcode is not used, and therefore, the low level signal is outputted. On the other hand, when the signal (1) is at the high level, indicating that the next dummy codeword is to be selected from the conversion table T3, then the absolute value of the DSV (o) at the end of the next dummy codeword supplied From the DSV calculator 142 is obtained; if the absolute value is larger than the predetermined value n=8, the subcode is used for the conversion of the current input dataword, so that the output (r) goes high, and if the absolute value is not larger than the predetermined value, the subcode is not used, so that a low level signal is outputted. At time 1 in FIG. 60, the output signal (1) of the next dummy code table determiner 125 is low and no output is generated either from the next code converter 141 or from the DSV calculator 142, which indicates that the subcode is not used, so that the subcode discriminator 143 outputs a low level signal. The output (r) of the subcode discriminator 143 is supplied to the selection table decider 15.

Along with the output (r) of the subcode selection determiner 14 (the subcode discriminator 143), the same table selection signal (e) as used to determine the dummy codeword is inputted to the selection table decider 15, which then decides which conversion table is to be used for the conversion of the current dataword, and outputs a 3-bit signal (s) indicating the decided selection table. More specifically, when the output (r) of the subcode discriminator 143 is at the low level, a signal indicating the conversion table designated by the table selection signal (e) is outputted; conversely, when the output (r) of the subcode discriminator 143 is at the high level, a signal indicating a subcode table is outputted. The output signal is fed to the encoder 16. Based on the decided selection table indicating signal (s) supplied from the selection table decider 15, the encoder 16 selects the conversion table to be used from among the conversion tables of FIGS. 41 to 55, and converts the 8-bit data (d) (dataword), inputted via the flip-flop circuit 11, into a 14-bit codeword for output. This 14-bit codeword is fed into the parallel-serial converter 17.

At time 1 in FIG. 62, since the output (r) of the subcode discriminator 143 is at the low level, the output (s) of the selection table decider 15 indicates T0, the same conversion table as designated by the table selection signal (e); therefore, in the encoder 16, the 8-bit data (d) "8C" is converted into a 14-bit codeword "10010000010001" (n) in accordance with the conversion table T0 shown in FIGS. 41 to 46, which is fed into the parallel-serial converter 17. This 14-bit codeword (n) is loaded into the parallel-serial converter 17 during a low level period of the symbol clock (a), and is outputted as a serial codeword sequence, with MSB as the leading bit, from the parallel-serial converter 17 in synchronism with the channel clock (b). The codeword sequence outputted from the parallel-serial converter 17 is fed into the NRZI modulator 18 where it is transformed into a signal (t), shown in FIG. 62, with its polarity being reversed at every appearance of a "1". With the high level designated as +1 and the low level as -1, when the CDS is calculated, the result is +1, and the DSV of the codeword sequence remains 0.

With the above operation, the 8-bit dataword has been converted into a 14-bit codeword. Next, the DSV at the end of the thus obtained codeword and the Pe signal indicating the state at the end of it are obtained, based on which the conversion table used for the conversion of the next dataword is determined. This operation will be described below.

Along with the 14-bit codeword, the encoder 16 outputs the CDS information associated with this codeword and the P signal indicating the state at the end of this codeword. The CDS information is fed to the DSV calculator 19 and the P signal to the Pe determiner 20. Further, the LSB of the codeword outputted from the encoder 16 is fed to the table determiner 21. Using the DSV (g) and Pe signal (f) at the end of the immediately preceding codeword supplied from the latch circuit 13 and the CDS information associated with the current codeword, the DSV calculator 19 calculates the DSV at the end of the current codeword and supplies the result (u) to the table determiner 21 as well as to the latch circuit 13. Based on the Pe signal (f) at the end of the immediately-preceding codeword supplied from the latch circuit 13 and the P signal of the current codeword supplied From the encoder 16, the Pe determiner 20 determines the Pe signal indicating the state at the end of the current codeword, and supplies the result (v) to the table determiner 21 as well as to the latch circuit 13. Based on the codeword LSB and also on the DSV (u) and Pe signal (v) at the end of the current, codeword supplied respectively from the DSV calculator 19 and the Pe determiner 20, the table determiner 21 determines the conversion table to be used for the next conversion, and supplies the result (w) to the latch circuit 13. More specifically, from the DSV and Pe signal at the end of the codeword, the value k=DSV.times.Pe is obtained, and the conversion table to be used is determined on the basis of the polarity of k and the LSB of the codeword: when the codeword LSB is "0" and k.gtoreq.0, the conversion table T0 is selected; when the LSB is "0" and k<0, the conversion table T1 is selected; when the LSB is 1 and k.gtoreq.0, the conversion table T2 is selected; and when the LSB is "1" and k <0, the conversion table T3 is selected for the conversion of the next, dataword. The DSV (u) and Pe signal (v) for the codeword and the output (w) from the table determiner 21, which are inputted to the latch circuit 13, are latched for one symbol period by using the symbol clock (a) and used as the information for the next dataword conversion.

Referring to FIG. 60, the DSV (u) "0" and Pe (v) "+1" at the end of the codeword (n) converted from the 8-bit data "8C" at time 1 and the selection table signal (w) "T2" for the next codeword are latched in the latch circuit 13, and are used at time 2 as the DSV (g) and Pe signal (f) at the end of the immediately preceding codeword and the table selection signal (e), respectively. Then, in the same manner as described above, data conversion is performed on the input 8-bit data "81" at time 2.

As described above, every input 8-bit data (dataword) is converted by the encoder 16 into a 14-bit codeword on the basis of the DSV and Pe signal at the end of the immediately-preceding codeword as well as the kind of the next codeword and the DSV at the end of it; as a result, the change range of the DSV is held within a finite value, i.e. .+-.12 at the end of a codeword and .+-.14 within a codeword sequence, and a DC-free codeword can thus be obtained.

We will now describe a method of reproduction signal decoding wherein an n-bit codeword is reverse-converted into the original m-bit dataword for reproduction in a recording and reproduction apparatus employing the above-described data conversion method of Embodiment 3.

FIG. 64 is a block diagram showing an example of an apparatus for decoding reproduced 14-bit codewords into the original 8-bit datawords in a recording and reproduction apparatus employing the data conversion method of Embodiment 3. In FIG. 64, the numeral 30 designates an NRZI demodulator for NRZI-demodulating the reproduction signal transmitted in synchronism with a reproduction channel clock. The NRZI demodulator 30 supplies the NRZI-demodulated signal to a serial-parallel converter 31. The serial-parallel converter 31 converts the NRZI-demodulated serial signal from the NRZI demodulator 30 into a 14-bit parallel signal by using a reproduction word clock word-synchronized by a synchronizing signal appended to the beginning of a block, and supplies the converted signal to a first decoder 33, a second decoder 34, and a third decoder 35. Further, the serial-parallel converter 31 supplies the LSB of the 14-bit codeword to a flip-flop circuit 36. The transmitted reproduction signal is also inputted to a k discriminator 32. The k discriminator 32 counts the DSV during the reproduction of the reproduction signal being transmitted in synchronism with the reproduction channel clock, by using a reproduction count start signal that is synchronized with the output of the serial-parallel converter 31 by the reproduction channel signal, the reproduction word clock, the synchronizing clock appended to the beginning of a block, etc. At the same time, the k discriminator 32 discriminates the terminal state Pe and the DSV of the codeword to determine k=DSV.times.Pe for reproduction, latches the signal indicating the polarity of k by the reproduction word clock, and supplies the thus latched signal to a selector 37 to provide the decoding condition for the next codeword to be decoded. As the signal indicating the polarity of k, a "1" is outputted for k.gtoreq.0, and a "0" is outputted for k<0, for example.

The first decoder 33 is supplied with 14-bit codewords outputted from the serial-parallel converter 31; of these 14-bit codewords, any codeword shown in the conversion table T0/T1 in FIGS. 41 to 46 or the conversion table T01/T11 in FIGS. 53 is decoded by the first decoder 33 into the original 8-bit dataword, and the result of the decoding is applied to one input terminal of a selector 38. The second decoder 34 is supplied, as is the first decoder 33, with 14-bit codewords outputted from the serial-parallel converter 31; of these 14-bit codewords, any codeword shown in the conversion table T2 in FIGS. 47 to 52 or the conversion table T21 in FIG. 54 is decoded by the second decoder 34 into the original 8-bit dataword, and the result of the decoding is applied to one input terminal of the selector 37. The third decoder 35 is supplied, as are the first and second decoders 33 and 34, with 14-bit codewords outputted from the serial-parallel converter 31; of these 14-bit codewords, any codeword shown in the conversion table T3 in FIGS. 47 to 52 or the conversion table T31 in FIG. 55 is decoded by the third decoder 35 into the original 8-bit dataword, and the result of the decoding is applied to the other input terminal of the selector 37.

The flip-flop circuit 36 delays the one-bit LSB, fed from the serial-parallel converter 31, by one word by using the reproduction word clock, and applies its output to the selector 38. Based on the signal from the k discriminator 32, the selector 37 selects the 8-bit dataword outputted from the second decoder 34 or the 8-bit dataword outputted from the third decoder 35, and applies the selected dataword to the other input of the selector 38. Based on the LSB of the codeword delayed by one word through the flip-flop circuit 36, the selector 38 selects the 8-bit dataword outputted from the first decoder 33 or the 8-bit dataword outputted from the selector 37, and outputs the selected 8-bit dataword.

The operation of the above apparatus will now be described. The reproduction signal is NRZI-demodulated by the NRZI demodulator 30, and fed to the serial-parallel converter 31, where the serial signal is converted to a parallel signal which is outputted as a 14-bit codeword. The reproduction signal is also supplied to the k discriminator 32 which counts the DSV of the reproduction signal by the reproduction count start signal, reproduction channel clock, and reproduction word clock, discriminates the DSV and Pe at the end of the codeword to determine k=DSV.times.Pe, latches the signal indicating the polarity of k by the word clock, and supplies the thus latched signal to the selector 37 as k information representing the condition at the end of the last decoded codeword immediately preceding the current codeword to be decoded. The 14-bit codeword outputted from the serial-parallel converter 31 is fed into the first decoder 33, second decoder 34 and third decoder 35, while the LSB of the 14-bit codeword is sent to the flip-flop circuit 36 where it is delayed by one word before it is transferred to the selector 38.

The first decoder 33 decodes the 14-bit codeword into the original 8-bit data (dataword) if it is a codeword shown in the conversion table T0/T1 in FIGS. 41 to 46 or the conversion table T01/T11 in FIG. 53, and supplies the decoded data to the selector 38. For the codewords in the conversion tables T0/T1 and T01/T11, the corresponding 8-bit data are not discriminated by the polarity of k at the end of the last decoded codeword, but these codewords are used when the LSB of the immediately-preceding codeword is "0". On the other hand, the second decoder 34 decodes the 14-bit codeword into the original 8-bit data if it is a codeword shown in the conversion table T2 in FIGS. 47 to 52 or the conversion table T21 in FIG. 54, and supplies the decoded data to the selector 37, and the third decoder 35 decodes the 14-bit codeword into the original 8-bit data if it is a codeword shown in the conversion table T3 in FIGS. 47 to 52 or the conversion table T31 in FIG. 55, and supplies the decoded data to the selector 37. For the codewords in the conversion tables T2/T21 and T3/T31, the corresponding 8-bit data need to be discriminated by the polarity of k at the end of the last decoded codeword, and these codewords are used when the LSB of the immediately preceding codeword is "1".

Next, using the signal indicating the polarity of k at the end of the last decoded signal supplied from the k discriminator 32 as the selection signal, the selector 37 selects the 8-bit data decoded by the second decoder 34 when k>0, or the 8-bit data decoded by the third decoder 35 when k<0, and supplies the selected data to the selector 38. Using the LSB of the last decoded codeword supplied from the flip-flop circuit 36 as the selection signal, the selector 38 selects the 8-bit data from the first decoder 33 when the LSB of the immediately-preceding codeword is "0", or the 8-bit data selected by the selector 37 when the LSB is "1", and outputs the selected data as the decoded 8-bit data.

Thus, according to the above decoding method of reverse-converting and decoding reproduced 14-bit codewords into 8-bit datawords in a recording and reproduction apparatus employing the data conversion method of Embodiment 3, the polarity of k is obtained from the DSV and Pe at the end of the immediately preceding codeword in the reproduction signal, and decoding is performed by switching the outputs of the conversion tables according to the polarity of k and the LSB of the immediately preceding codeword.

In the above-described decoding method of Embodiment 4, three kinds of decoders (first, second and third decoders) using different conversion tables are provided, and the decoded data are selected, using selectors, according to the discriminating conditions of the polarity of k and the LSB at the end of the immediately preceding codeword. It will be recognized, however, that the method of selecting the conversion table according to the discriminating conditions is not limited to the above-illustrated one. For example, as shown in FIG. 65, a discrimination signal may be generated from the signal supplied from the k discriminator and the LSB of the immediately-preceding codeword, and this signal may be inputted to the decoder along with the codeword to be decoded to obtain m-bit data (dataword); with this configuration also, the same effect as achieved in Embodiment 4 can be obtained.

In FIG. 65, the parts indicated at 30, 31, 32 and 36 are identical to the corresponding parts in the apparatus of Embodiment 4. The numeral 39 designates a decoding table discriminator which accepts at its inputs the signal indicating the polarity of k, outputted from the k discriminator 32, and the LSB of the immediately-preceding codeword supplied from the flip-flop circuit 36, and which discriminates the signal designating the decoding table to be used for the decoding of the current codeword. The decoding table discriminator 39 outputs a 2-bit control signal to the decoder 40; For example, a signal "00" when the same decoding table as in the first decoder 33 in Embodiment 4 is to be used, a signal "01" when the same decoding table as in the second decoder 34 is to be used, and a signal "11" when the same decoding table as in the third decoder 35 is to be used. The decoder 40 accepts at its inputs the 2-bit control signal designating the decoding table, outputted from the decoding table discriminator 39, as well as the 14-bit codeword to be decoded, and converts the 14-bit codewords into an 8-bit dataword for output.

The operation of the above apparatus will now be described. The 14-bit codeword outputted from the serial-parallel converter 31 is inputted to the decoder 40, while the LSB of the codeword is sent to the flip-flop circuit 36 where it is delayed by one word before being passed on to the decoding table discriminator 39. Also inputted to the decoding table discriminator 39 is the signal indicating the polarity of k at the end of the immediately-preceding codeword, outputted from the k discriminator 32. Based on the signal supplied from the k discriminator 32 and the LSB of the immediately preceding codeword supplied from the flip-flop circuit 36, the decoding table discriminator 39 discriminates the decoding table to be used for the decoding of the current codeword, and supplies the output to the decoder 40. At this time, a signal "00" indicating the same decoding table as used in the first decoder 33 in Embodiment 4 is supplied to the decoder 40 when the LSB of the immediately-preceding codeword is "0"; a signal "01" indicating the same decoding table as used in the second decoder 34 in Embodiment 4 is supplied when the LSB of the immediately-preceding codeword is "1" and k.gtoreq.0; and a signal "11" indicating the same decoding table as used in the third decoder 35 in Embodiment 4 is supplied when the LSB of the immediately-preceding codeword is "1" and k<0.

The 2-bit control signal outputted from the decoding table discriminator 39 and the 14-bit codeword are inputted to the decoder 40 for decoding: when the control signal bits are "00", the 14-bit codeword is decoded into an 8-bit dataword by using the same conversion table as used in the first decoder 33 in Embodiment 4 shown in FIG. 64; when the control signal bits are "01", the 14-bit codeword is decoded into an 8-bit dataword by using the same conversion table as used in the second decoder 34; and when the control signal bits are "11", the 14-bit codeword is decoded into an 8-bit dataword by using the same conversion table as used in the third decoder 35.

The decoded 8-bit data (dataword) is thus outputted from the decoder 40, achieving the same effect as obtained with the decoding method of Embodiment 4.

FIG. 66 is a diagram showing a circuit configuration for implementing the data conversion method of Embodiment 3. In FIG. 66, the parts indicated at 11, 12, 14, 15, and 17 to 20 are identical to the corresponding parts in the apparatus of Embodiment 3 shown in FIG. 57. The numeral 22 indicates a latch circuit for delaying the input signal by one symbol by using the symbol clock (a). The numeral 23 is an encoder which contains therein: data conversion tables, such as shown in FIGS. 41 to 55; a codeword not used in any of these conversion tables, as a codeword indicating a synchronizing signal; and codewords to be placed after the synchronizing signal and used for resetting the DSV at the end of the synchronizing signal to 0. Based on the signal supplied from the selection table decider 15, a sync. area signal (sy) indicating a synchronizing signal area, and a signal (dr) indicating the output of the DSV resetting codeword, the encoder 23 selects the conversion table, synchronizing signal or DSV reset data, and encodes the 8-bit data (d) outputted from the flip-flop circuit 11 into a 14-bit codeword for output. The encoder 23 also outputs 3-bit CDS information associated with the output 14-bit codeword and a 1-bit P signal indicating the state at the end of the output codeword ("1" when P=+1, "0" when P=-1); the CDS information is supplied to the DSV calculator 19 and the P signal to the Pe determiner 20.

The DSV outputted from the DSV calculator 19, the Pe signal outputted from the Pe determiner 20, and the LSB of the 14-bit codeword outputted from the encoder 23 are inputted to a table determiner 24 which then obtains k=DSV.times.Pe, determines the conversion table to be selected for the conversion of the next dataword succeeding the current dataword, and supplies a 2-bit table selection signal indicating the selected table and the value of k to the latch circuit 22. The numeral 25 is a DSV reset data discriminator to which the value of k at the end of the immediately-preceding codeword is inputted from the latch circuit 22, and which, based on the sync. area signal (sy) and symbol clock (a), discriminates such data as to reset the DSV at the end of the synchronizing signal to 0 in the two-symbol area succeeding the sync. signal area, creates a signal indicating such data, and supplies it to the encoder 23.

FIG. 67 is a diagram showing an example of a circuit configuration for the table determiner 24. The table determiner 24 includes: a k calculator 241 that obtains k=DSV.times.Pe from the DSV (u) at the end of the codeword supplied from the DSV calculator 19 and the Pe signal (v) supplied from the Pe determiner 20, and that outputs the resulting value; and a table discriminator 242 that accepts at its inputs the value of k from the k calculator 241 and the LSB of the codeword from the encoder, and that discriminates the conversion table to be selected for the next dataword to be converted. The respective outputs of the k calculator 241 and table discriminator 242 are supplied to the latch circuit 22 where they are delayed by one symbol.

FIG. 68 is a diagram showing an example of a circuit configuration for the DSV reset data discriminator 25. The DSV reset data discriminator 25 includes: an area signal generator 251 that generates at its output an area signal indicating the two-symbol DSV reset data area succeeding the synchronizing signal on the basis of the symbol clock (a) and sync. signal area signal (sy); and a DSV reset data generating signal producer 252 that, produces a signal indicating the output of a codeword for resetting the DSV at the end of the synchronizing-signal indicating codeword to "0" on the basis of the value of k at the end of the immediately-preceding codeword supplied from the latch circuit 22, the area signal from the area signal generator 251, and the symbol clock (a), and supplies the signal to the encoder 23.

Generally, a synchronizing signal appended at the beginning of a block is used to separate one codeword group from another, and is required to have high reliability. Therefore, a codeword that cannot occur in a codeword sequence converted from 8-bit data is used as the codeword to indicate the synchronizing signal, and at the time of reproduction, this codeword is detected as the reproduction synchronizing signal to be used as the reference to which the reproduction operation is performed. In Embodiment 6, a codeword "01000101000101" with CDS=+4 and P=-1, which is not used in any of the conversion tables in FIGS. 41 to 55 as a codeword corresponding to 8-bit data, is used as the codeword to indicate the synchronizing signal. This codeword satisfies the codeword "0" run length condition whether the LSB of the immediately-preceding codeword is "0" or 1; when two words are used in sequence, the DSV and Pe values at the end of the codeword immediately preceding the synchronizing signal are retained also at the end of the second word in the synchronizing signal. Furthermore, the DSV at the end of the codeword immediately preceding the synchronizing signal is smaller in absolute value terms than the predetermined value n=8 for DSV control in data conversion described in Embodiment 3, since the succeeding codeword is the synchronizing signal, not an NG codeword.

FIGS. 69 to 72 are timing diagrams for explaining in further detail the operation of the circuits described with reference to FIGS. 66, 67, and 68. In the figures, the signs (a) to (g), (k'), (sy), etc. correspond to the points indicated by the same signs in the input/output sections of the circuits shown in FIGS. 66 to 68.

The operation of each circuit will be described in detail below. The 8-bit data (c) from an error-correction encoding circuit is inputted to the flip-flop circuit 11 as well as to the subcode selection determiner 14. The flip-flop circuit 11 delays the input 8-bit data (c) by one dataword by using the symbol clock (a), and supplies the delayed data (d) as a parallel signal to the dummy code discriminator 12 as well as to the encoder 23. The dummy code discriminator 12 accepts at its inputs the 8-bit data (d) from the flip-flop circuit 11 and the table selection signal (e) from the latch circuit 13, and converts the 8-bit data (d) into a dummy codeword in accordance with the table selection signal (e). The dummy code discriminator 12 also receives the DSV (g) and Pe signal (f) at the end of the immediately-preceding codeword from the latch circuit 22, and outputs the DSV (i) and Pe signal (h) at the end of the dummy codeword. Furthermore, in the dummy code discriminator 12, the conversion table for the conversion of the next dummy codeword is determined on the basis of the DSV (i) and Pe signal (h) at the end of the dummy codeword as well as the LSB of the dummy codeword, and a signal (l) indicating whether the conversion table T3 is to be used for the next dummy codeword is outputted. The DSV (i) and Pe signal (h) at the end of the dummy codeword and the signal (l) indicating the table selected for the next dummy codeword, which are outputted from the dummy code discriminator 12, are supplied to the subcode selection determiner 14.

The subcode selection determiner 14 determines whether to use or not to use the subcode for the conversion of the current dataword on the basis of the 8-bit data input (c) and the outputs of the dummy code discriminator 12, i.e. the DSV (i) and Pe signal (h) at the end of the dummy codeword and the signal (l) indicating whether the conversion table T3 is to be used for the next dummy codeword. The subcode selection determiner 14 then outputs a signal (r) which is, for example, high when the subcode is to be used, and low when the main code is to be used. The output (r) of the subcode selection determiner 14 is supplied to the selection table decider 15. Along with the output (r) of the subcode selection determiner 14, the same table selection signal (e) as used to determine the dummy codeword is inputted to the selection table decider 15, which then decides which conversion table is to be used for the conversion of the current dataword, and supplies a 3-bit signal (s) indicating the decided selection table to the encoder 23. Based on the signal (s) from the selection table decider 15 indicating the decided selection table, the encoder 23 selects the conversion table to be used from among the conversion tables shown in FIGS. 41 to 55, and converts the 8-bit data (d) fed from the flip-flop circuit 11 into a 14-bit codeword which is outputted. The 14-bit codeword is inputted to the parallel-serial converter 17. This 14-bit codeword (n) is loaded into the parallel-serial converter 17 during a low level period of the symbol clock (a), and is outputted as a serial codeword sequence, with MSB as the leading bit, from the parallel-serial converter 17 in synchronism with the channel clock (b). The codeword sequence outputted from the parallel-serial converter 17 is fed into the NRZI modulator 18 where it is transformed into a signal with its polarity being reversed at every appearance of a "1". The operation here is the same as the conversion operation described in Embodiment 3.

With the above sequence of operations, the 8-bit data (dataword) has been converted into a 14-bit codeword. Next, the sync. area signal (sy) and the output of the DSV reset data discriminator 25 are inputted to the encoder 23, and the DSV at the end of the current codeword and the Pe signal indicating the state at the end of it are obtained, to determine the conversion table to be used for the conversion of the next dataword. This operation will be described below.

Outside the sync. signal area and DSV reset data area, the encoder 23 performs the above-described encoding operation to convert the 8-bit data (d) fed from the flip-flop circuit 11 into a 14-bit codeword, and outputs the 14-bit codeword along with the associated CDS information and the P signal indicating the state at the end of the codeword. In FIGS. 69 to 72, suppose, for example that the synchronizing signal area is indicated by a high level period of the sync. area signal (sy); then, during the high level period of the sync. area signal, the encoder 23 outputs the synchronizing signal codeword "01000101000101" along with its associated CDS information and P signal, regardless of the 8-bit data (d) and the output of the DSV reset data discriminator 25 being applied during that period. Also, when DSV reset data is inputted in the DSV reset data area, the encoder 23 outputs a 14-bit codeword for resetting the DSV along with its associated CDS information and P signal, regardless of the 8-bit data (d) and the sync. area signal (sy). Next, the CDS information is fed to the DSV calculator 19, and the P signal to the Pe determiner 20. Also, the LSB of the codeword outputted from the encoder 23 is inputted to the table determiner 24. Using the DSV (g) and Pe signal (f) at the end of the immediately-preceding codeword supplied from the latch circuit 22 and the CDS information associated with the current codeword, the DSV calculator 19 calculates the DSV at the end of the codeword, and supplies the result (u) to the table determiner 24 and the latch circuit 22. Based on the Pe signal (f) at the end of the immediately preceding codeword supplied from the latch circuit 22 and the P signal of the current codeword supplied from the encoder 23, the Pe determiner 20 determines the Pe signal indicating the state at the end of the codeword, and supplies the result (v) to the table determiner 24 and the latch circuit 22.

In the table determiner 24, the DSV (u) and Pe signal (v) at the end of the current codeword supplied from the DSV calculator 19 and Pe determiner 20, respectively, are inputted to the k calculator 241, which then calculates the k=DSV.times.Pe at the end of the codeword and supplies the calculated value (k) to the table discriminator 242 and the latch circuit 22. Based on the value of k (k) from the k calculator 241 and the LSB of the codeword, the table discriminator 242 discriminates the conversion table to be used for the next data conversion, and supplies the result (w) to the latch circuit 22. More specifically, the conversion table to be used is determined on the basis of the polarity of k at the end of the codeword and the LSB of the codeword: when the codeword LSB is "0" and k.gtoreq.0, the conversion table T0 is selected; when the LSB is "0" and k<0, the conversion table T1 is selected; when the LSB is "1" and k.gtoreq.0, the conversion table T2 is selected; and when the LSB is "1" and k<0, the conversion table T3 is selected for the next data conversion. The DSV (u) and Pe signal (v) of the codeword, the table selection signal (w), and the value of k (k) at the end of the codeword, which are input to the latch circuit 22, are delayed by one symbol period by using the symbol clock (a) and used as the information for the next data conversion. Of this information, the value of k (k') at the end of the codeword outputted from the latch circuit 22 is fed to the DSV reset data discriminator 25.

Next, the operation in the DSV reset data discriminator 25 will be described. The DSV reset data discriminator 25 is constructed as shown in FIG. 68, in which the area signal generator 251 generates a signal (ra) indicating the DSV reset data area from the sync area signal (sy) and symbol clock (a), and supplies the generated signal to the DSV reset data generating signal producer 252. Using the symbol clock (a) and the area signal (ra) supplied from the area signal generator 251, the DSV reset data generating signal producer 252 produces a signal (dr), during the area indicated by the area signal (ra), for generating the DSV reset data based on the value of k (k') at the end of the immediately-preceding codeword supplied from the latch circuit 22, and applies this signal to the encoder 23.

As shown in FIG. 73, the DSV reset data consists of two words appended immediately following the synchronizing signal area, the codeword sequence being such that the DSV at the end of the synchronizing signal codeword is reset to "0". The DSV at the end of the synchronizing signal codeword is not larger in absolute value terms than the predetermined value n=8 for DSV control in data conversion as previously described, that is, DSV=0, .+-.2, .+-.4, .+-.6, .+-.8. To reset the DSV to 0, the two-word DSV reset data is selected from among the data shown in FIG. 74, for example, so that the DSV at the end of the codeword constructed from the two-word DSV reset data is 0. Any codeword indicated by the data shown in FIG. 74, whether it is connected to the synchronizing signal codeword (LSB is 1) or connected each other, satisfies the codeword "0" run length condition.

When data as shown in FIG. 75 is selected as the two-word data for resetting the DSV to 0, from among the data shown in FIG. 74 according to the value of k at the end of the synchronizing signal codeword, the DSV at the codeword end of the DSV reset data can be made equal to 0. More specifically, in FIGS. 69 to 72, if the output (ra) of the area signal generator 251 is high during the two-word period after the synchronizing signal area at times 3 and 4, and the value of k (k') at the end of the synchronizing signal codeword fed from the latch circuit 22 is -8, then the DSV reset data generating signal producer 252, in synchronism with the symbol clock (a), outputs at time 3 a signal of five bits, for example, "01001" ("9" in decimal number), indicating the output of No. 4 code in FIG. 74, as the data for k'=-8 in FIG. 75, and at time 4 for the second word, a signal "11001" ("25" in decimal number) indicating the output of No. 2 code in FIG. 74. Outside the DSV reset data area, the output of the DSV reset data generating signal producer 252 is "00000". With the signal (dr) fed from the DSV reset data generating signal producer 252, the encoder 23 outputs a codeword "01001001000001" at time 3 and a codeword "01001001000001" at time 4, and the DSV at the codeword end becomes 0, as shown by (x) in FIGS. 71 and 72.

As described above, every input 8-bit data is converted by the encoder 23 into a 14-bit codeword on the basis of the DSV and Pe signal at the end of the immediately preceding codeword as well as the kind of the next codeword and the DSV at the end of it, and in data conversion, each synchronizing signal is followed by a data area for resetting the DSV value at the end of the synchronizing signal codeword to 0; as a result, the change range of the DSV is held within a finite value, i.e. .+-.12 at codeword end and .+-.14 within a codeword sequence, and a DC-free codeword can thus be obtained.

We will now describe a method of reproduction signal decoding wherein an n-bit codeword is reverse-converted into the original m-bit dataword for reproduction in a recording and reproduction apparatus employing the above-described data conversion method of Embodiment 6.

FIG. 76 is a block diagram showing an example of an apparatus for decoding codewords that were encoded by the data conversion method of Embodiment 6. In FIG. 76, the parts indicated at 30, 36, 39, and 40 are identical to the corresponding parts in the apparatus of Embodiment 5 shown in FIG. 65. The numeral 41 designates a serial-parallel converter by which an NRZI-demodulated serial reproduction signal outputted from the NRZI demodulator 30 is converted to a parallel signal. The converted parallel signal is fed to a latch circuit 42 and a sync. signal detector 43. The latch circuit 42 latches the parallel signal fed from the serial-parallel converter 41. The sync. signal detector 43 detects a synchronizing signal in the parallel signal fed from the serial-parallel converter 41, and supplies the reproduction synchronizing signal to a word clock generator 44 and a reset signal generator 45. Using the synchronizing signal from the sync. signal detector 43 and a reproduction channel clock (pa), the word clock generator 44 generates a reproduction word clock, and the parallel signal from the serial-parallel converter 41 is latched into the latch circuit 42 by the reproduction word clock.

Using the synchronizing signal from the sync signal detector 43 and the reproduction word clock from the word clock generator 44, the reset. signal generator 45 discriminates the DSV reset data area described in Embodiment 6, generates a reset signal indicating the resetting of the DSV at the end of that area to 0 and also a signal for resetting the LSB of the codeword in the DSV reset data area to 1, and supplies the respective signals to a k discriminator 46 and an LSB reset circuit 47. Using the reproduction channel clock, the reproduction word clock and the reset signal from the reset signal generator 45, the k discriminator 46 counts the DSV during the reproduction of the reproduction signal being transmitted in synchronism with the reproduction channel clock, discriminates the DSV and Pe at the end of the codeword to determine k=DSV.times.Pe for reproduction, and latches the signal indicating the polarity of k by the reproduction word clock, and the signal is then supplied to the decoding table discriminator 39 to provide the decoding condition for the next codeword to be decoded. As the signal indicating the polarity of k, a "1" is outputted for k.gtoreq.0, and a "0" is outputted for k<0, for example. The LSB reset circuit, 47 resets the LSB of the codeword in accordance with the signal supplied from the reset signal generator 45.

FIGS. 77 and 78 are timing diagrams for explaining in further detail the operation of the circuit described with reference to FIG. 76. In the figures, the signs (pa), (psy), (wcl), etc. correspond to the points indicated by the same signs in the input/output sections of the circuits shown in FIG. 76.

The circuit operation will be described in detail below. The 14-bit parallel signal outputted from the serial-parallel converter 41 is fed to the latch circuit 42 and also to the sync signal detector 43. The sync. signal detector 43 detects a codeword indicating the synchronizing signal in the reproduction signal, and outputs the synchronizing signal (psy) shown in FIGS. 77 and 78. The word clock generator 44 generates the reproduction word clock (wcl) by using the synchronizing signal from the sync. signal detector 43 and the reproduction channel clock (pa). The latch circuit 42 latches the parallel signal inputted from the serial-parallel converter 41 by the reproduction word clock fed from the word clock generator 44, and supplies the word-synchronized reproduced 14-bit codeword (pn) to the decoder 40, while the LSB of the codeword is fed to the flip-flop circuit 36 where it is delayed by one word before it is transferred to the LSB reset circuit 47.

Based on the synchronizing signal (psy) from the sync. signal detector 43 and the reproduction word clock (wcl) from the word clock generator 44, the reset signal generator 45 generates a signal (kr) indicating the DSV reset data area, which is the two-word area immediately succeeding the synchronizing signal as described in Embodiment 6, wherein the signal (kr) is, for example, low within the area and fed to the k discriminator 46; the reset signal generator 45 also generates a signal (lr) indicating the last one word of the DSV reset data area and supplies it to the LSB reset circuit 47. Using the reproduction channel clock the reproduction word clock, and the reset signal from the reset signal generator 45, the k discriminator 46 counts the DSV during the reproduction of the reproduction signal being transmitted in synchronism with the reproduction channel clock, discriminates the DSV and Pe at the end of the codeword to determine k=DSV.times.Pe for reproduction, and latches the signal indicating the polarity of k by the reproduction word clock, and then outputs the signal to provide the decoding condition for the next codeword to be decoded. At this time, the counting of DSV and the calculation of k are performed by resetting the DSV to 0 (k to 0) at the rising edge of the DSV reset data area indicating signal (kr) being outputted from the reset, signal generator 45, i.e., at the end of the codeword corresponding to the DSV reset data. The signal indicating the polarity of k at the end of the immediately preceding codeword, discriminated by the k discriminator 46, is fed to the decoding table discriminator 39.

With the signal (lr) indicating the last one word of the DSV reset data area fed from the reset signal generator 45, the LSB reset circuit, 47 resets the LSB of the codeword in that area to "1" before outputting it, while for other areas, the inputted LSB is outputted without resetting. This is because the LSB of all the codewords shown in FIG. 74 for the DSV reset data area is "1". The output of the LSB reset circuit 47 is supplied to the decoding table discriminator 39. The decoding table discriminator 39 discriminates the decoding table for the current codeword to be decoded on the basis of the signal supplied from the k discriminator 46 and the LSB of the immediately-preceding codeword supplied from the LSB reset, circuit 47, and supplies the result to the decoder 40. At this time, a signal "00" indicating the same decoding table as used in the first decoder 33 in Embodiment 4 is supplied to the decoder 40 when the LSB of the immediately-preceding codeword is "0"; a signal "01" indicating the same decoding table as used in the second decoder 34 in Embodiment 4 is supplied when the LSB of the immediately-preceding codeword is "1" and k.gtoreq.0; and a signal "11" indicating the same decoding table as used in the third decoder 35 in Embodiment 4 is supplied when the LSB of the immediately preceding codeword is "1" and k<0.

The 2-bit control signal outputted from the decoding table discriminator 39 and the 14-bit codeword are inputted to the decoder 40 for decoding: when the control signal bits are "00", the 14-bit codeword is decoded into an 8-bit dataword by using the same conversion table as used in the first decoder 33 in Embodiment 4 in FIG. 64; when the control signal bits are "01", the 14-bit codeword is decoded into an 8-bit dataword by using the same conversion table as used in the second decoder 34; and when the control signal bits are "11", the 14-bit codeword is decoded into an 8-bit dataword by using the same conversion table as used in the third decoder 35.

As described, according to the above decoding method of reverse-converting and decoding reproduced 14-bit codewords into 8-bit datawords in a recording and reproduction apparatus employing the data conversion method of Embodiment 6, the polarity of k is obtained from the DSV and Pe at the end of the immediately preceding codeword in the reproduction signal, and the value of k is reset to 0 in the DSV reset data area placed after the sync signal area, while at the same time, resetting the codeword LSB in the same area. Thus, in the above decoding method, the appropriate conversion table is selected according to the polarity of k and the LSB of the immediately preceding codeword; furthermore, if there occur errors in the reproduction signal, resulting in erroneous DSV counting during reproduction, the DSV at the end of the DSV reset data area can be reset to 0 so that, the correct DSV counting can be performed.

In the above-described decoding method of Embodiment 7, the discriminating signal created from the signal from the k discriminator and the LSB of the immediately preceding codeword is inputted to the decoder along with the codeword to be decoded, and n bits of codeword with discriminating signal bits are decoded into m bits of dataword. It will be recognized, however, that the method of selecting the conversion table according to the condition is not limited to the above-illustrated one. For example, as shown in FIG. 79, three kinds of decoders, the first, second and third decoders, using different conversion tables may be provided, and switching may be performed between decoded datawords, using selectors, according to the discriminating conditions of the polarity of k and the LSB at the end of the immediately preceding codeword; with this configuration also, the same effect as achieved in Embodiment 7 can be obtained.

In FIG. 79, the parts indicated at 30, and 33 to 38 are identical to the corresponding parts in the apparatus of Embodiment 4 shown in FIG. 64, and the parts indicated at 41 to 47 are identical to the corresponding parts in the apparatus of Embodiment 7 shown in FIG. 76.

The operation of Embodiment 8 will be described below. The 14-bit parallel signal outputted from the serial-parallel converter 41 is fed to the latch circuit 42 and also to the sync signal detector 43. The sync. signal detector 43 detects a codeword indicating the synchronizing signal in the reproduction signal, and outputs a synchronizing signal (psy). The word clock generator 44 generates a reproduction word clock (wcl) by using the synchronizing signal from the sync. signal detector 43 and the reproduction channel clock (pa). The latch circuit 42 latches the inputted parallel signal from the serial-parallel converter 41 by the reproduction word clock fed from the word clock generator 44, and outputs a word-synchronized 14-bit codeword which is transferred to the first decoder 33, the second decoder 34 and the third decoder 35, while the LSB of the codeword is fed to the flip-flop circuit 36 where it is delayed by one word before it is transferred to the LSB reset circuit 47.

Based on the synchronizing signal (psy) from the sync. signal detector 43 and the reproduction word clock (wcl) from the word clock generator 44, the reset, signal generator 45 generates a signal (kr) indicating the DSV reset data area, which is the two-word area immediately succeeding the synchronizing signal, then feeding the signal (kr) to the k discriminator 46, and also generates a signal (lr) indicating the last one word of the DSV reset data area and supplies it to the LSB reset circuit 47. Using the reproduction channel clock, the reproduction word clock and the reset signal from the reset signal generator 45, the k discriminator 46 counts the DSV during the reproduction of the reproduction signal being transmitted in synchronism with the reproduction channel clock, discriminates the DSV and Pe at the end of the codeword to determine k=DSV.times.Pe for reproduction, and latches a signal indicating the polarity of k by the reproduction word clock, and then outputs the signal to provide the decoding condition for the next, codeword to be decoded. At this time, the counting of DSV and the calculation of k are performed by resetting the DSV to 0 (k to 0) at the rising edge of the DSV reset data area indicating signal (kr) being outputted from the reset, signal generator 45, i.e., at the end of the codeword corresponding to the DSV reset data. The signal indicating the polarity of k at the end of the immediately-preceding codeword, discriminated by the k discriminator 46, is applied to the selector 37.

With the signal (lr) indicating the last one word of the DSV reset data area supplied from the reset signal generator 45, the LSB reset circuit 47 resets the LSB of the codeword in that area to "1" before outputting it, while for other areas, the input LSB is outputted without resetting. The output of the LSB reset circuit 47 is applied to the selector 38.

Using the signal indicating the polarity of k at the end of the last, decoded signal supplied from the k discriminator 46 as the selection signal, the selector 37 selects the 8-bit data decoded by the second decoder 34 when k.gtoreq.0, or the 8-bit data decoded by the third decoder 35 when k<0, and supplies the selected data to the selector 38. Using the LSB of the last decoded codeword supplied from the LSB reset circuit 47 as the selection signal, the selector 38 selects the 8-bit data outputted from the first decoder 33 when the LSB of the immediately-preceding codeword is "0", or the 8-bit data selected by the selector 37 when the LSB "1", and outputs the selected data as the decoded 8-bit data. Thus, the selector 38 outputs the decoded 8-bit data (dataword), and the same effect as achieved in Embodiment 7 can be obtained.

FIG. 80 is a diagram showing an example of a circuit configuration for an apparatus for implementing the data conversion method of Embodiment 3. In FIG. 80, the parts indicated at 11 to 15 and 17 to 20 are identical to the corresponding parts in the apparatus of Embodiment 3 shown in FIG. 57. The numeral 26 indicates a selector. The numeral 27 is an encoder which contains therein the data conversion tables shown in FIGS. 41 to 55 and a codeword indicating a synchronizing signal. Based on the signal from the selection table decider 15 and a sync. area signal indicating a synchronizing signal area, the encoder 27 selects the data conversion table and the synchronizing signal, and encodes the 8-bit data (d) outputted from the flip-flop circuit 11 into a 14-bit codeword for output. The encoder 27 also outputs 3-bit CDS information associated with the output 14-bit codeword and a 1-bit P signal indicating the state at the end of the output codeword ("1" when P=+1, "0" when P=-1); the CDS information is supplied to the DSV calculator 19 and the P signal to the Pe determiner 20. The same codeword as used to indicate the synchronizing signal in Embodiment 6 is used as the codeword for the synchronizing signal; that is, a codeword "01000101000101" with CDS=+4 and P=-1, which is not used in any of the conversion tables as a codeword corresponding to 8-bit data, is used. This codeword satisfies the codeword "0" run length condition whether the LSB of the immediately-preceding codeword is "0" or "1"; when two words are used in sequence, the DSV and Pe values at the end of the codeword immediately preceding the synchronizing signal are retained also at the end of the second word in the synchronizing signal. Furthermore, the DSV at the end of the codeword immediately preceding the synchronizing signal is not larger in absolute value terms than the predetermined value n=8 for DSV control in data conversion described in Embodiment 3, since the succeeding codeword is the synchronizing signal, not an NG codeword.

Using the symbol clock (a), an ID area signal generator 28 generates an ID area signal indicating an ID codeword area from the sync. area signal (sy) indicating the synchronizing signal area, and supplies it to the select, or 26 and also to an ID data generator 55. The ID codeword is data indicating recording signal channel, segment and other information for special-mode reproduction. In Embodiment 9, one-word data as ID1 indicating the DSV at the end of the synchronizing signal, one-word data as ID2 indicating the recording signal channel, segment number, etc., and a parity signal for the ID data are appended in this order in the block, as shown in FIG. 81. A flip-flop circuit 29 delays the DSV (g) fed from the latch circuit 13 by one dataword by using the symbol clock (a), and supplies the delayed DSV (g') to the ID data generator 55. Based on the ID area signal from the ID area signal generator 28 and the sync. area signal, the ID data generator 55 generates the ID1 codeword data indicating the value of the DSV fed from the flip-flop circuit 29, the ID2 codeword data indicating the channel, segment and other information, and the ID parity signal, and supplies these data to the selector 26. These ID data are selected by the selector 26 using the ID area signal applied from the ID area signal generator 28, and are appended to the input 8-bit data. A flip-flop circuit 56 delays the sync. area signal by one symbol before transferring it to the encoder 27.

FIG. 82 is a diagram showing an example of the ID1 codeword data that the ID data generator 55 generates from the DSV supplied from the flip-flop circuit 29. The ID1 data is generated, as shown, according to the DSV at the end of the synchronizing signal, i.e., the DSV at the end of the immediately-preceding block.

FIGS. 83 to 85 are timing diagrams for explaining in further detail the operation of the circuit described with reference to FIG. 80. In the figures, the signs (a) to (g), (g'), (sy), etc. correspond to the points indicated by the same signs in the input/output sections of the circuits shown in FIG. 80.

The circuit operation will be described in detail below. The sync. area signal (sy) is applied to the ID area signal generator 28 which, based on the symbol clock (a), generates and outputs an ID area signal (id2) indicating the three-symbol ID area succeeding the synchronizing signal, and an ID1 area signal (id1) indicating the ID1 area. In FIGS. 83 and 84, each of the area signals is high to indicate its associated area, and remains low outside that area. The flip-flop circuit 29 produces an output by delaying the DSV (g) fed from the latch circuit 13 by one symbol; in the ID1 area at time 2 in FIGS. 83 to 85, the output (g') indicates the DSV at the end of the codeword immediately preceding the synchronizing signal, i.e., the DSV at the end of the immediately preceding block. The ID data generator 55 generates and outputs the ID codeword data and parity signal, based on the ID area signal (id2) and ID1 area signal (id1) from the ID area signal generator 28 and the sync. area signal (sy); when the ID1 area signal (id1) indicating the ID1 area is high, the ID data generator 55 generates the ID1 data shown in FIG. 82 in accordance with the signal (g') indicating the DSV at the end of the immediately-preceding block supplied from the flip-flop circuit 29. In FIG. 85, since the output (g') of the flip-flop circuit 29 is "-8", "09 " is outputted as the ID1 data. The ID data outputted from the ID data generator 55 is applied to the selector 26 where it is appended to the 8-bit data from the error-correction encoding circuit in accordance with the ID area signal (id2) supplied from the ID area signal generator 28. The 8-bit da[a (c) with the ID data appended thereto outputted from the selector 26 is supplied to the flip-flop circuit 11 as well as to the subcode selection determiner 14. The flip-flop circuit 11 delays the 8-bit data (c) by one dataword by using the symbol clock (a), and transfers the delayed data (d) to the dummy code discriminator 12 and the encoder 27.

The encoding operation thereafter is the same as described in Embodiment 3 shown in FIG. 57: The 8-bit data (d) from the flip-flop circuit 11 and the table selection signal (e) from the latch circuit 13 are inputted to the dummy code discriminator 12 which then converts the 8-bit data (d) to a dummy codeword in accordance with the table selection signal (e). The dummy code discriminator 12 is also supplied with the DSV (g) and Pe signal (f) at the end of the immediately-preceding codeword from the latch circuit 13, and outputs the DSV (i) and Pe signal (h) at the end of the dummy codeword. Furthermore, based on the DSV (i) at the end of the dummy codeword, the Pe signal (h) at the end of the dummy codeword and the LSB of the dummy codeword, the dummy code discriminator 12 discriminates the conversion table to be used for the conversion of the next dummy codeword, and outputs a signal (l) indicating whether to use or not to use the conversion table T3 for the next dummy codeword. The DSV (i) at the end of the dummy codeword, the Pe signal (h) and the signal (l) indicating the selected table for the next dummy codeword, which are outputted from the dummy code discriminator 12, are supplied to the subcode selection determiner 14.

The subcode selection determiner 14 determines whether to use or not to use the subcode for the conversion of the current dataword on the basis of the 8-bit data input (c) and the outputs of the dummy code discriminator 12, i.e. the DSV (i) and Pe signal (h) at the end of the dummy codeword and the signal (l) indicating whether the conversion table T3 is to be used for the next dummy codeword. The subcode selection determiner 14 then outputs a signal (r) which is, for example, high when the subcode is to be used, and low when the main code is to be used. The output (r) of the subcode selection determiner 14 is supplied to the selection table decider 15. Along with the output (r) of the subcode selection determiner 14, the same table selection signal (e) as used to determine the dummy codeword is inputted to the selection table decider 15, which then decides which conversion table is to be used for the conversion of the current dataword, and supplies a 3-bit signal (s) indicating the decided selection table to the encoder 27. Based on the signal (s) from the selection table decider 15 indicating the decided selection table, the encoder 27 selects the conversion table to be used from among the conversion tables shown in FIGS. 41 to 55, and converts the 8-bit data (d) fed from the flip-flop circuit 11 into a 14-bit codeword which is outputted. At this time, if the sync. area signal (sy') delayed by one symbol through the flip-flop circuit 56 is inputted as a high level signal indicating the synchronizing signal area, then the encoder 27 outputs the synchronizing signal codeword "01000101000101" and its associated CDS information and P signal, regardless of the input 8-bit data (d).

The 14-bit codeword outputted from the encoder 27 is fed into the parallel-serial converter 17. This 14-bit codeword (n) is loaded into the parallel-serial converter 17 during a low level period of the symbol clock (a), and is outputted as a serial codeword sequence, with MSB as the leading bit, from the parallel-serial converter 17 in synchronism with the channel clock (b). The codeword sequence outputted from the parallel-serial converter 17 is fed into the NRZI modulator 18 where it is transformed into a signal with its polarity being reversed at every appearance of a "1".

With the above sequence of operations, the 8-bit data (dataword) has been converted into a 14-bit codeword. Next, the DSV at the end of the current codeword and the Pe signal indicating the state at the end of it are obtained, based on which the conversion table to be used For the conversion of the next data is determined. This operation will be described below.

Outside the synchronizing signal area, the encoder 27 outputs a 14-bit codeword along with the CDS information associated with the codeword and the P signal indicating the state at the end of the codeword; on the other hand, in the synchronizing signal area, the synchronizing signal codeword "01000101000101" and its associated CDS information and P signal are outputted. Next, the CDS information is supplied to the DSV calculator 19, and the P signal to the Pe determiner 20. Also, the LSB of the codeword outputted from the encoder 27 is input, ted to the table determiner 21. Using the DSV (g) and Pe signal (f) at the end of the immediately preceding codeword supplied from the latch circuit 13 and the CDS information associated with the current codeword, the DSV calculator 19 calculates the DSV at the end of the codeword, and supplies the result (u) to the table determiner 21 and the latch circuit. 13. Based on the Pe signal (f) at the end of the immediately-preceding codeword supplied from the latch circuit 13 and the P signal of the current codeword supplied from the encoder 27, the Pe determiner 20 determines the Pe signal indicating the state at the end of the codeword, and supplies the result (v) to the table determiner 21 and the latch circuit 13.

In the table determiner 21, the DSV (u) and Pe signal (v) at the end of the current codeword are inputted from the DSV calculator 19 and Pe determiner 20, respectively, and k=DSV.times.Pe at the end of the codeword is calculated. Based on the polarity of this value (k) and the LSB of the codeword, the table determiner 21 determines the conversion table to be used for the next data conversion, and supplies the result (w) to the latch circuit 13. More specifically, the conversion table to be used is determined on the basis of the polarity of k at the end of the codeword and the LSB of the codeword: when the codeword LSB is "0" and k.gtoreq.0, the conversion table T0 is selected; when the LSB is "0" and k<0, the conversion table T1 is selected; when the LSB is "1" and k.gtoreq.0, the conversion table T2 is selected; and when the LSB is "1" and k<0, the conversion table T3 is selected for the next data conversion. The DSV (u) and Pe signal (v) of the codeword and the table selection signal (w) outputted from the table determiner 21 are fed into the latch circuit 13 where these signals are delayed by one symbol period by using the symbol clock (a), to provide the information for the next data conversion.

As described above, every input 8-bit data is converted by the encoder 27 into a 14-bit codeword on the basis of the DSV and Pe signal at the end of the immediately-preceding codeword as well as the kind of the next codeword and the DSV at the end of it, and in data conversion, data indicating the DSV value at the end of the synchronizing signal codeword is appended in the ID codeword immediately succeeding the synchronizing signal; as a result, the change range of the DSV is held within a finite value, i.e. .+-.12 at codeword end and .+-.14 within a codeword sequence, and a DC-free codeword can thus be obtained.

We will now describe a method of reproduction signal decoding wherein an n-bit codeword is reverse-converted into the original m-bit dataword for reproduction in a recording and reproduction apparatus employing the above-described data conversion method of Embodiment 9.

FIG. 86 is a diagram showing an example of a circuit configuration for an apparatus for implementing this decoding method. In FIG. 86, the parts indicated at 30, 36, 39, and 40 to 44 are identical to the corresponding parts in the apparatus of Embodiment 7 shown in FIG. 76. The numeral 60 is an area signal generator which, based on the synchronizing signal from the sync signal detector 43 and the reproduction word clock from the word clock generator 44, discriminates the ID codeword area shown in FIG. 81 in Embodiment 9, and generates a signal (pi2) designating that area and a signal (pi1) designating the ID1 codeword area. The signal (pi2) is supplied to an ID parity check circuit 61 and also to a reset data generator 65, and the signal (pi1) is supplied to an ID data discriminator 62. Using the reproduction channel clock, the reproduction word clock and the ID codeword area signal (pi2) from the area signal generator 60, the ID parity check circuit 61 checks the ID parity for the signal in the ID codeword area of the data decoded by the decoder 40, and outputs, for example, a high level signal to the ID data discriminator 62 when the ID data is correct. Using the reproduction channel clock, the reproduction word clock and the ID1 codeword area signal (pi1) from the area signal generator 60, the ID data discriminator 62 holds the ID1 data carried in the signal in the ID codeword area of the data decoded by the decoder 40, and outputs the thus held ID1 area data to the reset data generator 65 when the signal from the ID parity check circuit 61 goes high (when the ID data is correct).

A DSV counter 63 counts the DSV during the reproduction of the reproduction signal being transmitted in synchronism with the reproduction channel clock, and supplies the result of the count to a k discriminator 64. The k discriminator 64 discriminates the state Pe at the end of the codeword and also k=DSV.times.Pe at the end of the codeword in reproduction on the basis of the DSV supplied from the DSV counter 63, and latches the signal indicating the polarity of k by the reproduction word clock, and then feeds the signal to the decoding table discriminator 39 to provide the decoding condition for the next codeword to be decoded. As the signal indicating the polarity of k, a "1" is outputted for k.gtoreq.0, and a "0" is outputted for k<0, for example. Using the ID1 data from the ID data discriminator 62, the ID codeword area signal from the area signal generator 60 and the reproduction signal, the reset data generator 65 generates signals for resetting the DSV count in the DSV counter 63 and the value of k in the k discriminator 64 by detecting the DSV at the end of the ID codeword area.

FIG. 87 is a diagram showing an example of a circuit configuration for the reset data generator 65. The reset data generator 65 has: an area signal generator 651 which, based on the ID codeword area signal (pi2) from the area signal generator 60 and the reproduction word clock (wcl), generates a signal that is high in the ID codeword area and also in the one-codeword area immediately succeeding the ID codeword area a signal that is high in the one-codeword area immediately succeeding the ID codeword area, and a signal that rises at the end of the codeword immediately succeeding the ID codeword area; a DSV counter 652 that starts counting the DSV from 0 at the start of the ID codeword area and that obtains the DSV over the ID codeword area and the one-codeword area immediately succeeding the ID codeword area; a first DSV reset data producer 653 which obtains the DSV at the end of the ID codeword area from the DSV supplied from the DSV counter 652 and the ID1 data supplied from the ID data discriminator 62, and which supplies the obtained data as DSV reset data to the k discriminator 64; and a second DSV reset data producer 654 which obtains the DSV at the end of the codeword immediately succeeding the ID codeword area from the DSV supplied from the DSV counter 652, the ID1 data supplied from the ID data discriminator 62, and the signal, supplied from the area signal generator 651, that rises at the end of the codeword immediately succeeding the ID codeword area, and which supplies the obtained data as DSV reset data to the DSV counter 63.

FIGS. 88 and 89 are timing diagrams for explaining in further detail the operation of the circuits described with reference to FIGS. 86 and 87. In the Figures, the signs (pa), (psy), (wcl), etc. correspond to the points indicated by the same signs in the input/output sections of the circuits shown in FIG. 86 and 87.

The operation of each circuit will be described in detail below. The 14-bit parallel signal outputted from the serial-parallel converter 41 is fed to the latch circuit 42 and also to the sync. signal detector 43. The sync. signal detector 43 detects a codeword indicating the synchronizing signal in the reproduction signal, and outputs the synchronizing signal (psy) shown in FIGS. 88 and 89. The word clock generator 44 generates the reproduction word clock (wcl) by using the synchronizing signal from the sync. signal detector 43 and the reproduction channel clock (pa). The latch circuit 42 latches the parallel signal inputted from the serial-parallel converter 41 by the reproduction word clock fed from the word clock generator 44, and supplies the word-synchronized reproduced 14-bit codeword (pn) to the decoder 40, while the LSB of the codeword is fed to the flip-flop circuit 36 where it is delayed by one word before it is transferred to the decoding table discriminator 39.

Based on the synchronizing signal (psy) from the sync. signal detector 43 and the reproduction word clock (wcl) from the word clock generator 44, the area signal generator 60 generates the signal (pi2) designating the ID codeword area immediately succeeding the synchronizing signal shown in FIG. 81 in Embodiment 9 as a signal which is, for example, high within that area; the area signal generator 60 also generates the signal (pi1) whose low level period designates the ID1 data area. Using the reproduction channel clock, the reproduction word clock and the reset signal from the reset data generator 65, the DSV counter 63 counts the DSV during the reproduction of the reproduction signal being transmitted in synchronism with the reproduction channel clock, and supplies the count to the k discriminator 64. The k discriminator 64 discriminates the DSV and Pe at the end of the codeword to determine k=DSV.times.Pe for reproduction, and latches the signal indicating the polarity of k by the reproduction word clock, and then outputs the signal to provide the decoding condition for the next codeword to be decoded. At this time, the discrimination of k is performed by resetting the DSV at the end of the ID codeword area by using the reset signal from the reset data generator 65. The signal indicating the polarity of k at the end of the immediately preceding codeword, discriminated by the k discriminator 64, is fed to the decoding table discriminator 39.

The decoding table discriminator 39 discriminates the decoding table for the current codeword to be decoded on the basis of the signal fed from the k discriminator 64 and the LSB of the immediately-preceding codeword fed from the flip-flop circuit 36, anti supplies the result to the decoder 40. At this time, a signal "00" indicating the same decoding table as used in the first decoder 33 in Embodiment 4 is supplied to the decoder 40 when the LSB of the immediately-preceding codeword is "0"; a signal "01" indicating the same decoding table as used in the second decoder 34 in Embodiment 4 is supplied when the LSB of the immediately-preceding codeword is "1" and k.gtoreq.0; and a signal "11" indicating the same decoding table as used in the third decoder 35 in Embodiment 4 is supplied when the LSB of the immediately-preceding codeword is "1" and k<0.

The 2-bit control signal outputted from the decoding table discriminator 39 and the 14-bit codeword are inputted to the decoder 40 for decoding: when the control signal bits are "00", the 14-bit codeword is decoded into an 8-bit dataword by using the same conversion table as used in the first decoder 33 in Embodiment 4 in FIG. 64; when the control signal bits are "01", the 14-bit codeword is decoded into an 8-bit dataword by using the same conversion table as used in the second decoder 34; and when the control signal bits are "11", the 14-bit codeword is decoded into an 8-bit dataword by using the same conversion table as used in the third decoder 35. The thus decoded 8-bit data is outputted.

The 8-bit data outputted from the decoder 40 is transferred to the ID parity check circuit 61 and also to the ID data discriminator 62. In the high level area of the signal (pi2) outputted from the area signal generator 60, designating the ID codeword area succeeding the synchronizing signal, the ID parity check circuit 61 checks the ID parity for the signal in the ID codeword area of the data decoded by the decoder 40, and when the ID data is correct, supplies, for example, a high level signal (ip) to the ID data discriminator 62. The ID data discriminator 62 holds the ID1 data when the ID1 data area designating signal (pi1) from the area signal generator 60 is low, and outputs the thus held ID1 area designating data (d1) to the reset data generator 65 when the signal from the ID parity check circuit 61 goes high (when the ID data is correct). The ID1 data is data indicating the DSV at the end of the synchronizing signal, as described in Embodiment 9.

Next, the operation of the reset data generator 65 will be described. In the reset data generator 65, the area signal generator 651, based on the ID codeword area signal (pi2) from the area signal generator 60 and the reproduction word clock (wcl), generates and outputs a signal (r1) that is high in the ID codeword area and also in the one-codeword area immediately succeeding the ID codeword area, a signal (r2) that rises at the end of the ID codeword area and stays high throughout the one-codeword area immediately succeeding the ID codeword area, and a signal (r3) that rises at the end of the codeword immediately succeeding the ID codeword area. The DSV counter 652, with the reproduction signal inputted thereto, starts counting the DSV from 0 at the start (DSV1 in FIG. 88) of the ID codeword area, obtains the DSV during the period when the signal (r1) from the area signal generator 651 is high, designating the ID codeword area and the succeeding one-codeword area, and supplies the result to the first DSV reset data producer 653 and also to the second DSV reset data producer 654. Along with the DSV from the DSV counter 652, the signal (r2) that rises at the end of the ID codeword area and remains high throughout the one-codeword area immediately succeeding the ID codeword area is supplied from the area signal generator 651 to the first DSV reset data generator 653. The first DSV reset data producer 653 then obtains the DSV at the rising of the signal (r2), i.e. the DSV from the start to the end of the ID codeword area (DSV1 to DSV2 in FIGS. 88 and 89), determines the DSV at the end of the ID codeword area in the codeword sequence on the basis of the first obtained DSV and the ID1 data supplied from the ID1 data discriminator 62, and transfers the result as DSV reset data (dr1) to the k discriminator 64. At this time, the ID1 data from the ID data discriminator 62 indicates the DSV at the end of the synchronizing signal in conversion; the cumulative sum of the DSV from the start to the end of the ID codeword area yields the DSV at the end of the ID codeword area. When the DSV reset data (dr1) that indicates the DSV at the end of the ID codeword area is inputted from the first DSV reset data producer 653, the k discriminator 64 resets the DSV to the inputted DSV value and discriminates the value of k; therefore, the polarity of k at the end of the immediately-preceding codeword which is used for determining the decoding table for decoding the codeword immediately succeeding the ID codeword area, is dependent on the thus reset DSV.

The DSV from the DSV counter 652 is also inputted to the second DSV reset data producer 654 to which the signal (r3) that rises at the end of the codeword immediately succeeding the ID codeword area is supplied from the area signal generator 651. The second DSV reset data producer 654 then obtains the DSV at the rising of the signal (r3), i.e. the DSV from the start of the ID codeword area to the end of the codeword immediately succeeding the ID codeword area (DSV1 to DSV3 in FIGS. 88 and 89), determines the DSV at the end of the codeword immediately succeeding the ID codeword area in the codeword sequence on the basis of the first obtained DSV and the ID1 data supplied from the ID data discriminator 62, and transfers the result as DSV reset data (dr2) to the DSV counter 63. When the DSV from the start of the ID codeword area to the end of the codeword immediately succeeding the ID codeword area is added cumulatively to the DSV indicated by the ID1 data fed from the ID data discriminator 62, the DSV at the end of the codeword immediately succeeding the ID codeword area can be obtained. When the DSV reset data (dr2) indicating the DSV at the end of the codeword immediately succeeding the ID codeword area is inputted from the second DSV reset data producer 654, the DSV counter 63 resets the DSV to the inputted DSV value and starts counting the DSV from the next codeword.

As described, according to the above decoding method of reverse-converting and decoding reproduced 14-bit codewords into 8-bit datawords in a recording and reproduction apparatus employing the data conversion method of Embodiment 9, the polarity of k is obtained from the DSV and Pe at the end of the immediately-preceding codeword in the reproduction signal, and data appended in the ID codeword area and indicating the DSV at the end of the immediately-preceding block is detected, based on which the DSV in reproduction is reset. Thus, in the above decoding method, the appropriate conversion table used for decoding is selected according to the polarity of k and the LSB of the immediately-preceding codeword; furthermore, if there occur errors in the reproduction signal, resulting in erroneous DSV counting during reproduction, the DSV can be reset by the DSV value in the ID codeword so that the correct DSV counting can be performed.

In the above-described decoding method of Embodiment 10, the discriminating signal created from the signal from the k discriminator and the LSB of the immediately-preceding codeword is inputted to the decoder along with the codeword to be decoded, and n bits of codeword with discriminating signal bits are decoded into m bits of dataword. It will be recognized, however, that the method of selecting the conversion table according to the condition is not limited to the above-illustrated one. For example, as shown in FIG. 90, three kinds of decoders, the first, second and third decoders, using different conversion tables may be provided, and switching may be performed between datawords, using selectors, according to the discriminating conditions of the polarity of k and the LSB at the end of the immediately-preceding codeword; with this configuration also, the same effect as achieved in Embodiment 10 can be obtained.

In FIG. 90, the parts indicated at 30, and 33 to 38 are identical to the corresponding parts in the apparatus of Embodiment 4 shown in FIG. 64, the parts indicated at 41 to 44 are identical to the corresponding parts in the apparatus of Embodiment 7 shown in FIG. 76, and the parts indicated at 60 to 65 are identical to the corresponding parts in the apparatus of Embodiment 10 shown in FIG. 86.

The operation of Embodiment 11 will be described below. The 14-bit parallel signal outputted from the serial-parallel converter 41 is fed to the latch circuit 42 and also to the sync. signal detector 43. The sync. signal detector 43 detects a codeword indicating the synchronizing signal in the reproduction signal, and outputs a synchronizing signal (psy). The word clock generator 44 generates a reproduction word clock (wcl) by using the synchronizing signal from the sync. signal detector 43 and the reproduction channel clock (pa). The latch circuit 42 latches the parallel signal inputted from the serial-parallel converter 41 by the reproduction word clock fed from the word clock generator 44, and outputs a word-synchronized 14-bit codeword (pn) which is transferred to the first decoder 33, the second decoder 34 and the third decoder 35, while the LSB of the codeword is fed to the flip-flop circuit 36 where it is delayed by one word before it is transferred to the selector 38.

Based on the synchronizing signal (psy) from the sync. signal detector 43 and the reproduction word clock (wcl) from the word clock generator 44, the area signal generator 60 generates the signal (pi2) designating the ID codeword area succeeding the synchronizing signal shown in FIG. 81 in Embodiment 9; the area signal generator 60 also generates the signal (pi1) whose low level period designates the ID1 data area. Using the reproduction channel clock, the reproduction word clock and the reset signal from the reset data generator 65, the DSV counter 63 counts the DSV during the reproduction of the reproduction signal being transmitted in synchronism with the reproduction channel clock, and supplies the count to the k discriminator 64. The k discriminator 64 discriminates the DSV and Pe at the end of the codeword to determine k=DSV.times.Pe for reproduction, and latches the signal indicating the polarity of k by the reproduction word clock, which and then outputs the signal to provide the decoding condition for the next codeword to be decoded. At this time, the discrimination of k is performed by resetting the DSV at the end of the ID codeword area by using the reset signal from the reset data generator 65. The signal indicating the polarity of k at the end of the immediately-preceding codeword, discriminated by the k discriminator 64, is fed to the decoding table discriminator 39.

Using the signal indicating the polarity of k at the end of the last decoded signal supplied from the k discriminator 64 as the selection signal, the selector 37 selects the 8-bit data decoded by the second decoder 34 when k.gtoreq.0, or the 8-bit data decoded by the third decoder 35 when k<0, and supplies the selected data to the selector 38. Using the LSB of the last decoded codeword supplied from the flip-flop circuit 36 as the selection signal, the selector 38 selects the 8-bit data outputted from the first decoder 33 when the LSB of the immediately-preceding codeword is "0", or the 8-bit data selected by the selector 37 when the LSB is "1", and outputs the selected data as the decoded 8-bit data.

The 8-bit data outputted from the selector 38 is also transferred to the ID parity check circuit 61 and the ID data discriminator 62. In the area of the signal outputted from the area signal generator 60, designating the ID codeword area succeeding the synchronizing signal, the ID parity check circuit, 61 checks the ID parity for the signal in the ID codeword area of the decoded data, and when the ID data is correct, supplies, for example, a high level signal (ip) to the ID data discriminator 62. The ID data discriminator 62 holds the ID1 data when the ID1 data area designating signal (pi1) from the area signal generator 60 is low, and outputs the thus held ID1 area designating data (d1) to the reset data generator 65 when the signal from the ID parity check circuit 61 goes high (when the ID data is correct). The ID1 data is data indicating the DSV at the end of the synchronizing signal, as described in Embodiment 9.

Next, in the reset data generator 65, the area signal generator 651, based on the ID codeword area signal (pi2) from the area signal generator 60 and the reproduction word clock (wcl), generates and outputs a signal (r1) that is high in the ID codeword area and also in the one-codeword area immediately succeeding the ID codeword area, a signal (r2) that rises at the end of the ID codeword area and stays high throughout the one-codeword area immediately succeeding the ID codeword area, and a signal (r3) that rises at the end of the codeword immediately succeeding the ID codeword area. The DSV counter 652, with the reproduction signal inputted thereto, starts counting the DSV from 0 at the start of the ID codeword area, obtains the DSV during the period when the signal (r1) from the area signal generator 651 is high, designating the ID codeword area and the succeeding one-codeword area, and supplies the result to the first DSV reset data producer 653 and also to the second DSV reset data producer 654. Along with the DSV from the DSV counter 652, the signal (r2) that rises at the end of the ID codeword area and remains high throughout the one-codeword area immediately succeeding the ID codeword area is supplied from the area signal generator 651 to the first DSV reset data generator 653. The first DSV reset data producer 653 then obtains the DSV at the rising of the signal (r2), i.e. the DSV from the start to the end of the ID codeword area, determines the DSV at the end of the ID codeword area in the codeword sequence on the basis of the first obtained DSV and the ID1 data supplied from the ID data discriminator 62, and transfers the result as DSV reset data (dr1) to the k discriminator 64. When the DSV reset data (dr1) that indicates the DSV at the end of the ID codeword area is inputted from the DSV reset data producer 653, the k discriminator 64 resets the DSV to the inputted DSV value and discriminates the value of k; therefore, the polarity of k at the end of the immediately-preceding codeword for determining mined the decoding table for decoding the codeword immediately succeeding the ID codeword area, is dependent on the thus reset DSV.

The DSV from the DSV counter 652 is also inputted to the second DSV reset data producer 654 to which the signal (r3) that rises at the end of the codeword immediately succeeding the ID codeword area is supplied from the area signal generator 651. The second DSV reset data producer 654 then obtains the DSV at the rising of the signal (r3), i.e. the DSV from the start of the ID codeword area to the end of the codeword immediately succeeding the ID codeword area, determines the DSV at the end of the codeword immediately succeeding the ID codeword area in the codeword sequence on the basis of the first obtained DSV and the ID1 data supplied from the ID1 data discriminator 62, and transfers the result as DSV reset data (dr2) to the DSV counter 63. When the DSV reset data (dr2) indicating the DSV at the end of the codeword immediately succeeding the ID codeword area is inputted from the second DSV reset data producer 654, the DSV counter 63 resets the DSV to the input DSV value and starts counting the DSV from the next codeword. The decoded 8-bit data (dataword) is thus output from the selector 38, and the same effect as achieved in Embodiment 10 can be obtained.

FIG. 1 shows the modulation parameters obtained with the data conversion method of the present invention, by comparison with those obtained with the prior art methods; in the data conversion method of the present invention, an 8-bit dataword is converted to a 14-bit codeword, with the number of successive 0s between arbitrary data "1" and the next data "1" in the codeword sequence after conversion being one at minimum and five at maximum, and with the diverging range of the DSV of the codeword sequence after conversion being made finite. As shown, in the example of the present invention, Tmax/Tmin=3.0, which shows that Tmax and Tmax/Tmin can be made smaller than those achieved by the prior art 8-14 modulation method, and furthermore, Tw.times.Tmin=0.653, which shows that Tmin and Tw.times.Tmin can be made larger than those achieved by the prior art 8-14 modulation method. As a result, the data conversion method of the invention is much less likely to cause a peak shift due to intersymbol interference, provides good overwrite characteristics, and realizes high-density recording.

As this invention may be embodied in several forms without departing from the spirit of essential characteristics thereof, the present embodiment is therefore illustrative and not restrictive, since the scope of the invention is defined by the appended claims rather than by the description preceding them, and all changes that fall within metes and bounds of the claims, or equivalence of such metes and bounds thereof are therefore intended to be embraced by the claims.