Semiconductor Integrated Circuit Device and Process of Manufacturing the Same

1. A semiconductor integrated circuit device comprising a SRAM having a memory cell, the memory cell including a transfer MISFET to be controlled by a word line and a flip-flop circuit having a driver MISFET and a load MISFET, wherein said semiconductor integrated circuit device comprises: a first conductive film overlying a main surface of a semiconductor substrate and forming a gate electrode of said driver MISFET; a second conductive film overlying the main surface of said semiconductor substrate and forming a gate electrode of said transfer MISFET; a third conductive film overlying said first and second conductive films and forming a gate electrode of said load MISFET; a fourth conductive film overlying said third conductive film and forming a channel region, a source region and a drain region of said load MISFET; a dielectric film overlying said fourth conductive film and covering a memory cell array of the SRAM; a fifth conductive film overlying said dielectric film and covering said memory cell array, said fifth conductive film forming a plate electrode; a capacitance element constituted by said dielectric film, said drain region of said load MISFET and said plate electrode; and an opening in said plate electrode over the channel region at the drain region side of the load MISFET.

2. A semiconductor integrated circuit device according to claim 1, wherein said dielectric film is formed at least partially of a silicon nitride film.

3. A semiconductor integrated circuit device according to claim 2, wherein said silicon nitride film has been removed from a bottom of said opening after said opening has been formed in said plate electrode, and wherein hydrogen has been supplied through said opening to the fourth conductive film forming said load MISFET, by a hydrogenating annealing.

4. A semiconductor integrated circuit device according to claim 3, wherein said silicon nitride film has been removed from regions forming peripheral circuits of the semiconductor integrated circuit device simultaneously as said silicon nitride film has been removed from the bottom of said opening.

5. A semiconductor integrated circuit device according to claim 1, wherein, with respect to a plan view in parallel with said main surface, said drain region and said gate electrode of said load MISFET do not overlap, thereby to form an offset region in said channel region, and wherein said opening is formed in said plate electrode such that said plate electrode does not cover said offset region.

6. A semiconductor integrated circuit device comprising a SRAM having a memory cell, the memory cell including a transfer MISFET to be controlled by a word line and a flip-flop circuit having a driver MISFET and a load MISFET, wherein said semiconductor integrated circuit device comprises: a first conductive film overlying a main surface of a semiconductor substrate and forming a gate electrode of said driver MISFET; a second conductive film overlying the main surface of said semiconductor substrate and forming a gate electrode of said transfer MISFET; a third conductive film overlying said first and second conductive films and forming a channel region, a source region and a drain region of said load MISFET; a fourth conductive film overlying said third conductive film and forming a gate electrode of said load MISFET; a dielectric film overlying said fourth conductive film and covering a memory cell array of said SRAM; a fifth conductive film overlying said dielectric film and covering said memory cell array, said fifth conductive film forming a plate electrode; a capacitance element constituted by said dielectric film, said gate electrode of said load MISFET and said plate electrode; and an opening in said plate electrode over the channel region at the drain region side of the load MISFET.

7. A semiconductor integrated circuit device according to claim 6, with respect to a plan view in parallel with said main surface, said drain region and said gate electrode of said load MISFET do not overlap, thereby to form an offset region in said channel region, and wherein said opening is formed in said plate electrode such that said plate electrode does not cover said offset region.

8. A semiconductor integrated circuit device comprising a SRAM having a memory cell, the memory cell including a transfer MISFET to be controlled by a word line and a flip-flop circuit having a driver MISFET and a load MISFET, wherein said semiconductor integrated circuit device comprises: a first conductive film overlying a main surface of a semiconductor substrate and forming a gate electrode of said driver MISFET; a second conductive film overlying the main surface of said semiconductor substrate and forming a gate electrode of said transfer MISFET; a third conductive film overlying said first and second conductive films and forming a plate electrode; a dielectric film overlying said third conductive film and covering said third conductive film; a fourth conductive film overlying said dielectric film and forming a gate electrode of said load MISFET; a fifth conductive film overlying said fourth conductive film and forming a channel region, a source region and a drain region of said load MISFET; a capacitance element constituted by said dielectric film, said gate electrode of said load MISFET and said plate electrode; and an opening in said plate electrode beneath the channel region at the drain region side of the load MISFET.

9. A semiconductor integrated circuit device according to claim 8, wherein, with respect to a plan view in parallel with said main surface, said drain region and said gate electrode of said load MISFET do not overlap, thereby to form an offset region in said channel region, and wherein said opening is formed in said plate electrode such that said plate electrode is not formed beneath said offset region.

10. A semiconductor integrated circuit device comprising: a semiconductor substrate having a main surface; a plurality of static random access memory cells arranged in a row direction and in a column direction, each of said plurality of static random access memory cells including first and second driver MISFETs and first and second load MISFETs, each of said driver MISFETs having a gate electrode formed over said main surface and source and drain regions formed in said semiconductor substrate; a first insulating film formed over said driver MISFETs so as to cover said main surface; first conductive strips formed over said first insulating film, a source region, a drain region and a channel forming region of each of the first and second load MISFETs being formed in said first conductive strips, said drain regions of said first and second load MISFETs being electrically connected to said drain regions of said first and second driver MISFETs, respectively; gate electrodes of said first and second load MISFETs formed overlying said first insulating film such that a gate insulating film thereof intervenes between said gate electrodes and said first conductive strips, and such that, in a direction perpendicular to said main surface, said gate electrodes and said first conductive strips are laminated to overlap each other, said gate electrodes of said first and second load MISFETs being electrically connected to said drain regions of said second and first driver MISFETs, respectively; a second insulating film formed over said first conductive strips and said gate electrodes of said first and second load MISFETs; and a plate electrode layer formed over said second insulating film, such that one of a respective gate electrode and drain region, of said first and second load MISFETs, said second insulating film, and said plate electrode layer comprises a capacitance element, wherein respective gate electrodes and drain regions of said first and second load MISFETs are not overlapped to form an offset region in said channel forming region thereof in each of said memory cells, and wherein said plate electrode layer has openings such that the plate electrode layer does not cover said offset region.

11. A semiconductor integrated circuit device according to claim 10, wherein said plurality of static random access memory cells constitute a memory cell array, and wherein said plate electrode layer is supplied with the supply voltage from outside of said memory cell array.

12. A semiconductor integrated circuit device according to claim 11, further comprising: power source lines formed over said first insulating film and formed integrally with said first conductive strips, wherein said plate electrode layer and said power source lines are electrically separated from each other in said memory cell array.

13. A semiconductor integrated circuit device according to claim 10, wherein said gate electrodes of said first and second load MISFETs are overlying respective channel forming regions of the first and second load MISFETs.

14. A semiconductor integrated circuit device according to claim 10, wherein said channel forming regions of said first and second load MISFETs are overlying respective gate electrodes of the first and second load MISFETs.

15. A semiconductor integrated circuit device according to claim 10, wherein said driver MISFETs and said load MISFETs are n-channel MISFETs and p-channel MISFETs, respectively, and wherein each of said first conductive strips is comprised of a silicon film.

16. A semiconductor integrated circuit device according to claim 15, further comprising: a third insulating film overlying said plate electrode layer so as to cover said main surface; and a silicon nitride film overlying said third insulating film and having such a thickness as to be permeable to hydrogen but not to humidity.

17. A semiconductor integrated circuit device according to claim 10, wherein said openings in said plate electrode layer extend such that the plate electrode layer does not cover a region between the drain region and the channel forming region of the first and second load MISFETs.

18. A semiconductor integrated circuit device according to claim 10, wherein said openings in said plate electrode layer extend such that the plate electrode layer leaves uncovered an entirety of the channel forming regions of the first and second load MISFETs.

19. A semiconductor integrated circuit device according to claim 18, wherein said openings in said plate electrode layer extend such that the plate electrode layer does not cover a region between the drain region and the channel forming region of the first and second load MISFETs.

20. A semiconductor integrated circuit device according to claim 10, wherein said openings have a rectangular shape.

21. A semiconductor integrated circuit device according to claim 10, wherein each of said openings have a shape of a band, extending in said row direction, to expose said offset regions of said memory cells arranged in said row direction.

22. A semiconductor integrated circuit device according to claim 10, wherein said gate electrodes of said first and second load MISFETs are provided over said first conductive strips, and wherein said openings of said plate electrode layer are provided above offset regions where respective gate electrodes and drain regions of said first and second load MISFETs are not overlapped.

23. A semiconductor integrated circuit device according to claim 10, wherein said first conductive strips are provided over said gate electrodes of said first and second load MISFETs, and wherein said openings of said plate electrode layer are provided above offset regions where respective gate electrodes and drain regions of said first and second load MISFETs are not overlapped.

24. A semiconductor integrated circuit device according to claim 10, wherein each of the plurality of static random access memory cells further includes first and second transfer MISFETs, the first and second transfer MISFETs each including source and drain regions in the semiconductor substrate and a gate electrode overlying the semiconductor substrate, and wherein the semiconductor integrated circuit device further includes pad layers electrically connected to the source or drain regions of the first and second transfer MISFETS, and the plate electrode layer had additional openings for exposing said pad layers.