Thin Film Transistor, Solid Device, Display Device and Manufacturing Method of a Thin Film Transistor

1. A method for manufacturing a thin film transistor on a substrate, comprising the steps of: forming a thin silicon film on the substrate; forming a source area, a drain area and a channel area in the silicon film by implanting impurities of a predetermined type to selected portions of the silicon film where the source and drain areas are to be formed, the channel area being formed between the source area and the drain area;. forming a gate insulation film on the channel area and at least a portion of the source and drain areas; after forming the source and drain areas, forming a gate electrode having a first end and a second end on the gate insulation film over the channel area such that the first end overlaps one end of the source area and the second end overlaps one end of the drain area; forming an interlayer insulation film over the gate electrode and the gate insulation film; forming two contact holes in the interlayer insulation film and the gate insulation film to expose a portion of the source and drain area, respectively; implanting impurities of the predetermined type to the exposed portion of the source and drain area to form a high impurity concentration area in the source and drain areas, respectively; and forming a source electrode and a drain electrode in the respective contact holes to connect to the respective high impurity concentration areas.

2. The method of claim 1, further comprising, after the step of forming the source, drain and channel areas, the step of performing a crystalline treatment on the silicon film.

3. A method for manufacturing a thin film transistor on a substrate, comprising the steps of: forming a first thin silicon film containing a low concentration of impurities of a predetermined type on the substrate; selectively etching the first thin silicon film so as to form a source area and a drain area in the first thin silicon film; forming a second thin silicon film on the substrate as a channel area to connect between the source and drain areas; forming a gate insulation film on the channel area and at least a portion of the source and drain areas; forming a gate electrode having a first end and a second end on the gate insulation film over the channel area such that the first end substantially overlaps one end of the source area and the second end substantially overlaps one end of the drain area; forming a mask coveting the gate electrode and a predetermined area of the source and drain areas; and implanting impurities of the predetermined type to the source and drain areas such that the areas of the source and drain area uncovered by the mask become high impurity concentration areas.

4. The method of claim 3 wherein the second thin film is formed so as to partially overlap the source and drain areas.

5. The method of claim 3, further comprising the steps of: forming an interlayer insulation film over the gate electrode and the gate insulation film; forming two contact holes in the interlayer insulation film and the gate insulation film to expose a portion of the predetermined area of the source and drain areas, respectively; and forming a source electrode and a drain electrode in the respective contact holes to connect to the predetermined area of the source and drain areas, respectively.

6. A method for manufacturing a thin film transistor on a substrate, comprising the steps of: forming a first thin silicon film containing a high concentration of impurities of a predetermined type on the substrate; selectively etching the first thin silicon film so as to form a first area and a second area in the first thin silicon film as high impurity concentration areas; forming a second thin silicon film connecting between the first and second areas on the substrate, the second silicon film including a third area, a fourth area and a fifth area connecting between the third and fourth areas; implanting a low concentration of impurities of the predetermined type to the third and fourth areas in the second thin silicon film so that the first and third areas form a source area, the second and fourth areas form a drain area and the fifth area forms a channel area connecting between the source and drain areas; forming a gate insulation film on the channel area and at least a portion of the source and drain areas; and forming a gate electrode having a first end and a second end on the gate insulation film over the channel area such that the first end overlaps one end of the source area and the second end overlaps one end of the drain area.

7. The method of claim 6, further comprising, after the step of implanting a low concentration of impurities, the step of performing a crystalline treatment on the first and second than silicon films.

8. The method of claim 6 wherein the second thin silicon film is formed so as to partially overlap the first and second areas.

9. A method for manufacturing a CMOS circuit including two thin film transistors of two different types on a substrate, comprising the steps of; forming a first thin silicon film on the substrate; selectively etching the first thin silicon film to form first, second, third and fourth areas in the first thin silicon film; implanting a low concentration of impurities of a first conductivity type to the first and second areas to form source and drain areas, respectively, of a first thin film transistor; implanting a low concentration of impurities of a second conductivity type opposite to the first conductivity type to the third and fourth areas to form source and drain areas, respectively, of a second thin film transistor; forming a second thin silicon film on the substrate as a channel area of the first transistor connecting between the source and drain areas of the first transistor as well as a third thin silicon film on the substrate as a channel area of the second transistor connecting between the source and drain areas of the second transistor; forming a gate insulation film on the source, drain and channel areas of the two thin film transistors; and forming two gate electrodes over the two channel areas, respectively, each gate electrode having a first end and a second end with the first end overlapping one end of the respective source area and the second end overlapping one end of the respective drain area.

10. The method of claim 9, further comprising the steps of: forming an interlayer insulation film over the two gate electrodes and the gate insulation film; forming four contact holes in the interlayer insulation film and the gate insulation film to expose a portion of the two source areas and the two drain areas, respectively; implanting impurities of the first conductivity type to the exposed portion of the source and drain areas of the first transistor to form a high impurity concentration area therein, respectively; implanting impurities of the second conductivity type to the exposed portion of the source and drain areas of the second transistor to form a high impurity concentration area therein, respectively; and forming two source electrodes and two drain electrodes in the respective contact holes to connect to the respective high impurity concentration areas.

11. The method of claim 9 wherein the second thin silicon film is formed so as to partially overlap the source and drain areas of the first transistor, and the third thin silicon film is formed so a to partially overlap the source and drain areas of the second transistor.

12. A method for manufacturing a liquid crystal display (LCD) circuit including three thin film transistors on a substrate, comprising the steps of: forming a thin silicon film including first, second and third regions on the substrate; implanting impurities of a first conductivity type to the selected portions of the first and second regions where respective source and drain areas of first and second transistors are to be formed; selectively etching the silicon film so as to form a source area, a drain area and a channel area in each of the first and second regions for the first and second transistors respectively with the respective channel area being formed between the respective source and the drain areas and to form a pattern in the third region; forming a gate insulation film on the three regions; forming first, second and third gate electrodes on the first, second and third regions, respectively, each of the first and second gate electrodes being formed on the respective channel area and having a first end and a second end with the first end overlapping one end of the respective source area and the second end overlapping one end of the respective drain area; and implanting impurities of a second conductivity type opposite to the first conductivity type to the pattern in the third region with the third gate electrode being used as a mask to form source, drain and channel areas for a third transistor with the channel area of the third transistor being formed under the third gate electrode; wherein the step of forming the three gate electrodes includes forming a fourth gate electrode on the gate insulating film over the drain area of the second transistor and wherein the drain area of the second transistor includes an extended part which forms a storage capacitance with the fourth gate electrode.

13. The method of claim 12 wherein the first and third transistors are formed as CMOS transistors.

14. The method of claim 12 wherein the source and drain areas of the first and second transistors are formed as low impurity concentration areas.

15. A method for manufacturing a liquid crystal display (LCD) circuit including first, second and third thin film transistors on first, second and third regions of a substrate, respectively, the method comprising the steps of; forming a thin silicon film containing a high concentration of impurities of a first conductivity type on the substrate; selectively etching the thin silicon film to form first and second areas on the first region and third and fourth areas on the second region; forming a first silicon pattern on the first region connecting between the first and second areas, a second silicon pattern on the second region connecting between the third and fourth areas, and a third silicon pattern on the third region, the first and second silicon patterns each including a first portion, a second portion and a third portion connecting between the first and second portions; implanting a low concentration of impurities of the first conductivity type to the first and second portions of the first and second patterns respectively, so that the first area and the first portion of the first silicon pattern form a source area of a first transistor and the second area and the second portion of the first silicon pattern form a drain area of the first transistor, the third area and the first portion of the second silicon pattern form a source area of a second transistor and the fourth area and the second portion of the second silicon pattern form a drain area of the second transistor, and the third portion of each of the first and second silicon patterns forms a channel area of the respective transistors; forming a gate insulation film on the three regions of the substrate; forming first, second and third gate electrodes on the first, second and third regions, respectively, each of the first and second gate electrodes being formed over the respective channel area and having a first end and a second end with the first end overlapping one end of the respective source area and the second end overlapping one end of the respective drain area; and implanting a high concentration of impurities of a second conductivity type opposite to the first conductivity type to the third silicon pattern with the third gate electrode being used as a mask to form source and drain areas of a third thin film transistor and a channel area between the source and drain areas of the third transistor.

16. The method of claim 15, further comprising, after the step of forming the gate insulation film, the step of activating the implanted impurities.

17. The method of claim 15, wherein the step of forming the three gate electrodes includes forming a fourth gate electrode on the gate insulation film over the drain area of the second transistor and wherein the fourth area in the drain area of the second transistor includes an extended part which forms a storage capacitance with the fourth gate electrode.

18. The method of claim 15 wherein the first silicon pattern is formed so as to partially overlap the first and second areas, and the second silicon pattern is formed so as to partially overlap the third and fourth areas.

19. A method for manufacturing a liquid crystal display (LCD) circuit including first, second and third thin film transistors on first, second and third regions of a substrate, respectively, the method comprising the steps of: forming a thin silicon film on the substrate; selectively etching the thin silicon film to form first and second areas on the rest region, third and fourth areas on the second region, and fifth and sixth areas on the third region, the first and second areas each including a first part and a second part; implanting impurities of a first conductivity type to the six areas; forming first, second and third channel areas on the substrate connecting between the first and second areas, the third and fourth areas, and the fifth and six areas, respectively; forming a gate insulation film on the three regions of the substrate; forming first, second and third gate electrodes on the gate insulation film over the first, second and third channel areas, respectively, the first gate electrode overlapping the first parts of the first and second areas on the first region; implanting a high concentration of impurities of the first conductivity type to the second part of the first and second areas and the third and fourth areas with the second gate electrode being used as a mask, so that source areas and drain areas of the first and second transistors are formed, respectively; and implanting a high concentration of impurities of a second conductivity type opposite to the first conductivity type to the fifth and sixth areas using the third gate electrode as a mask to form a source area and a drain area of the third transistor.

20. The method of claim 19 wherein the first channel area is formed so as to partially overlap the first and second areas, the second channel areas is formed so as to partially overlap the third and fourth area, and the third channel area is formed so as to partially overlap the fifth and sixth areas.