US 5,506,543 AGrant
Circuitry for Bias Current Generation
Issue Date:1996-04-09
•18 Claims
•2 Drawing Sheets
Abstract
The circuit for generating current has a controllable current source M.sub.7, an input transistor pair 24 having a first branch and a second branch, a current mirror 28 having a first branch and a second branch, and an amplifier 50. The controllable current source M.sub.7 is coupled to the first and second branches of the input transistor pair 24. The first branch of the current mirror 28 is coupled to the first branch of the input transistor pair 24. The second branch of the current mirror 28 is coupled to the second branch of the input transistor pair 24. The input transistor pair 24 is coupled between the controllable current source M.sub.7 and the current mirror 28. The amplifier 50 has an output coupled to the controllable current source M.sub.7, and a first input coupled to the second branch of the input transistor pair 24 and the second branch of the current mirror 28.
Metadata
Assignee
- Texas Instruments Incorporated
Inventor
- Henry T. Yung
Application Information
Application Number:US 3557146
Filing Date:1994-12-14
Priority Date:1994-12-14
Art Unit:255
Classifications
IPC:
H03F 345
Field of Search:
330323253;257;261;292;259313;314;315;316
Patent Drawings (2 sheets)
Description
Field of the Invention
This invention generally relates to electronic systems and in particular it relates to bias current generation for electronic systems.
Background of the Invention
A variety of integrated circuit devices, such as operational amplifiers, require the generation of a stable bias current by a portion of the device. The bias current is used to set the magnitude of the currents used to power the various components of the device. It is very important that the bias current remain as near as possible to a predetermined level to insure that the total current required by the integrated circuit device is predictable.
A variety of forces acting upon the integrated circuit device can create fluctuations in the bias current level. Three significant forces are the ambient temperature in which the device is operating, which causes bias current fluctuations, and the variations which are introduced in the device during the construction of the device, which affect the magnitude of the bias current, and supply voltage variations.
Summary of the Invention
Generally, and in one form of the invention, a circuit for generating current has a controllable current source, an input transistor pair, a current mirror, and an amplifier. The controllable current source is coupled to the first and second branches of the input transistor pair. The first branch of the current mirror is coupled to the first branch of the input transistor pair. The second branch of the current mirror is coupled to the second branch of the input transistor pair. The input transistor pair is coupled between the controllable current source and the current mirror. The amplifier has an output coupled to the controllable current source, and a first input coupled to the second branch of the input transistor pair and the second branch of the current mirror.
This invention provides several advantages. One advantage of this invention is that it is insensitive to body effect of transistors. Another advantage is that it can generally be used to control behavior of the drain saturation voltage of transistors.
Brief Description of the Drawings
In the drawings:
FIG. 1 is a schematic diagram of a first preferred embodiment bias current circuit;
FIG. 2 is a schematic diagram of a prior art bias current circuit;
FIG. 3 is a schematic diagram of a second preferred embodiment bias current circuit.
FIG. 4 is a schematic diagram of a third preferred embodiment bias current circuit.
Detailed Description of Preferred Embodiments
Referring to FIG. 1, a circuit diagram of a first preferred embodiment bias current circuit according to the invention is shown. The circuit includes MOSFET's M.sub.1 -M.sub.8, capacitor C.sub.1, input voltage .DELTA.V.sub.GS, and bias voltage V.sub.DD. In this embodiment, transistors M.sub.1, M.sub.2, M.sub.6, M.sub.7, and M.sub.8 are p-channel transistors. Transistors M.sub.3, M.sub.4, and M.sub.5 are n-channel transistors. Transistors M.sub.1 and M.sub.2 each form a branch of the input transistor pair 24. Transistors M.sub.6 -M.sub.8 each form a branch of the current mirror 26 that is controlled by the voltage at node 20. Transistors M.sub.3 and M.sub.4 each form a branch of the current mirror 28 that is controlled by the voltage at node 22.
In the first preferred embodiment bias current circuit, shown in FIG. 1, let the width-to-length ratio of transistor M.sub.n be given by (W/L).sub.n, where n=1, 2, . . ., 8. Let (W/L).sub.3 =(W/L).sub.4 =(W/L).sub.5, (W/L).sub.6 =1/2(W/L).sub.7 =(W/L).sub.8, (W/L).sub.1 >(W/L).sub.2. All the transistors are biased at the saturation region. With a positive voltage of .DELTA.V.sub.GS applied across the gates of M.sub.1 and M.sub.2, ##EQU1##
V.sub.GS2 is the gate to source voltage for transistor M.sub.2. V.sub.GS1 is the gate to source voltage for transistor M.sub.1. V.sub.T is the threshold voltage for transistors M.sub.2 and M.sub.1. .mu. is the majority carrier mobility. C.sub.0X is the gate capacitance per unit area of transistors M.sub.2 and M.sub.1. I.sub.1 is the current flowing through transistors M.sub.1 and M.sub.2.
The following equation for the current I.sub.1 is then derived from the above equation for .DELTA.V.sub.GS : ##EQU2##
The above equation shows that the current I.sub.1 is proportional to the square of .DELTA.V.sub.GS. When this current is used to bias a transistor M.sub.X with the same .mu.C.sub.0X in the saturation region, ##EQU3##
The factor K is independent of temperature and well controlled since it depends only on the width-to-length ratios of the transistors. Thus, .vertline.V.sub.GSX -V.sub.T .vertline. is directly proportional to .DELTA.V.sub.GS. Different useful properties can be obtained from the current I.sub.1 depending on the nature of .DELTA.V.sub.GS. Two of the possible applications are described below.
One application of the first preferred embodiment of FIG. 1 is an enhancement of a prior art bias circuit. The basic structure of the prior art bias circuit is shown in FIG. 2. The prior art circuit of FIG. 2 includes MOSFET's M.sub.10 -M.sub.14 ; bipolar transistors Q.sub.1 and Q.sub.2 ; .DELTA.V.sub.BE voltage between nodes 32 and 34; and bias voltage V.sub.DD. The channel width-to-length ratio of MOSFET M.sub.10 is 2 times that of MOSFET M.sub.11. Bipolar transistor Q.sub.2 is 10 times the size of bipolar transistor Q.sub.1. MOSFET's M.sub.12, M.sub.13, and M.sub.14 all have the same channel width-to-length ratio. With the same amount of current I.sub.2 going through the bipolar transistors Q.sub.1 and Q.sub.2, the voltage .DELTA.V.sub.BE is relatively insensitive to the absolute value of I.sub.2. The current I.sub.2 is given approximately by the following equation: ##EQU4##
In the prior art circuit of FIG. 2, M.sub.10 and M.sub.11 tend to have different V.sub.T 's (threshold voltages) due to the body effect. This can generate quite a significant amount of error in the current I.sub.2. This problem can be solved by using the circuit in FIG. 1 with .DELTA.V.sub.BE applied as .DELTA.V.sub.GS in the equation for I.sub.1. In FIG. 1, since M.sub.1 and M.sub.2 have their sources tied together, their V.sub.T 's tend to match. In addition, the voltage .DELTA.V.sub.BE can be easily multiplied with various circuit techniques before being applied as .DELTA.V.sub.GS in FIG. 1, thus adding flexibility to circuit implementation.
Another application of the first preferred embodiment, shown in FIG. 1, is obtained by applying a temperature independent voltage as .DELTA.V.sub.GS in FIG. 1. This voltage can be derived, for example, from a bandgap voltage reference. From the equation above for (V.sub.GSX -V.sub.T), it can be seen that (V.sub.GSX -V.sub.T) will then be independent of temperature. When this current is used to bias an operational amplifier with the input transistors having the same .mu.C.sub.0X, any temperature independent input offset voltage can be corrected by steering different portions of current through the input transistors. This correction will remain valid under different temperatures. To achieve the same .mu.C.sub.0X, the same type of input transistors (M.sub.1 and M.sub.2) can be used in the bias circuit shown in FIG. 1. For instance, an N-channel input pair can be used in the bias circuit to match an N-channel input pair in an operational amplifier.
Of course, the applications of the first preferred embodiment of FIG. 1 are not limited to the ones described above. The structure shown in FIG. 1 can obviously be flipped over with N-channel transistors as the input pair (M.sub.1 and M.sub.2). Cascode transistors can be added to enhance the performance of this bias circuit. In general, a start-up circuit may be desired to make the bias circuit operate in the proper region. Compensation will also be needed to keep the bias circuit stable. This is accomplished by the compensation capacitor C.sub.1 shown in FIG. 1.
Referring to FIG. 3, a circuit diagram of a second preferred embodiment bias current circuit according to the invention is shown. The circuit includes MOSFET's M.sub.21 -M.sub.45, capacitor C.sub.2, input voltage .DELTA.V.sub.GS, and bias voltage V.sub.DD.
The second preferred embodiment, shown in FIG. 3, operates in the same way as the first preferred embodiment, shown in FIG. 1. Transistors M.sub.21 -M.sub.24, shown in FIG. 3, take the place of transistor M.sub.7, shown in FIG. 1. Transistors M.sub.25 and M.sub.26 take the place of transistor M.sub.1. Transistor M.sub.27 takes the place of transistor M.sub.2. Transistors M.sub.28 -M.sub.31 form a cascode current mirror which takes the place of the current mirror formed by transistors M.sub.3 and M.sub.4. Transistors M.sub.28 and M.sub.9 preferably have low V.sub.T 's structure shown in FIG. 1 can obviously be flipped over with N-channel Transistors M.sub.21 -M.sub.24 and M.sub.32 -M.sub.35 form a cascode current mirror which takes the place of the current mirror formed by transistors M.sub.6 -M.sub.8. Transistors M.sub.36 and M.sub.37 take the place of transistor M.sub.5. Transistor M.sub.36 preferably has a low V.sub.T. Capacitor C.sub.2 is a compensation capacitor. Transistors M.sub.38 -M.sub.42 form a start-up circuit which forces the bias circuit to operate in the proper region. Transistors M.sub.43 -M.sub.45 form an output switch. Transistors M.sub.42 and M.sub.45 serve as capacitors.
Table 1 itemizes the critical components of the second preferred embodiment shown in FIG. 3. As an illustration and not a limitation, the designations and electrical parameters are included.
The third preferred embodiment, shown in FIG. 4, operates similar to the first preferred embodiment, shown in FIG. 1. Transistors M.sub.1 -M.sub.4 and M.sub.7 are the same as in FIG. 1. Transistors M5 and M6 of FIG. 1 have been replaced by amplifier 50 in FIG. 4. Amplifier 50 has an optional connection to node 52. Transistor M.sub.7 serves as a controllable current source that is controlled by the output of amplifier 50. An output current can be mirrored from any of transistors M.sub.7, M.sub.3, and M.sub.4.
This invention provides several advantages. One advantage of this invention is that it is insensitive to body effect of transistors. Another advantage is that it can generally be used to control behavior of the drain saturation voltage of transistors.
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.
Claims
What is claimed is:
1. A circuit for generating current comprising: a controllable current source; an input transistor pair having a first branch and a second branch, the controllable current source is coupled to the first and second branches of the input transistor pair; a current mirror having a first branch and a second branch, the first branch of the current mirror is coupled to the first branch of the input transistor pair, the second branch of the current mirror is coupled to the second branch of the input transistor pair, the input transistor pair is coupled between the controllable current source and the current mirror; and an amplifier having an output coupled to the controllable current source, a first input coupled to the second branch of the input transistor pair and the second branch of the current mirror, and a second input coupled to the first branch of the input transistor pair and the first branch of the current mirror.
2. The circuit of claim 1 wherein the controllable current source is a transistor.
3. A circuit for generating current comprising: a first current mirror having a first branch, a second branch, and a third branch; an input transistor pair having a first branch and a second branch, the first branch of the first current mirror is coupled to the first and second branches of the input transistor pair; a second current mirror having a first branch and a second branch, the first branch of the second current mirror is coupled to the first branch of the input transistor pair, the second branch of the second current mirror is coupled to the second branch of the input transistor pair, the input transistor pair is coupled between the first current mirror and the second current mirror; a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor is coupled to the second branch of the first current mirror, the control terminal of the first transistor is coupled to the second branch of the input transistor pair and the second branch of the second current mirror; and a start up circuit coupled to the first terminal of the first transistor.
4. The circuit of claim 3 wherein the first current mirror comprises: a second transistor having a control terminal, the second transistor forms the first branch of the first current mirror; a third transistor having a control terminal, the third transistor forms the second branch of the first current mirror, the control terminal of the third transistor is coupled to the first transistor and the control terminal of the second transistor; and a fourth transistor having a control terminal, the fourth transistor forms the third branch of the first current mirror, the control terminal of the fourth transistor is coupled to the control terminal of the third transistor.
5. The circuit of claim 4 wherein the second, third, and fourth transistors are the same size.
6. The circuit of claim 3 wherein the input transistor pair comprises: a second transistor which forms the first branch of the input transistor pair; and a third transistor which forms the second branch of the input transistor pair.
7. The circuit of claim 6 wherein an input voltage is applied between a control terminal of the second transistor and a control terminal of the third transistor.
8. The circuit of claim 3 wherein the second current mirror comprises: a second transistor having a control terminal, the second transistor forms the first branch of the second current mirror, the control terminal of the second transistor is coupled to the first branch of the input transistor pair; and a third transistor having a control terminal, the third transistor forms the second branch of the second current mirror, the control terminal of the third transistor is coupled to the control terminal of the second transistor.
9. The circuit of claim 8 wherein the second and third transistors are the same size.
10. The circuit of claim 3 further comprising a capacitor coupled between the second branch of the first current mirror and the second branch of the second current mirror.
11. A circuit for generating current comprising: a first current mirror having a first branch, a second branch, and a third branch, the first branch of the first current mirror has a first terminal and a second terminal, the second branch of the first current mirror has a first terminal and a second terminal, and the third branch of the first current mirror has a first terminal and a second terminal; an input transistor pair having a first branch and a second branch, the first branch of the input transistor pair has a first terminal and a second terminal, and the second branch of the input transistor pair has a first terminal and a second terminal, the first terminal of the first branch of the first current mirror is coupled to the first terminal of both the first and second branches of the input transistor pair; a second current mirror having a first branch and a second branch, the first branch of the second current mirror has a first terminal and a second terminal, and the second branch of the second current mirror has a first terminal and a second terminal, the first terminal of the first branch of the second current mirror is coupled to the second terminal of the first branch of the input transistor pair, the first terminal of the second branch of the second current mirror is coupled to the second terminal of the second branch of the input transistor pair; a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor is coupled to the first terminal of the second branch of the first current mirror, the control terminal of the first transistor is coupled to the first terminal of the second branch of the second current mirror; and a start up circuit coupled to the first terminal of the first transistor.
12. The circuit of claim 11 wherein the second terminals of the first, second, and third branches of the first current mirror are coupled together.
13. The circuit of claim 11 further comprising a control terminal of the first current mirror coupled to the first terminal of the second branch of the first current mirror.
14. The circuit of claim 11 wherein the second terminals of the first and second branch of the second current mirror are coupled together.
15. The circuit of claim 11 further comprising a control terminal of the second current mirror coupled to the first terminal of the first branch of the second current mirror.
16. The circuit of claim 11 wherein the second terminal of the first transistor is coupled to the second terminal of the second branch of the second current mirror.
17. The circuit of claim 11 further comprising a control terminal of the first branch of the input transistor pair and a control terminal of the second branch of the input transistor pair, an input voltage is coupled between the control terminal of the first branch of the input transistor pair and the control terminal of the second branch of the input transistor pair.
18. The circuit of claim 11 further comprising an output switch coupled to the first terminal of the third branch of the first current mirror.