Liquid Crystal Display Device Capable of Compensating for a Positioning Error Between a Drain Line and a Display Electrode

This invention relates to a liquid crystal display device and, more particularly, to an active matrix liquid crystal display device.

As will later be described, a conventional active matrix liquid crystal display device of the type described, comprises a liquid crystal panel. The liquid crystal panel comprises an insulating film and a plurality of thin-film transistors, each of which has a drain electrode and a source electrode.

Each of drain lines is of a first conductive material. The drain lines are formed on the insulating film and connected to the drain electrodes of the thin-film transistors, respectively.

Each of the display electrodes is of a second conductive material which is different from the first conductive material. The display electrodes are formed on the insulating film and connected to the source electrodes of the thin-film transistors, respectively.

Inasmuch as the display electrodes are different in material from the drain lines, the display electrodes and the drain lines are formed at different patterning steps. As a result, positioning errors inevitably occur between the drain lines and the display electrodes. This results in non-uniformity of capacitances between the drain line and the display electrode for one of the thin-film transistors and between the display electrode for the thin-film transistor in question and the drain line for an adjacent one of the thin-film transistors. The adjacent one of the thin-film transistors is nearer the display electrode for the thin-film transistor in question rather than the drain line for the thin-film transistor in question.

Inasmuch as the non-uniformity of the capacitances results in degradation of display quality of the display device, it is required to compensate for the non-uniformity of the capacitances.

In Japanese Utility Model Publication No. B586/1993, another display device is disclosed which comprises auxiliary lines, each of which is of the second conductive material. The auxiliary lines are formed on the drain lines simultaneously with the display electrodes. However, inasmuch as each auxiliary line has the same shape or width as each drain line has, it is difficult to compensate for the non-uniformity of capacitances between the drain line and the display electrode for the thin-film transistor in question and between the display electrode for the thin-film transistor in question and the drain line for the adjacent one of the thin-film transistors that is adjacent to the display electrode for the thin-film transistor in question.

It is therefore an object of this invention to provide an active matrix liquid crystal display device which can compensate for non-uniformity of capacitances between a drain line and a display electrode for a particular one of thin-film transistors and between the display electrode for the particular one of the thin-film transistors and another drain line for an adjacent one of the thin-film transistors that is nearer to the display electrode for the particular one of the thin-film transistors rather than the drain line for the particular one of the thin-film transistors.

It is another object of this invention to provide an active matrix liquid crystal display device of the type described, which has a high display quality.

Other objects of this invention will become clear as the description proceeds.

According to one aspect of this invention, there is provided an active matrix liquid crystal display device including a glass substrate and a plurality of thin-film transistors formed on the glass substrate in a matrix form. Each of the thin-film transistors comprises a semiconductor film, a gate electrode, a gate insulating film intervening between the gate electrode and the semiconductor film, a first electrode formed in contact with said semiconductor film, a second electrode formed in the semiconductor film apart from the first electrode, a first bus line arranged in a row direction in contact with the gate electrode, a second bus line arranged in a column direction in contact with the first electrode, a display electrode formed in contact with the second electrode along the second bus line apart from the second bus line, and a compensating conductive layer formed in contact with one of the second bus line and the display electrode. The compensating conductive layer has a portion projecting from the above-mentioned one of the second bus line and the display electrode towards the other of the second bus line and the display electrode to thereby keep a distance between the portion of the compensating conductive film and the other of the second bus line and the display electrode constant.

According to another aspect of this invention, there is provided an active matrix liquid crystal display device comprising a liquid crystal panel comprising: an insulating film and; a plurality of thin-film transistors formed on the insulating film. Each of the thin-film transistors has a drain electrode and a source electrode. The panel further includes drain lines, each being of a first conductive material and having a first predetermined width, the drain lines are formed on the insulating film and connected to the drain electrodes of the thin-film transistors, respectively. The panel also includes display electrodes, each being of a second conductive material different from the first conductive material. The display electrodes are formed on the insulating film and connected to the source electrodes of the thin-film transistors, respectively. Lastly, the panel incorporates and compensating lines, each being of the second conductive material and having a second predetermined width greater than the first predetermined width. The compensating lines are formed on the drain lines simultaneously with the display electrodes with both peripheral parts of the compensating line for each of the thin-film transistors formed on the insulating film and with a predetermined distance left between the display electrode and the compensating line for each of the thin-film transistors and between the display electrode for one of the thin-film transistors and the compensating line for an adjacent one of the thin-film transistors. The adjacent one of the thin-film transistors is nearer to the display electrode for the thin-film transistor in question rather than the drain line of the thin film transistor in question. The compensating lines compensate for non-uniformity of capacitances between the drain line and the display electrode for each of the thin-film transistors and between the display electrode for the thin-film transistor in question and the drain line for the adjacent one of the thin-film transistors.

According to still another aspect of this invention, there is provided an active matrix liquid crystal display device comprising a liquid crystal panel comprising: an insulating film; a plurality of thin-film transistors formed on the insulating film, each of the thin-film transistors having a drain electrode and a source electrode; drain lines, each being of a first conductive material, the drain lines being formed on the insulating film and connected to the drain electrodes of the thin-film transistors, respectively; first compensating lines, each being of the first conductive material, the first compensating lines being formed on the insulating film simultaneously with the drain lines with a predetermined distance left between the drain line and the first compensating line for each of the thin-film transistors; second compensating lines, each being of the first conductive material, the second compensating lines being formed on the insulating film simultaneously with the drain lines and the first compensating lines with the second compensating line for each of the thin-film transistors located farther from the drain line for each of the thin-film transistors than the first compensating line for each of the thin-film transistors and with the predetermined distance left between the second compensating line for one of the thin-film transistors and the drain line for an adjacent one of the thin-film transistors, the adjacent one of the thin-film transistors being nearer to the second compensating line for the thin-film transistor in question rather than the drain line for the thin-film transistor in question; and display electrodes, each being of a second conductive material which is different from the first conductive material. The display electrodes are formed on the insulating film and connected to the source electrode of the thin-film transistors, respectively. The display electrode for each of the thin-film transistors is formed on the insulating film so that the display electrode for each of the thin-film transistors is positioned between the first and the second compensating lines for each of the thin-film transistors. The display electrode for each of the thin-film transistors is furthermore formed on the first and the second compensating lines for each of the thin-film transistors so that both peripheral parts of the display electrode for each of the thin-film transistors overlaid on the inner peripheral parts of the first and the second compensating lines for each of the thin-film transistors. The first and the second compensating lines compensate for the non-uniformity of capacitances between the drain line and the display electrode for each of the thin film transistors, and between the display electrode for the thin-film transistor in question and the drain line for the adjacent one of the thin-film transistors.

FIG. 1 is a schematic plan view of a conventional active matrix liquid crystal display device;

FIG. 2 is a schematic vertical sectional view taken along a line E--E of FIG. 1;

FIG 3 shows an equivalent circuit of the active matrix liquid crystal display device illustrated in FIG. 1;

FIG. 4 is a schematic plan of an active matrix liquid crystal display device according to a first embodiment of this invention;

FIG. 5 is a schematic vertical sectional view taken along a line A--A of FIG. 4;

FIG. 6 is a vertical sectional taken along a line B--B;

FIG. 7 is a schematic plan view of an active matrix liquid crystal display device according to a second embodiment of this invention;

FIG. 8 is a schematic plan view of an active matrix liquid crystal display device according to a third embodiment of this invention; and

FIG. 9 is a schematic vertical sectional view taken along a line D--D of FIG. 8.

Referring to the FIGS. 1 to 3, a conventional liquid crystal display device will be described for a better understanding of this invention. The liquid crystal display device is equivalent to the conventional display device described in the preamble of the instant specification. The liquid crystal display device comprises a liquid crystal panel comprising a matrix of thin-film transistors. The matrix is arranged on a glass substrate 11. Each of the thin-film transistors has a gate electrode 12, a source electrode 17s, and a drain electrode 17d. The gate electrodes 12 of the thin-film transistors are formed on the glass substrate 11. Gate lines or buses 13 are also formed on the glass substrate 11 so as to be connected to the gate electrodes 12.

A gate insulating film 14 is formed on the gate electrodes 12, the gate lines 13, and a remaining surface of the glass substrate 11. Display electrodes 19 are formed on the gate insulating film 14 so as to be connected to the source electrodes 17s of the thin-film transistors, respectively. The display electrodes 19 are connected to the ground. Each of the display electrodes 19 is made of a transparent conductive film of, for example, indium tin oxide and serves as a pixel or dot. Drain lines or buses 18 are formed on the gate insulating film 14 so as to be connected to the drain electrodes 17d of the thin-film transistors, respectively. Each of the drain lines 18 is made of a metal of, for example, aluminum or chrome.

In the display device, the thin-film transistors selectively operate by supplying a drive signal to the desired drain lines 18. As a result, a predetermined voltage is applied to the display electrode 19 to display the pixel. In this event, the drain line 18 is supplied with an alternating or inverting voltage signal having a frequency which is equal to a scanning frequency of display. The scanning frequency is typically 40 kHz for VGA display. As shown in the art, a dot-invert driving method is effective in driving the drain lines 18 so that the display device carries out the display with flicker reduced. In the dot-invert driving method, positive and negative polarity voltages are supplied to a particular drain line of the drain lines 18 and an adjacent drain line of the drain lines 18, respectively, at a time instant. The adjacent drain line is adjacent to the particular drain line. At a subsequent instant in time, the negative and the positive polarity voltages are supplied to the particular and the adjacent drain lines 18, respectively.

In the display device, the display electrodes 19 and the drain lines 18 are formed at different patterning steps in the manner described in the preamble of the instant specification. This is because the display electrodes 19 are different in material from the drain lines 18. As a consequence, positioning errors unavoidably occur between the drain lines 18 and the display electrodes 19. In other words, a difference occurs between distances L1 and L2 (FIG. 1), where L1 represents a distance between the drain line 18 and the display electrode 19 for each of the thin-film transistors, L2 representing a distance between the display electrode 19 for the thin-film transistor in question and the drain line 18 for an adjacent one of the thin-film transistors that is adjacent to the display electrode 18 for the thin-film transistor in question. This results in non-uniformity of capacitances defined by the distances L1 and L2. As known in the art, the non-uniformity of the capacitances results in the degradation of in display quality of the display device when the display device is driven using the dot-invert driving method.

Turning to FIGS. 4 to 6, the description will proceed to an active matrix liquid crystal display device according to a first embodiment of this invention. The display device comprises similar parts designated by like reference numerals. The active matrix liquid crystal display device comprises a liquid crystal panel 40 (FIG. 6) comprising the glass substrate 11. A gate layer 12', the gate electrodes 12, and the gate lines 13 are formed on the glass substrate 11. The gate insulating film 14 is formed on the gate layer 12', the gate electrodes 12, the gate lines 13, and a remaining surface of the glass substrate 11. An amorphous silicon layer 15 is formed on a part of the gate insulating film 14 that is positioned above the gate layer 12'. A source layer 16s and a drain layer 16d are formed on the amorphous silicon layer 15. The source and the drain electrodes 17s and 17d of, for example, chrome are formed on the source and the drain layers 16s and 16d respectively. Each of the source and the drain electrodes 17s and 17d has a thickness of, for example, 140 nm.

The drain lines 18 are formed on the gate insulating film 14. Each of the drain lines 18 is of a first conductive material of, for example, chrome or aluminum and has a first predetermined width.

The display electrodes 19 are formed on the gate insulating film 14. Each of the display electrodes 19 is a transparent conductive film of a second conductive material which is different from the first conductive material. The second conductive material is, for example, indium tin oxide.

Each of compensating lines 19a (FIGS. 4 and 6) is of the second conductive material and has a second predetermined width which is wider than the first predetermined width. The compensating lines 19a are formed on the drain lines 18 simultaneously with the display electrodes 19 with both peripheral parts of the compensating line 19a for each of the thin-film transistors formed on the gate insulating film 14. A predetermined distance LO is defined between the display electrode 19 and the compensating 19a for each of the thin-film transistors, and between the display electrode 19 for one of the thin-film transistors and the compensating line 19a for an adjacent one of the thin-film transistors. The adjacent one of the thin-film transistors is nearer to the display electrode 19 for the thin-film transistor under consideration rather than the drain line 18 for the thin-film transistor under consideration. Each of the peripheral parts of the compensating line 19a is formed on the gate insulating film 14 by, for example, 2 .mu.m as shown in FIG. 6.

The compensating lines 19a compensate for non-uniformity of capacitances between the drain line 18 and the display electrode 19 for each of the thin-film transistors and between the display electrode 19 for one of the thin-film transistors and the drain line 18 for the adjacent one of the thin-film transistors.

In FIG. 6, an insulating film 30 is selectively formed on the compensating films 19a and the drain lines 18. The liquid crystal panel comprises another glass substrate 20 having a lower surface on which a transparent opposite electrode 21 is formed. A liquid crystal 22 is filled between the display electrodes 19 and the transparent opposite electrode 21 and between the insulating film 30 and the transparent opposite electrode 21.

Turning to FIG. 7, the description will proceed to an active matrix liquid crystal display device according to a second embodiment of this invention. The display device is similar to the display device of FIG. 4 except that the compensating lines 19a are formed on entire surfaces of the drain lines 18. The compensating lines 19a are formed on restricted surfaces of the drain lines 18 of the display device of FIG. 4. The restricted surfaces of the drain lines 18 correspond to the display electrodes 19 in the display device of FIG. 4.

Turning to FIGS. 8 and 9, a description will be made as regards an active matrix liquid crystal display device according to a third embodiment of this invention. The display device comprises similar parts designated by like reference numerals.

The drain lines 18 are formed on the gate insulating film 14 and connected to the drain electrodes 17d of the thin-film transistors, respectively. Each of the drain lines 18 is of the first conductive material.

Each of first compensating lines 18a is of the first conductive material. The first compensating lines 18a are formed on the gate insulating film 14 simultaneously with the drain lines 18 with a predetermined distance LO left between the drain line 18 and the first compensating line 18a for each of the thin-film transistors.

Each of second compensating lines 18a' is made of the first conductive material. The second compensating lines 18a' are formed on the gate insulating film 14 simultaneously with the drain lines 18 and the first compensating line 18a with the second compensating line 18a' for each of the thin-film transistors located farther from the drain line 18 for each of the thin-film transistors than the first compensating line 18a for each of the thin-film transistors. The predetermined distance LO is defined between the second compensating line 18a' for one of the thin-film transistors and the drain line 18 for an adjacent one of the thin-film transistors. The adjacent one of the thin-film transistors is nearer to the second compensating line 18a' for the thin-film transistor in question rather than the drain line 18 for the thin-film transistor in question.

Each of the display electrodes 19 is made of the second conductive material. The display electrodes 19 are formed on the gate insulating film 14 so that the display electrode 19 for each of the thin-film transistors is positioned between the first and the second compensating lines 18a and 18a'. The display electrode 19 for each of the thin-film transistors are is furthermore formed on the first and the second compensating lines 18a and 18a' for each of the thin-film transistors so that both peripheral parts of the display electrode 19 for each of the thin-film transistors are overlaid on inner peripheral parts of the first and the second compensating lines 18a and 18a' for each of the thin-film transistors.

The first and the second compensating lines 18a and 18a' compensate for non-uniformity of capacitances between the drain line 18 and the display electrode 19 for each of the thin-film transistors and between the display electrode 19 for one of the thin-film transistors and the drain line 18 for the adjacent one of the thin-film transistors.