Elevated Source/Drain Junction Metal Oxide Semiconductor Field-Effect Transistor Using Blanket Silicon Deposition

The present invention relates to the field of microelectronics and integrated circuit technology. More specifically, the present invention relates to the fabrication of insulated-gate field-effect transistor (IGFET) devices with elevated (raised) source/drain junctions.

Elevated source/drain junction metal oxide semiconductor field effect transistors (MOSFETs) have been proposed to eliminate the short channel and drain-induced barrier lowering (DIBL) effects of scaled submicron transistors. Fabrication of the elevated source/drain junction structure using conventional prior art methods requires the use of selective epitaxial semiconductor growth or selective silicon growth (SSG). For example, see Rodder, et al., U.S. Pat. No. 5,198,378, issued Mar. 30, 1993 and assigned to the assignee of this application. The elevated source/drain Junction structure allows formation of source/drain junctions with very shallow electrical junction depth from the surface of the MOSFET channel, along with low sheet resistance, self-aligned silicide layers on the surfaces of the elevated source/drain junctions. Device structures with elevated source/drain junctions allow formation of relatively thick, self-aligned silicide layers without the problem of excessive junction leakage.

The elevated source/drain junction structures are expected to be useful for transistors having line width or channel length dimensions (i.e., transistors having a gate length from source to drain) of 0.25.mu. or less. However, successful implementation of elevated source/drain junction structures requires reliable selective epitaxial silicon growth or selective polycrystalline or amorphous silicon growth processes and related fabrication equipment. However, these processes and related equipment have many problems related to process performance, deposition selectivity controls, facet formation, and process contamination sensitivity problems. Also, most selective silicon growth (SSG) processes are optimally performed at temperatures greater than 700.degree. C., which may cause transistor reliability degradations due to presence of hydrogen in the silicon deposition process medium. Moreover, higher deposition temperatures (T.gtoreq.850.degree. C.) typically used for the SEG process can result in redistribution of the dopant profiles in the IGFET device structure such as the channel dopant profile and the source/drain lightly doped drain (LDD). These problems indicate that there is a need for a fabrication method for forming elevated source/drain junction structures without the use of selective epitaxial semiconductor growth or selective semiconductor growth processes.

The described embodiments of the present invention provide a method for fabricating elevated source/drain junction, metal oxide semiconductor field-effect transistors. The process does not require the use of selective semiconductor growth processes. In one embodiment, a MOSFET gate stack is formed having a gate dielectric layer beneath a polycrystalline silicon gate layer and a disposable layer, such as silicon nitride, formed on top of the polycrystalline silicon gate. A conformal layer of, for example, silicon dioxide is formed overall (using a conformal low-pressure chemical vapor deposition or LPCVD process) and anisotropically etched to form sidewall spacers on the sides of the polysilicon gate, and disposable layer stack. The disposable nitride layer is then removed and a layer of polycrystalline silicon or amorphous silicon is deposited overall. The polysilicon deposition process can be performed in a chemical-vapor (CVD) equipment for later deposition of other materials. A layer of silicon nitride is then deposited on the surface of the polycrystalline silicon layer probably using non-conformal (CVD) techniques. The silicon nitride layer is etched anisotropically using a selective plasma etch process to leave sidewall silicon nitride layers on the portion of the polycrystalline or amorphous silicon layer over the sidewalls of the gate structure. The exposed portion of the polycrystalline silicon layer is then thermally oxidized. A selective isotropic silicon nitride etch is then used to remove the sidewall silicon nitride layers, followed by a selective silicon etch to selectively remove the portion of the polycrystalline silicon or amorphous silicon layer exposed by the removal of the silicon nitride sidewalls. This leaves elevated source and drain junctions extending from the sidewalls of the gate on to the isolation structures surrounding the field-effect transistor gate area.

FIGS. 1 through 8 are side view schematic diagrams showing the processes of one embodiment of the present invention.

FIGS. 1 through 8 are side view schematic diagrams showing one embodiment of the present invention. The detailed description presented here is for an n-channel IGFET or NMOS transistor device. However, the method of this invention is also applicable to fabrication of p-channel IGFET or PMOS transistor devices.

The described embodiment begins with FIG. 1, at this stage the doped wells (e.g. p and n wells) have already been formed, Silicon dioxide layer 12 is formed on the surface of silicon substrate 10 using a thermal oxidation process and silicon nitride layer 14 is formed on the surface of silicon dioxide layer 12 using a chemical-vapor deposition (CVD) technique. Silicon nitride layer 14 and silicon dioxide layer 12 are than patterned using well-known microlithography and plasma etch processes to form the LOCOS mask. An alternative structure may be used which includes a thin polysilicon layer (not shown) between the silicon nitride 14 and silicon dioxide 12 layers. This alternative structure (called poly buffered LOCOS or PBL) is patterned similar to the one shown in FIG. 1. A channel stop implant is then performed as indicated by the arrows in FIG. 1. The structure of FIG. 1 is subjected to thermal oxidation in a steam or oxygen environment to form field oxide regions 18 and channel stop regions 16 as shown in FIG. 2. After the field oxidation process the LOCOS mask layers 12 and 14 are removed. A silicon dioxide gate dielectric layer 20 is then formed using thermal oxidation techniques. The gate dielectric layer 20 may also be formed using nitride-oxide or oxynitirde materials. Polycrystalline silicon layer 22 (or silicon/geranium alloy layer) is then formed on the surface of silicon dioxide layer 20 using a chemical vapor deposition (CVD) process to a thickness of approximately 2,000 .ANG. to 3,000 .ANG.. Silicon nitride layer 24 is then formed on the surface of polycrystalline silicon gate electrode layer 22 using chemical-vapor deposition techniques to a thickness of approximately 1,000 .ANG. to 1,500 .ANG.. The 2-layer structure of polycrystalline silicon gate electrode layer 22 and silicon nitride layer 24 is patterned and etched using well-known microlithography and anisotropic plasma etching methods to form the gate stack shown in FIG. 3.

A thin blanket layer of silicon dioxide, or another dielectric material (not shown) is then formed using a conformal chemical-vapor deposition (CVD) process. The structure of FIG. 3 is then subjected to an implantation of phosphorous or arsenic ions having a dose of 2 to 8.times.10.sup.13 /cm.sup.2 at 30 to 50 KeV, to form shallow lightly doped drain or LDD junction regions 28 as shown in FIG. 3. Fabrication of the LDD junction regions is optional for the purpose of this invention. Then, another blanket layer of silicon dioxide or another suitable dielectric material (not shown) is formed using a conformal chemical-vapor deposition (CVD) process. The silicon dioxide layer (not shown) is then subjected to an anisotropic plasma etching process to form the sidewall dielectric spacers 26. Silicon nitride layer 24 is then removed using a selective plasma etch or a hot phosphoric acid (H.sub.3 PO.sub.4) wet strip and a layer of polycrystalline silicon 30 is deposited using a low-pressure chemical-vapor deposition (LPCVD) process or a physical-vapor deposition (PVD) process such as evaporation or sputtering as shown in FIG. 4. The silicon layer 30 may be deposited either way a conformal or a partially conformal deposition process. The preference is to use a partially conformal PVD or CVD process which deposits a thinner silicon layer on the dielectric spacer 26 then on the flat surfaces (such as on the source/drain junction 28 and field insulating 18 regions). The PVD processes such as evaporation and sputtering usually deposit material layers with partial conformality (typically 20% to 70%). The CVD process parameters may also be adjusted in order to achieve reduced deposition conformalities (e.g. 30% to 85%). A thin (200 to 1000 .ANG.) conformal silicon nitride layer is then formed using low-pressure chemical-vapor deposition or plasma enhanced chemical-vapor deposition (PECVD). This layer is then subjected to anisotropic ion etching in a suitable plasma chemistry such as CHF.sub.3 /CF.sub.4 /O.sub.2 /Ar plasma to form sidewall nitride spacers 32 as shown in FIG. 5. The resulting structure is then subjected to thermal oxidation in an oxygen or steam ambient at a temperature of approximately 800.degree. to 1000.degree. C. for approximately 1 to 30 minutes to form silicon dioxide layer 34 having a thickness of approximately 100 to 500 .ANG. on the exposed portions of polycrystalline silicon layer 30. The sidewall silicon nitride spacers 32 serve as an oxidation mask and prevent silicon dioxide growth on the sidewall portion of silicon layer 30.

Using well-known photolithographic techniques, the portion of silicon dioxide layers 34 and polycrystalline silicon layer 30 which are not necessary to provide conductors are patterned and subsequently etched on the areas above field oxide regions 18 as shown in FIG. 6. This process step results in formation of the local interconnect region over the field oxide regions which are subsequently covered with a self-aligned silicide layer. Silicon nitride sidewall spacers 32 are then removed using a selective isotropic etch. This etch process can be accomplished using plasma or a wet strip chemistry. The resulting structure is then subjected a selective silicon etch using a plasma etch process (e.g., CL.sub.2 plasma). The portions of polycrystalline silicon layer 30 which are exposed by the removal of sidewall spacer nitride layers 32 are then removed down to sidewall oxide spacer layers 26. This clearly defines the portion of polycrystalline silicon layer 30 overlaying the device gate and the portions of polycrystalline silicon layer 30 which overlay the source/drain junction areas and extend on to field oxide regions 18 (the starting silicon for local interconnects). The structure of FIG. 6 is then subjected to an ion implantation of arsenic and/or phosphorus ions having a concentration of 1 to 3.times.10.sup.15 /cm.sup.2 and an implant energy of 30 to 100 KeV. When driven in, using a furnace anneal for rapid thermal anneal step, this forms heavily doped shallow source/drain junctions regions 30 as shown in FIG. 7. After removal of silicon dioxide layer 34, a layer of titanium (or another suitable refractory metal such as cobalt) is then deposited using sputtering to form titanium layer 36 overall. The structure of FIG. 7 is then subjected to annealing at approximately 585.degree. C. for about 25 minutes (or at 850 degrees to 700 degrees for 30-180 sec using rapid thermal processing) in a nitrogen ambient. The unreacted portions of the titanium layer 36 and the portion of titanium layer which has reacted with the nitrogen ambient to form titanium nitride are then etched away using a selective etch process leaving titanium silicide cap 38 and silicide source/drain junction extensions 40 and 42 (including silicide local interconnects) as shown in FIG. 8.

Thus, a MOS field-effect transistor (MOSFET) 44 as shown in FIG. 8 is formed having elevated source/drain junctions, including titanium silicide elevated source 40, titanium silicide elevated drain 42 and gate 22 capped by titanium silicide layer 38. This structure was formed using no selective silicon growth or selective epitaxial growth techniques. Although specific embodiments of the present invention are disclosed herein, this is not to be construed as defining the scope of the invention. The scope of the invention is defined only by the claims appended hereto.