US 5,495,585 AGrant
Programmable Timing Logic System for Dual Bus Interface
Issue Date:1996-02-27
•13 Claims
•20 Drawing Sheets
Abstract
A programmable timing logic system for enabling access to a first or second bus, of dual system busses, by a central processor and/or a protocol-timing translation logic unit wherein messages may be received from one bus while command/control data is being transmitted to the other bus. Incomplete command cycles are retried a specific number "n" of times, each for a preset predetermined time period of "p" microseconds.
Metadata
Assignee
- Unisys Corporation
Inventors
- Wayne C. Datwyler
- Paul B. Ricci
Application Information
Application Number:US 9617442
Filing Date:1992-10-16
Priority Date:1992-10-16
Art Unit:235
Classifications
IPC:
G06F 1336G06F 1340
Field of Search:
395325;200;725;275;550
Patent Drawings (20 sheets)
Description
FIELD OF THE INVENTION
This disclosure relates to electronic interface control mechanisms which provide intercommunication between a processor and dual system busses.
CROSS REFERENCES TO RELATED INVENTIONS
This application is related to a co-pending application entitled "Intermodule Message Transfer System" which was filed Feb. 14, 1992 as U.S. Ser. No. 07/837,174 and which is included herein by reference. This message transfer system provided communication between a single word protocol system and a multiple word protocol system each operating at different clock speeds. Also included by reference is a copending application entitled "Dual Bus Interface Transfer System For Central Processing Module" filed Oct. 16, 1992 as U.S. Ser. No. 07/963,304.
BACKGROUND OF THE INVENTION
Many problems arise when it is necessary to interconnect a processing unit with one or more system busses which permit intercommunication to other memory modules, other processors and to other input/output systems. It is always necessary that there be taken into account means for allowing flexibility within the system, such as allowing partitioning, and also providing for system speed and also for proper data transfer integrity and correction, in addition to redundancy which might be required should one area fail.
Prior art systems such as U.S. Pat. No. 4,622,630 entitled "Data Processing System Having Unique Bus Control Protocol" involve a single common bus which is used for communication of address and data information among various system components but which single bus is time multiplexed in order to provide periods for address transfer and periods for data information transfer.
U.S. Pat. No. 4,982,321 entitled "Dual Bus System" provides an architecture where two system busses are used but for entirely different purposes. Thus one bus is operable for memory operations while another bus is operable for input/output operations but there is no redundancy or means by which each of the busses can be used for each of the other functions. Thus this system could not operate on a single bus since it at all times requires two busses for operations.
U.S. Pat. No. 4,535,448 entitled "Dual Bus Communication System" involves a dual set of busses used to provide coupling between data services and voice services of a particular AT&T communication system designated the CS300. One bus functions on a time division basis for communication between port circuits while the other bus functions as a packet-switch data processing bus for interfacing system peripherals with port circuitry. Again here the busses in this system are dissimilar and are not interchangeable to provide any redundancy.
U.S. Pat. No. 4,933,846 entitled "Network Communications Adapter With Dual Interleaved Memory Banks Servicing Multiple Processors" involves dissimilar busses such that one bus functions for transferring addresses and the other functions for the transfer of data. Then further this system operates for multiple computers hooked together in a network and does not function as a single computer hooked into dual common redundant busses.
The architecture of the presently disclosed system involves a single computer system operating independently but providing dual redundant system busses which have bus interface units which permit the processor and another element designated as the translation logic unit to communicate to either one of the two or dual system busses so that data communication and transfers may occur between the processor and other auxiliary resources such as a memory module, an input/output module, or another processor module if so desired. Each one of the two system busses involved is a duplicate of the other so that the system can operate on any one of the busses should the other one fail. Another feature of the present system is the flexibility of expansion so that a second central processing module system can be integrated for communication on the dual busses and permit partitioning into concurrently operating systems.
An ongoing problem in the operative functioning of these versatile computer and digital module intercooperating systems involves the time allocation and usage between various command cycles, control data cycles, message and data transfer cycles such that no single cycle will hang onto or monopolize the system busses causing access blockage and/or unnecessary delay, to the detriment of execution of other operational cycles.
The presently described programmable timing logic system serves to equitably allocate system bus time access to various resources which continually use the system busses, thus to minimize delays and access blockage of data transfer cycles.
SUMMARY OF THE INVENTION
The programmable timing logic system services two communication channels operating between two system busses and two resource modules (a central processor and a protocol translation unit).
Commands, data and messages to/from the resource modules are given a predetermined access request period for use of either one of the two system busses. Each such operational cycle is allocated up to 16 retries for bus access before the particular data transfer cycle is terminated and access request is given over to another data transfer cycle. Thus the incompletion or failure of one transfer cycle will not unduly delay the use of a system bus for another pending transfer cycle. The timing logic system will also signal the completion of a data transfer cycle and then release the just-used system bus to another requesting data transfer cycle in addition to logging any possible errors.
The present system provides the architecture for a bus interface unit which cooperates with two identical system busses such that the system can operate on either bus alone or on both busses at the same time. A specialized protocol is implemented which allows the processor and its associated transfer box (translation logic unit) to send or receive information data to and from either or both of the busses. The transfer box translates the dual bus protocol to the processor protocol and vice versa for messages going between the processor and the dual system busses.
A particular feature of the bus interface unit is that it permits one system bus to do Reads and Writes to memory while allowing another system bus to carry messages from other module resources to be received by the processor. Additionally, since each of the two system busses are identical to each other, the failure of one bus would not shut down the system since the other bus would be fully capable of carrying out all the required operations since the processor unit can access both system busses at the same time or alternatively access any one of the system busses as required.
The system performance can be enhanced since during the time that Reads and Writes are being communicated to memory on one bus, the messages from other of the resource modules in the system can be received simultaneously on the other bus for action by the processor unit. Additionally because of the capability of two redundant system busses in the architecture, it is possible to partition the system into two independent operating machines operating under separate central processing modules (CPM's).
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram of the dual bus interface unit showing the two communication channels connecting the system busses and processor;
FIG. 1A is a block diagram showing the disclosed bus interface unit and its relationship to the mainframe processor and the transfer box unit;
FIG. 1B is a drawing showing the function of the bus interface unit in communicating to the dual system busses;
FIG. 1C is a schematic drawing showing the data flow being returned from memory and transferred from the system busses to the bus interface unit for conveyance to the processor;
FIG. 2 is an overall system diagram showing the location of the bus interface units in the central processing module the two system busses connected to an input/output module which communicates to a task control unit, (TCU) and an external processor memory interface unit (PMIU);
FIG. 3A is a drawing showing the transfer of message data from the transfer box through the bus interface unit to the system busses while FIG. 3B shows the flow of data from the system busses through the bus interface unit into the transfer box;
FIG. 4 is schematic block drawing showing the main circuitry units involved in the central processing module (CPM), in the translation logic unit and in the bus interface unit logic;
FIG. 5A is a block drawing of the bus interface unit transmission programmable array logic which is indicated in more detail through use of FIGS. 5B and 5C which indicates the functions of the bus interface unit-transmit state machine;
FIG. 6A is a block diagram showing the bus interface unit receive-programmable array logic whereby message data is moved from the system bus to the bus interface unit;
FIGS. 6B and 6C are drawings of the function of the state machine operation for the bus interface unit receive logic;
FIG. 7A is a block diagram of the return-programmable array logic for the bus interface unit; FIGS. 7B and 7C show diagrams illustrating the functions of the return state machine operations;
FIG. 8A is a block diagram to illustrate the functioning of the programmable timing logic of the bus interface unit; FIGS. 8B and 8C are drawings showing the functions of the timeout state machine.
GENERAL OVERVIEW
A general view of the overall system involved is seen in FIGS. 1A and 2 wherein a pair of system busses 12.sub.a and 12.sub.b are each interconnected to a number of resource modules in the system. These resource modules include a central processing module 8 in which there resides a bus interface unit 10. This bus interface unit actually is a dual unit of which one operates with a system bus A, 12.sub.a and the other unit cooperates with the system bus B, 12.sub.b. The additional resources connected to both of the system busses include a memory control module MCM 48 (memory unit) and an input/output module 68 (IOM) which provides communication with various peripherals attached to the system in addition to a task control unit 88 (TCU) which controls the allocation of system tasks, and an external message interface unit 98 (PMIU) which connects to a system having non-compatible protocol operations.
Within the central processing module 8, this disclosure is particularly involved with the function and operation of the bus interface unit 10 having two channels 10.sub.a, 10.sub.b operating in a dual capacity such that the system bus A, 12.sub.a will have its own bus interface channel 10.sub.a (FIG. 1) and also the other system bus B, 12.sub.b will have its own dedicated bus interface channel 10.sub.b (FIG. 1).
FIG. 1 is a generalized overall view of the dual bus interface unit 10 indicating its major components for integrating communication between dual systems busses and the Translation Logic 20 and Processor 28. The M bus 28m connects the bus exchange 15 to the mainframe processor 28 while the T bus 20.sub.t connects the translation logic unit 20 to the bus exchange. Then Channel A, 10.sub.a and Channel B, 10.sub.b respectively use the A bus 15.sub.a and B bus 15.sub.b with a series of state machines 10.sub.ta, 10.sub.tb ; 10.sub.ra, 10.sub.rb ; and 10.sub.rta, 10.sub.rtb.
The bus interface unit 10 is further shown in FIG. 1A and functions to permit the processor 28 and the translation logic 20 to communicate with the dual bus system, that is to say, system busses 12.sub.a and 12.sub.b.
The processor 28 is capable of executing Reads or Writes to the system memory 48 of FIG. 1A. The mainframe processor 28 can also read the time of day from the input/output module 68 which houses the system clock. Thus there can be enabled, through the bus interface unit 10, a flow of data from either one of the system busses A or B, to and from the mainframe processor 28 and/or the translation logic unit 20.
DESCRIPTION OF PREFERRED EMBODIMENT
The flow of communications and data provided by the bus interface unit 10 will be seen in FIG. 1B which shows data sent to the system busses 12.sub.a, 12.sub.b, and in FIG. 1C which shows data returned from the system bus to the bus interface unit 10 (BIU) for transfer to the mainframe processor 28. As seen in FIG. 1B, there is indicated the transfer of data and commands from the processor 28 through the memory bus exchange 15 and thence to either the A bus output register 16.sub.a0 or to the B bus output register 16.sub.b0. These A and B bus registers respectively connect to the system A bus 12.sub.a and the system B 12.sub.b.
Referring to FIG. 1A for initiating a "Read" from the memory unit 48, the processor interface logic in 28 sends a command to the bus interface logic unit 10 (BIU) along with a BIU 10 request signal. The command and the address are loaded into the output registers 16.sub.a0 and 16.sub.b0 for conveyance to both system busses. The Bus Interface Unit 10 will then make a request to the system bus arbitrators (in the Central Processing Module 8 of FIGS. 2, 4) for use of a system bus.
When a system bus (12a or 12b) has been granted access, the bus interface unit 10 executes all the necessary system bus protocols unique to the system bus 12 in order to send the command, the address (and data if there is required an "overwrite" to the system memory 48). If a "Read" cycle is commanded, then the requested data is returned from the memory 48, checked for parity, and the data is then sent to the central processor 28, FIG. 1A.
Likewise referring to FIG. 1C, it can be seen that data taken from the memory unit 48 can be transferred on either bus, but, in this case specifically on system bus A, 12.sub.a, over to the A bus input register 18.sub.ai and thence on the A bus 15a to internal register 16.sub.ai from which it is conveyed to the memory bus exchange 15 for subsequent transfer to the processor 28.
Referring to FIGS. 3A and 3B there is seen the use of the translation logic unit 20. The translation logic 20 serves the function of providing an interface for handling the mainframe processor protocol which uses one 52-bit word and transfers this into 4 word messages for compatibility with an external digital system 98 using a different clock rate and protocol; thus the translation logic 20 of FIGS. 3A and 3B "Writes to" and also receives four word messages from the system busses 12.sub.a and 12.sub.b. The data flow is seen in FIG. 3A as the transfer of four words from the translation logic 20 to the memory bus exchange 15 and thence to the A bus and B bus output registers (16.sub.a0, 16.sub.b0) for conveyance to the system A bus 12.sub.a and the system B bus 126. This illustrates the output of message data from the transfer bus logic 20 to the system busses 12.sub.a, 12.sub.b. Thus the command, and the four data words, can then be transferred, for example, to an input/output module 68, and to the TCU 88 or PMIU 98.
When the translation logic 20 wants to send a message to the input/output module 68, a request is made to the bus interface unit BIU 10 (FIG. 1A). Once a grant is made by the bus interface unit, BIU 10, the message command word will be loaded into both of the BIU output registers 16.sub.a0, 16.sub.b0 for both system busses. The BIU 10 (Bus Interface Unit) will then make a request to the system bus arbitrators (in the CPM 8) for use of a system bus such as 12.sub.a or 12.sub.b. When a system bus has been granted, the BIU 10 will execute all necessary system bus protocols which are required by the bus to send the command and also the four data words to the input/output module IOM 68.
The BIU 10 (Bus Interface Unit) continuously monitors the system busses for messages which are addressed to the central processing module 8 (CPM). The system bus is continually loading data into the input registers 18.sub.ai, 18.sub.bi of the BIU 10.
A determination is made of data on the system bus if what was loaded was a "message" and if this message was addressed to processor 28 IN the central processing module, CPM 8. If such is the case, then several actions can be forthcoming.
If the BIU 10 is currently "not ready" to accept a message (such as waiting for Read data to be returned on the other system bus), then certain signals such as a "not ready" signal (A-PENRDY-B or B-PENRDY-B) will be asserted into the message. PENRDY denotes "processing element" not ready.
The message transfer will pause until the "not ready" signal goes away and then the BIU 10 will then load it into the translation box logic unit 20.
The BIU 10 may also issue a signal designated A-RETRY-B or B-RETRY-B to the message, if it is currently unable to process the message. Finally, when it can accept the message, and check the parity and send the four data words to the translation logic 20, the BIU 10 will do so. The BIU 10 will execute all necessary system bus protocols unique to the system bus in order to facilitate the message transfer.
FIG. 4 is a generalized block diagram showing the relationship of logic units the central processing module 8 which holds, the translator logic 20 and the bus interface unit 10. In addition, FIG. 1, also shows this relationship indicating how the two channels A and B (15.sub.a, 15.sub.b) are organized.
The central processing module 8 contains the mainframe processor 28 (IMP) and a number of other generalized functional blocks shown in FIG. 4. Connected to the processor logic of the CPM 8 is the translator logic 20. As shown in FIG. 4, this involves the translator box 20.sub.x, the translator box controller 20.sub.c, and the translator box memory RAM 20.sub.r.
The logic unit designated as the bus interface unit logic BIU 10 is shown in a generalized block form with blocks indicating the Mix unit 10.sub.m, the Error Logging unit 10.sub.u, the Parity Check Unit 10.sub.pc, and the Timeout Unit 10.sub.tm. Additionally, there are shown the return unit state machine RETURNA designated 10.sub.rta and also the RETURN B unit state machine, 10.sub.rtb. Additionally are shown the bus interface transmit programmable array logic such as 10.sub.ta and 10.sub.tb and the bus interface receive programmable array logic designated 10.sub.ra and 10.sub.rb. Each system bus A and system bus B will connect to a decoder 10.sub.d (10.sub.da and 10.sub.db) which provides decoding functions for the system busses 12.sub.a and 12.sub.b.
The Mix Unit, 10m, of FIG. 4 combines control signals from both system busses into one signal for the processor control logic unit in CPM 8. It also functions to stop incoming messages to the CPM 8 from a system bus, if the CPM 8 is not ready to accept the message.
The Decoder 10.sub.da and 10.sub.da of FIG. 4 functions to monitor the system busses, 12.sub.a and 12.sub.b to notify the BIU 10 that a bus message is designated for the host CPM 8. It also functions to see if a "Write Command" on the system bus should be invalidated in cache memory as being no longer valid data.
The mainframe processor control logic in the CPM 8, FIG. 4, will receive completion status signals from a system bus when a given command cycle has been completed.
The multiple bus exchange 15 allows the mainframe processor 28, the translation logic unit 20 and the BIU 10 to exchange data. Thus the processor 28 can read or write the transfer unit 20 or read from or write data to the BIU 10. Control lines determine which modules are sources and which are receiving units.
BUS INTERFACE UNIT-TRANSMIT STATE MACHINE (BIU-XMT 10.sub.ta AND 10.sub.tb)
The bus interface unit logic 10 will be seen to have two programmable array logic state machines, one for each channel for each of the system busses. These are designated as transmit (XMT) state machines which provide the functions seen in FIGS. 5A and 5B.
The BIU-XMT programmable array logic is a state machine which may be implemented by use of a Signetics chip PLUS405 running at 16 megahertz. Its main function is to handle the system bus protocols for carrying out the various system bus operations which are initiated by the processor 28 (IMP) or transfer box logic 20. There is one bus interface unit transmit PAL (BIU-XMT) for each system bus.
FIG. 5A is a block diagram of the bus interface unit transmit programmable array logic unit (BIU-XMT) and the signals which interface with it. It should be noted that the subsequent designation of single names will often involve a small "x" which indicates that the signal exists for both the A and the B busses 12.sub.a and 12.sub.b. For example, x-RETRY-B refers to two signals, that is to say A-RETRY-B and also B-RETRY-B. The use of a small "n" is used to indicate a number so that for instance--MSGn represents MSGn. MSG2, and so on. MSG stands for message number.
FIG. 5A is a drawing illustrating the transmit function of the bus interface unit and its relationship to other modules in the system. FIG. 5A shows how various signals from the processor logic 28, the Error Logging unit 10.sub.u and the translator box logic 20 are sent to the bus interface unit programmable transmit logic 10.sub.ta. The bus transmit programmable array logic 10.sub.ta receives a series of signals from the A Bus 12.sub.a and also outputs a series of signals to the A Bus 12.sub.a as shown in the drawings of FIG. 5A. Also the transmit unit 10.sub.ta provides signals to the A Bus output register 16.sub.a0 and to the A Bus output buffer 16.sub.a0b.
Another series of output lines from the bus interface unit transmit programmable array logic (BIU.sub.-- XMT) 10.sub.ta is fed to the Return A logic 10.sub.rta. The timeout unit 10.sub.tm and the parity check unit 10.sub.pc provide signal lines into the bus interface unit transmit programmable logic 10.sub.ta.
FIG. 5A basically indicates commands and data transfers from the processor 28 (IMP) or from the transfer box 20.sub.x to the system busses 12.sub.a, 12.sub.b. In this manner the transfer box messages can be serviced for transfer to the busses 12.sub.a and 12.sub.b. When the command phase of a bus operation is initiated, a system bus signal will permit commands to be transmitted from the IMP processor 28 or the transfer box 20.sub.x.
Thus the mainframe processor 28 and the translation box logic 20 are capable of sending and receiving messages via a dual system bus architecture which caries message protocols different from the message protocols used by the mainframe processor.
The attached Table I will illustrate how the mainframe processor 28 provides message commands and how each command is encoded when it is sent to the bus interface unit-transmit programmable array logic 10.sub.ta.
The various input and output signals shown in FIG. 5A are defined in the following lists.
INPUTS (FIG. 5A) BIU-XMT PAL
System Bus Retry(x.sub.-- RETRY.sub.-- B)
Source: Sx.sub.-- RETRY.sub.-- B buffered by a Receiver
Dest: BIU-XMT PAL
Polarity: Active Low
Type: Unidirectional
If the BIU-XMT PAL is executing an operation to the system bus and this signal is asserted when there are no active "not ready's", the state machine will abort the operation and if the retry limit has not been met, will retry the operation at a later time.
System Bus Error (x.sub.-- Berr.sub.-- B)
Source: Sx.sub.-- Berr.sub.-- B buffered by a Receiver
Dest: BIU-RCV PAL, BIU LCA
Polarity: Active Low
Type: Unidirectional
This signal indicates that some active receiver on the system bus has detected a parity error.
Memory Module Not Ready (x.sub.-- MMNRDY.sub.-- B)
Source: Sx.sub.-- MMNRDY.sub.-- B buffered by a Receiver
Dest: BIU-RCV PAL, BIU-XMT PAL
Polarity: Active Low
Type: Unidirectional
If the BIU-XMT PAL is executing a system bus operation which reads or writes from memory, this signal will cause the state machine to pause its execution until the signal is no longer active.
Processing Element Not Ready (x.sub.-- PENRDY.sub.-- B)
Source: Sx.sub.-- PENRDY.sub.-- B buffered by a Receiver
Dest: BIU-XMT, TAG Check (LOADORG Control), BIU-RCV
Polarity: Active Low
Type: Unidirectional
If the BIU-XMT PAL is executing a system bus operation which reads from the PMIU or sends out a message, this signal will cause the state machine to pause its execution until the signal is no longer active.
PROCR (IMP) Command (M.sub.-- CMD016, M.sub.-- CMD116)
Source: CMDREQ PAL synchronized in BIU Error Log Unit
Dest: BIU-XMT PAL, TIMEOUT PAL, RETURN PAL
Polarity: Encoded Bus
Type: Unidirectional, Encoded Commands
These two signals contain the bus operation encoding from the IMP interface logic. Table I . indicates values.
System Bus Busy (x.sub.-- BUSBUSY.sub.-- B)
Source: Sx.sub.-- BBSY.sub.-- B buffered by a Receiver
Dest: Arbiter, BIU-XMT
Polarity: Active Low
Type: Unidirectional
This signal indicates that there is an operation which is active on the system bus.
System Bus Grant (Sx.sub.-- BGNTx.sub.-- B)
Source: System Bus Arbiter
Dest: TIMEOUT, BIU-XMT
Polarity: Active Low
Type: Unidirectional
This signal, validated with x.sub.-- BUSBUSY.sub.-- B, indicates that the requesting CPM has been granted the indicated system bus for a bus operation.
Bus Operation Timeout (TIMEOUT.sub.-- B)
Source: TIMEOUT PAL
Dest: BIU-XMT PAL, TBOX, RETURN PAL
Polarity: Active Low
Type: Unidirectional
This signal is used to determine when a bus operation has timed out. This can occur while waiting for a system bus grant after a system bus request, waiting for a not ready signal to go inactive while executing a bus operation, or waiting for data to be returned while executing a read type operation.
TBOX BIU Request (T.sub.-- BREQ.sub.-- B)
Source: TBOX
Dest: BIU-XMT PAL, Error Log, TIMEOUT PAL, TAGCHCK PAL, RETURN PAL
Polarity: Active Low
Type: Unidirectional
This signal becomes active when the TBOX wishes to send a message to a system bus.
Data Parity Error (.sub.-- DATAPE.sub.-- B)
Source: PARCHCK PAL
Dest: BIU-XMT PAL, BIU-RCV PAL, Error Log, DECODER PAL, RETURN PAL
Polarity: Active Low
Type: Unidirectional
This signal is asserted whenever a parity error is detected on one of the system buses.
Test Bit (TS.sub.-- XBDRV.sub.-- B)
Source: Error Log Unit
Dest: BIU-XMT PAL
Polarity: Active Low
Type: Unidirectional
This signal is a test bit used during board debug. It causes the BIU-XMT PAL to assert the signals B.sub.-- DRIVE.sub.-- B and x.sub.-- BBSY.sub.-- B.
Processing Element Acknowledge (x.sub.-- PEACK.sub.-- B)
Source: Sx.sub.-- PEACK.sub.-- B buffered by Receiver.
Dest: BIU-XMT PAL, Error Log
Polarity: Active Low
Type: Unidirectional
This signal is asserted by the PMIU 98 when it has successfully accepted a message from the CPM or is acknowledging that it has received a read time of day, RTOD command.
Memory Module Acknowledge (x.sub.-- MMACK.sub.-- B)
Source: Sx.sub.-- MMACK.sub.-- B buffered by Receiver.
Dest: BIU-XMT PAL, Error Log Unit
Polarity: Active Low
Type: Unidirectional
This signal is asserted by memory to acknowledge that it has received a valid command.
IMP BIU Request (M.sub.-- BREQ16.sub.-- B)
Source: CMDREQ PAL synchronized in Error Log
Dest: BIU-XMT PAL, TIMEOUT PAL, RETURN PAL
Polarity: Active Low
Type: Unidirectional
This signal validates the IMP Command bits.
System Bus Retry (x.sub.-- RETRY.sub.-- B)
Source: Sx.sub.-- RETRY.sub.-- B buffered by Receiver.
Dest: BIU-XMT PAL
Polarity: Active Low
Type: Unidirectional
If the BIU-XMT PAL is executing a system bus operation and this signal is asserted by the receiving module, the operation will be aborted and, if the retry limit has not been exceeded, the operation will be retried at a later time.
System Bus Error (x.sub.-- Berr.sub.-- B)
Source: Sx.sub.-- Berr.sub.-- B buffered by Receiver.
Dest: BIU-XMT PAL, BIU-RCV PAL, Error Log Unit
Polarity: Active Low
Type: Unidirectional
This signal indicates that some active receiver on the system bus has detected a parity error.
OUTPUTS (FIG. 5A)
System Bus Command Valid (x.sub.-- CMDVLD.sub.-- B)
Dest: System Bus Driver
Polarity: Active Low
Type: Unidirectional
Indicates that there is a valid system bus command on the system bus.
System Bus Data Valid (x.sub.-- DATVLD.sub.-- B)
Dest: System Bus Driver
Polarity: Active Low
Type: Unidirectional
Indicates that there is a valid data word on the system bus.
Output Buffer Drive (B.sub.-- DRIVE.sub.-- B)
Dest: Output Buffers through driver
Polarity: Active Low
Type: Unidirectional
Activates the output buffers to the system bus.
XMIT PAL Busy (x.sub.-- BBSY.sub.-- B)
Dest: System Bus through driver, DECODER PAL, Test Register
Polarity: Active Low
Type: Unidirectional
Indicates that the BIU-XMT PAL is driving "bus busy" onto the system bus.
Operation Abort (x.sub.-- ABORT.sub.-- B)
Dest: Error Log Unit, RETURN PAL
Polarity: Active Low
Type: Unidirectional
Indicates that the current operation by the BIU-XMT PAL is being aborted because of a bus error, a retry, or a timeout.
Invalid Address (x.sub.-- INVADR.sub.-- B)
Dest: Error Log Unit, RETURN PAL
Polarity: Active Low
Type: Unidirectional
If this signal is active, the current operation being performed resulted in the destination system bus receiver not acknowledging the operation.
Load Output Register (x.sub.-- LDOREG.sub.-- B)
Dest: Output Register via TAGCHCK PAL
Polarity: Active Low
Type: Unidirectional
Causes the output registers to be loaded with the data on the A or B internal buses (15.sub.a, 15.sub.b).
Data Acknowledge (=.sub.-- DACK.sub.-- B)
Dest: RETURN PAL
Polarity: Active Low
Type: Unidirectional
This signal indicates that the current bus operation has completed successfully.
BIU-XMT States (FIG. 5B): There are twenty operative states associated with this BIU-XMT state machine. It is to be noted that the bus interface unit transmit programmable array logic, 10ta will operate as a state machine. This is indicated in FIG. 5B which shows the various routines which can be provided by the bus interface transmit unit 10.sub.ta. Similarly this set of routines is also provided by the second bus interface transmit programmable array logic 10.sub.tb which performs the same set of automatic functions shown in FIG. 5B.
The following list explains the various circular block acronyms shown in FIG. 5B to indicate the functions that they perform.
BUS INTERFACE UNIT--RECEIVE STATE MACHINE (BIU-RCV)
FIG. 6A shows a drawing of the bus interface unit programmable array logic state machine designated 10ra. The BIU-RCV programmable array logic is a state machine which is implemented, for example, by means of a Signetics PLUS405 type of device running at 16 megahertz. Its chief function is to control and handle messages coming in on one of the system busses (12.sub., 12.sub.b) which is addressed for a particular central processing module CPM.
The bus interface unit-receive state machine 10.sub.ra is the central programmable array logic unit of FIG. 6A which is shown having a set of signal line connections to certain elements of the system. It should be noted that the programmable array logic will assert to the system certain signals such as bus retries, bus errors and not-ready signals as appropriate. In the described system there is one bus interface receive state machine for each of the system busses 12.sub.a and 12.sub.b.
As seen in FIG. 6A the bus interface unit-receive state machine will interchange signals with the system bus 12.sub.a and also with the A Bus internal register 16.sub.ai in addition to the cache unit 40.sub.c and the translation box logic unit 20.sub.x, FIG. 3A. Other input lines to the bus interface unit-receive state machine are seen to be supplied by the Mix unit 10.sub.m, the parity check unit 10.sub.pc, the timeout unit 10.sub.tm, the return unit 10.sub.rta and the decoder 10.sub.d.
The BIU-RCV state machine is a dual bus receiving and routing system for receiving non-compatible protocol messages for storage in TBOX 20.sub.x and translation for message protocol compatibility to the Central Processing Module CPM 8. It controls and handles messages coming in on system busses 12.sub.a, 12.sub.b which are addressed to a particular CPM processor (if more than one CPM is used) or addressed to a translation box logic unit 20 in the CPM 8, FIG. 4.
The BIU-RCV will also assert the signal Sx .sub.-- BERR.sub.-- B if a parity error is detected; or it can assert Sx.sub.-- RETRY.sub.-- B if a message should be retried at a later time; or it can assert Sx.sub.-- NRDY.sub.-- B if a message needs to be held a few clocks before it can be accepted.
As seen in FIG. 6A, there are a series of inputs to the receive programmable array logic 10.sub.ra.
INPUTS TO BIU-RCV (10.sub.ra FIG. 6A)
Processing Element Not Ready (x.sub.-- PENRDY.sub.-- B)
Source: Sx.sub.-- PENRDY.sub.-- B buffered by a Receiver
Dest: BIU-XMT, TAG Check (LOADORG Control), BIU-RCV
Polarity: Active Low
Type: Unidirectional
If the BIU-RCV PAL detects a parity error on the system bus and is asserting x.sub.-- Bus error.sub.-- B, or the BIU-RCV is asserting x.sub.-- RETRY.sub.-- B, it will continue to assert these signals for two clocks after x.sub.-- PENRDY.sub.-- B has become inactive.
Incoming Message (x.sub.-- MSG.sub.-- B)
Source: DECODER PAL
Dest: BIU-RCV PAL and TBOX
Polarity: Active Low
Type: Unidirectional
This signal indicates to the BIU-RCV PAL that a message for the host CPM 8 has been detected on the system bus (12.sub.a, 12.sub.b).
Stop Messages (x.sub.-- STOPMSG.sub.-- B)
Source: MIX PAL (10m)
Dest: BIU-RCV PAL
Polarity: Active Low
Type: Unidirectional
If a valid message is detected on the system bus and this signal is being asserted, the BIU-RCV PAL will assert x.sub.-- RETRY.sub.-- B.
Data Valid FF (x.sub.-- DATVLDFF.sub.-- B)
Source: Input Register
Dest: BIU-RCV PAL, TBOX, COMBINE PAL, RETURN PAL
Polarity: Active Low
Type: Unidirectional
This signal is active during the data phase of system bus operations. It is a registered input to the CPM card.
System Bus Error (x.sub.-- Bus error.sub.-- B)
Source: Sx.sub.-- Bus error.sub.-- B buffered by a Receiver
Dest: BIU-RCV PAL, Error Log Unit
Polarity: Active Low
Type: Unidirectional
This signal indicates that some active receiver on the system bus has detected a parity error.
Cache Full x.sub.-- CACHEFULL.sub.-- B)
Source: Cache
Dest: BIU-RCV PAL
Polarity: Active Low
Type: Unidirectional
The cache asserts this signal when its invalidation queue has filled or otherwise cannot proceed with invalidations. It causes the BIU-RCV PAL to assert a retry when a write operation initiated by a another processing element is detected on the system bus.
Data Parity Error x.sub.-- DATAPE.sub.-- B)
Source: PARCHCK PAL
Dest: BIU-RCV PAL, BIU-XMT PAL, Error Log Unit, DECODER PAL, RETURN PAL
Polarity: Active Low
Type: Unidirectional
This signal is asserted whenever a parity error is detected on one of the system buses.
TBOX Busy (T.sub.-- BUSY.sub.-- B)
Source: TBOX
Dest: BIU-RCV PAL
Polarity: Active Low
Type: Unidirectional
The TBOX asserts this signal whenever it is unable to process any new incoming messages from the system bus or is unable to service a request from the processor 28 IMP.
Memory Module Not Ready (x.sub.-- MMNRDY.sub.-- B)
Source: Sx.sub.-- MMNRDY.sub.-- B buffered by a Receiver
Dest: BIU-RCV PAL, BIU-XMT PAL
Polarity: Active Low
Type: Unidirectional
If the BIU-RCV detects a parity error on the system bus and is asserting x.sub.-- Bus error.sub.-- B, or the BIU-RCV PAL is asserting x.sub.-- RETRY.sub.-- B, it will continue to assert these signals for two clocks after x.sub.-- MMNRDY.sub.-- B has become inactive.
System Bus Busy FF (x.sub.-- BBSYFF.sub.-- B)
Source: Input Register
Dest: BIU-RCV PAL
Polarity: Active Low
Type: Unidirectional
This signal indicates that a bus requestor has control of the system bus.
Invalidation Command (x.sub.-- INVCMD)
Source: DECODER PAL
Dest: BIU-RCV PAL, CACHE
Polarity: Active High
Type: Unidirectional
Indicates that a bus operation, such as an overwrite, that requires cache invalidation, has occurred on the system bus.
Bus Busy (x.sub.-- BBSY.sub.-- B)
Source: XMIT PAL
Dest: BIU-RCV PAL, System Bus, DECODER PAL
Polarity: Active Low
Type: Unidirectional
This signal indicates that the BIU-XMT PAL is currently executing a bus operation.
Command Valid FF (x.sub.-- CMDVLDFF.sub.-- B)
Source: Input Register
Dest: BIU-RCV PAL, DECODER PAL, Cache
Polarity: Active Low
Type: Unidirectional
Indicates that a command from the system bus is valid within the input register, 18.sub.ai, 18.sub.hi.
Other Side Not Ready (x.sub.-- NRDYO)
Source: Other Side BIU-RCV PAL
Dest: BIU-RCV PAL, System Bus
Polarity: Active High
Type: Unidirectional
This signal from the opposite BIU-RCV PAL indicates that it is asserting "not ready" on its system bus. This is used to detect and escape a possible dead lock condition.
BIU Not Ready (BIU.sub.-- NRDY.sub.-- B)
Source: TIMEOUT PAL
Dest: BIU-RCV PAL
Polarity: Active Low
Type: Unidirectional
Indicates to the BIU-RCV PAL that if any messages come onto the system bus addressed to the host CPM 8, .sub.-- PENRDY.sub.-- B should be asserted until this signal is inactive.
The bus interface unit receive state machine also has a number of output lines which are listed below together with their functions:
OUTPUTS: BIU-RCV, FIG. 6A
Invalidation Command Delay (x.sub.-- DELAY.sub.-- B)
Dest: Cache Invalidation Logic
Polarity: Active Low
Type: Unidirectional
This signal is the x.sub.-- INVCMD signal delayed for one clock.
Processing Element Acknowledge (x.sub.-- PEACKO.sub.-- B)
Dest: System Bus Driver, Test Register
Polarity: Active Low
Type: Unidirectional, Open Collector on System Bus
Once an entire message has been received by the CPM 8, this signal is asserted on to the system bus to the message originator, to indicate the message has been correctly received.
Load Internal Register (x.sub.-- LDNREGI.sub.-- B)
Dest: COMBINE PAL
Polarity: Active Low
Type: Unidirectional
As a message is being sent to the host CPM, this signal loads the internal register as valid data is being received in the input register.
Bus Error (x.sub.-- Berro)
Dest: System Bus Driver
Polarity: Active High
Type: Unidirectional
Indicates that a bus error has been detected on the system bus during any command phase or any data phase in which the host CPM 8 is involved.
Receiving Message (x.sub.-- RCVG.sub.-- B)
Dest: DECODER PAL, TIMEOUT PAL, TBOX LCA, TBXCNTR PAL, RETURN PAL
Polarity: Active Low
Type: Unidirectional
Indicates that a message is currently being received off of the system bus.
System Bus Retry (x.sub.-- RETRYO)
Dest: System Bus Driver
Polarity: Active High
Type: Unidirectional
Tells the originator of the system bus operation to retry the operation at a later time. This signal will be asserted for messages if the TBOX 20 is busy doing another operation or if simultaneous messages are received on both buses. It will also be asserted for write type system bus operations if the cache is currently unable to service the invalidation.
System Bus Not Ready (x.sub.-- NRDYO)
Dest: System Bus Driver, Other Side BIU-RCV PAL
Polarity: Active High
Type: Unidirectional
This signal is asserted as Sx.sub.-- PENRDY.sub.-- B on the system bus after traveling through an inverting open collector buffer. It is asserted when a message is loaded into the input register while BIU.sub.-- NRDY.sub.-- B is active.
There are several internal flip-flops used in the bus interface unit receive state machine. These are indicated as follows:
BIU-RCV Internal Flip-Flop's:
The state machine functions provided by the bus interface unit-receive state machine involve some eleven automatic functions which are shown in FIG. 6B.
The following list indicates the operations provided by the various functions of the bus interface unit-receive state machine:
FIG. 7A is a block diagram showing the signals which relate to the RETURN A state machine 10rta. This state machine has the function to control the select lines of the multiple bus exchange 15 and to signal the mainframe processor logic 28 when "read" data is being returned to it or when an operation has been completed. It will also signal if there was an error that prevented the operation from being completed successfully.
In actuality, there are two separate RETURN programmable array logic units designated as RETURN A (10.sub.rta) and RETURN B (10.sub.rtb). The only difference between the two programmable array logic units is the encoding on the select lines to the multiple bus exchange 15 of the two busses. The acronym RETURN.sub.x will refer to the features of both of these programmable array logic units. The Return PAL is a state machine implemented with a Signetics PLUS 405 device operating at 16 MHZ.
Referring to FIG. 7A the RETURN programmable array logic 10.sub.rta will be seen to receive signals from the parity check unit 10.sub.pc, from the bus interface transmit unit 10.sub.ta, from the error log bus interface 10.sub.u, from the mainframe processor logic 28, from the translator box unit 20.sub.x, and from the bus interface receive unit 10.sub.ra and the timeout unit 10.sub.tm. Additionally, there is an input line from the system bus such as 12.sub.a to the return logic 10.sub.rta.
The RETURN programmable array logic 10.sub.rta will be seen to provide output signals to the multi-bus exchange 15, to the processor logic 28, to the MIX unit 10.sub.m and to the A Bus internal register 18.sub.ai.
Basically the Return-PAL provides a dual bus signal control operation for a processor. It allows "read data" from a dual system bus to be sent to the mainframe processor 28 and signals whether the read command was completed successfully or unsuccessfully. It detects and decides whether the operation should be re-tried or not and tells the mainframe processor the final result status. This is accomplished for each bus of the dual system busses.
The following is a list of input signals and their functions which are passed on to the RETURN programmable array logic 10.sub.rta.
INPUTS TO RETURN PAL, FIG. 7A
Data Acknowledge (.sub.-- DACK.sub.-- B)
Source: BIU-XMT PAL
Dest: RETURN.sub.x PAL
Polarity: Active Low
Type: Unidirectional
This signal becomes active when a system bus operation has completed successfully.
Invalid Address (x.sub.-- INVADR.sub.-- B)
Source: BIU-XMT PAL
Dest: RETURN.sub.x PAL, Error Log Unit
Polarity: Active Low
Type: Unidirectional
This signal indicates that the bus operation in progress had an invalid address error. This means that the destination module did not provide an acknowledge when a operation was directed towards it.
Operation Abort (x.sub.-- ABORT.sub.-- B)
Source: BIU-XMT PAL
Dest: RETURN.sub.x PAL, Error Log Unit
Polarity: Active Low
Type: Unidirectional
If this signal becomes active, it indicates that the bus operation in progress had to be aborted. This could be because of a parity error on the system bus, a timeout, or a module asserting retry during an operation.
Data Valid (x.sub.-- DATVLD.sub.-- B)
Source: BIU-XMT PAL
Dest: RETURN.sub.x PAL, System Bus via Output Driver
Polarity: Active Low
Type: Unidirectional
This signal indicates the "data phase" during the current bus operation.
Command Valid .sub.-- CMDVLD.sub.-- B)
Source: BIU-XMT PAL
Dest: RETURN.sub.x PAL, Error Log Unit, System Bus via Output Driver
Polarity: Active Low
Type: Unidirectional
This signal indicates the command phase during the current bus operation.
IMP Command (M.sub.-- CMD016, M.sub.-- CMD116)
Source: CMDREQ PAL synchronized in Error Log Unit
Dest: RETURN.sub.x PAL, BIU-XMT PAL, TIMEOUT PAL
Polarity: Encoded Bus
Type: Unidirectional, Encoded Commands
These two signals contain the bus operation encoding from the mainframe processor (IMP) interface logic. See Table I . for their values.
PROCR (IMP) BIU Request (M.sub.-- BREQ16.sub.-- B)
Source: CMDREQ PAL synchronized in Error Log Unit
Dest: RETURN.sub.x PAL, BIU-XMT PAL, TIMEOUT PAL
Polarity: Active Low
Type: Unidirectional
This signal validates the mainframe processor IMP Command bits.
Read Invalid Address (RDINVADR16)
Source: CMDREQ PAL synchronized in Error Log Unit
Dest: RETURN.sub.x PAL, TIMEOUT PAL
Polarity: Active High
Type: Unidirectional
This signal indicates that the mainframe processor (IMP) has received an invalid address error and is now reading the address out of the internal registers, 18.sub.ai, 18.sub.bi.
Retry Limit (LIMIT)
Source: Error Log Unit
Dest: RETURN.sub.x PAL, DECODER PAL
Polarity: Active High
Type: Unidirectional
If this signal is active, the next attempt to use the system bus that receives a retry or a bus error will have exceeded the retry limit.
TBOX BIU Request (T.sub.-- BREQ.sub.-- B)
Source: TBOX
Dest: RETURNx PAL, TIMEOUT PAL, BIU-XMT PALS, TAGCHCK PAL
Polarity: Active Low
Type: Unidirectional
This signal indicates to the BIU 10 that the TBOX 20 would like to start sending a message onto a system bus.
Operation Timeout (TIMEOUT.sub.-- B)
Source: TIMEOUT PAL
Dest: BIU-XMT PAL, Error Log Unit, RETURN PAL
Polarity: Active Low
Type: Unidirectional
If this signal becomes active, it indicates that the present operation has timed out waiting for a system bus grant or waiting for data to be returned during a read type operation.
Data Valid Flip-Flop x.sub.-- DATVLDFF.sub.-- B)
Source: Input Register
Dest: RETURN.sub.x PAL, BIU-RCV PAL, TBOX, COMBINE PAL
Polarity: Active Low
Type: Unidirectional
This signal is active during the data phase of system bus operations. It is a registered input to the CPM 8 card.
Receiving Message (x.sub.-- RCVG.sub.-- B)
Source: BIU-RCV PAL
Dest: RETURN.sub.x PAL, TIMEOUT PAL, DECODER PAL, TBOX, TBXCNTR PAL
Polarity: Active Low
Type: Unidirectional
This signal will be active whenever the BIU-RCV PAL is in the process of receiving a message from the system bus.
Data Parity Error (x.sub.-- DATAPE.sub.-- B)
Source: PARCHCK PAL
Dest: RETURN.sub.x PAL, BIU-XMT PAL, Error Log Unit, DECODER PAL
Polarity: Active Low
Type: Unidirectional
This signal is asserted whenever a parity error is detected on one of the system buses.
Test Register Output Enable (TS.sub.-- xNRGOE.sub.-- B)
Source: Error Log Unit
Dest: RETURN.sub.x PAL
Polarity: Active Low
Type: Unidirectional
This test signal causes the internal registers 18.sub.ai, 18.sub.bi to drive their data and the multiple bus exchange 15 to source the A or B bus.
The RETURN programmable array logic unit-state machine, 10rta of FIG. 7A, has a number of output lines which are listed hereinbelow in addition to Table II which indicates the RETURN select lines:
OUTPUTS: RETURN.sub.x PAL FIG. 7A
Multiple Bus Exchange Select Lines (x.sub.-- SELECT.sub.-- 0,x.sub.-- SELECT.sub.-- 1)
Dest: Multiple Bus Exchange via driver
Polarity: Encoded Bus
Type: Unidirectional, Encoded Commands
These two select lines determine in which way the multiple bus exchange 15 routes the various buses. Table II . lists the encoded values for the A and B bus select lines.
Load Internal Register (x.sub.-- LDNREG3.sub.-- B)
Dest: COMBINE PAL
Polarity: Active Low
Type: Unidirectional
This signal being active causes the internal registers (18.sub.ai, 18.sub.bi) to load data on the RxBUS.
BIU Error (x.sub.-- BIUERR.sub.-- B)
Dest: MIX PAL
Polarity: Active Low
Type: Unidirectional
When this signal is returned from the BIU logic it indicates that an operation finished with an error such as a parity error, a retry limit, or an invalid address.
Side Active (x.sub.-- SIDE.sub.-- B)
Dest: COMBINE PAL, DIRECT PAL
Polarity: Active Low
Type: Unidirectional
This signal indicates which system bus an operation went out on. It is used to let the mainframe processor (IMP) logic know which bus to access when read data is returned.
Internal Register Output Enable (x.sub.-- NRGOE.sub.-- B)
Dest: Internal Register
Polarity: Active Low
Type: Unidirectional
This signal causes the internal register (18.sub.ai, 18.sub.bi) to drive its contents onto the A or B bus.
BIU Data Valid (x.sub.-- BIU.sub.-- DATVLD.sub.-- B)
Dest: MIX PAL
Polarity: Active Low
Type: Unidirectional
This signal indicates to the processor (IMP) logic that valid read data is being driven to the M.sub.-- BUS, 28.sub.m.
BIU Data Acknowledge (x.sub.-- BIU.sub.-- DACK.sub.-- B)
Dest: MIX PAL
Polarity: Active Low
Type: Unidirectional
When a bus operation has completed, this signal will be driven to the IMP Logic.
FIG. 7B shows the various functions provided by the RETURN PAL state machine which is resident in the hardware of FIG. 7A. As seen in FIG. 7B, there are 14 functional operational states associated with the RETURN state machine 10.sub.rta or 10.sub.rtb.
The various states provided by the RETURN state machine and also the state transitions are indicated hereinbelow together with the functions that they perform.
TIMEOUT STATE MACHINE
The timeout state machine is a programmable array logic unit which is state machine implemented, usually by means of a Signetics PLUS405 device, which runs at 16 Megahertz. The chief function of the timeout state machine is to send out a request for use of the system bus (12a, 12b) and also to determine if an operation has already timed out.
As seen in FIG. 8A the timeout state machine 10.sub.tn is connected to various of the other modules in the bus interface unit system. The timeout state machine 10.sub.tm will be seen to receive signals from the system bus such as 12.sub.a, 12b, from the bus interface unit receive logic state machine 10.sub.ra, from the error log unit 10.sub.u, from the processor logic 28, from the translator box 20.sub.x, from the mix unit 20.sub.m, from the second bus interface unit receive state machine B, 10.sub.rb.
Likewise the timeout state machine will provide certain output signals as seen in FIG. 8A to the bus 12.sub.a or 12.sub.b, to the A Bus output register 18.sub.a0, to the return array logic 10.sub.rta, to the bus interface unit transmit state machine 10.sub.ta, 10.sub.tb, to the bus interface unit receive state machine 10.sub.ra, to the processor logic 28 and, to the MIX unit 20.sub.m and also to the transmit and receive state machines 10.sub.ta, 10.sub.tb, 10.sub.ra, 10.sub.rb, and the RETURN programmable array logic 10.sub.rtb, and 10.sub.rta.
FIG. 8A shows the timeout state machine 10.sub.tm and the related modules with which it operates. This could be described as a system for requesting bus access (system bus A and B) and setting time limitations for execution of command cycles.
The timeout state machine FIG. 8B, does several important things, for example it checks to see if a command operation has "timed out", and is considered as an "error". This indicates that the time allotted for a given operation has exceeded 512 microseconds. The system will allow up to 16 tries for this type error or other errors.
Further the timeout state machine also functions to put out a bus request to access a system bus.
It also determines if any commanded operation has timed out, that is to say, is no longer a viable command which is capable of execution.
As seen in FIG. 8A, a number of input signals are provided to the timeout state machine 10.sub.tm. The first group of inputs come from the system busses such as system bus A and system bus B. These signals include the system bus A grant and the system bus B grant. Once the timeout state machine has made a system bus request, this signal (validated with A bus busy or B bus busy) will indicate that the operation has been granted access to system bus, which ever bus is not busy A or system bus B.
The other inputs to the timeout state machine from the system bus include the system bus A-busy and the system bus B-busy signals. These signals will indicate that a bus operation is already currently in progress on system bus A or system bus B. The other input from the system bus to the timeout state machine is the clock signal designated as the 512 microsecond clock signal. This clock signal is to determine when bus access operations have timed out because each bus is busy or not available for too long a period.
There are a series of inputs from the error logging bus interface unit 10.sub.u which signals include the processor bus interface unit request signal, and the Read invalid address signal which indicates that the processor has received an invalid address error and is now reading the address out of the internal registers. The processor bus interface unit request signal is a signal which validates the command signals for the processor 28. Added further inputs from the error log unit 10.sub.u, to the timeout state machine 10.sub.tm include the TBOX retry signal which causes the transfer box 20.sub.x to stop sending a message and to retry again once the signal is inactive. It causes the timeout state machine 10.sub.tm to remain in the idle state while it is active. The final signal from the error unit 10.sub.u is the processor retry signal. If this signal becomes active, it causes the processor logic 28 to stop sending its commands to the bus interface unit 10 and to retry it again once the signal is inactive. It causes the timeout state machine to remain in the idle state while the signal is active.
There are several inputs from the processor 28 to the timeout state machine and these signals include the processor bus interface unit request line, the processor command signal line, and the processor data valid line which indicates that valid data is driven to the bus interface unit 10 by the processor. The processor command signals contain encoded values which were shown in Table I.
The transfer box 20.sub.x provides an input signal to the timeout state machine 10.sub.tm which is designated as the transfer box bus interface unit request signal. This signal indicates to the bus interface unit 10 that the transfer box would like to start sending a message onto the system bus (12.sub.a, 12.sub.b).
The mix logic 20.sub.m of FIG. 8A provides an output signal to the timeout state machine which is designated as the bus interface unit data acknowledge signal. This signal indicates to the receiver that the current operation is completed, and the data is being returned from the system bus to the processor 28, and is now valid.
The bus interface receive state machines 10.sub.ra and 10.sub.rb each provide inputs to the timeout state machine. These are called the A side receiving message and the B side receiving messages so that this signal will be active whenever the receiving state machine is in the process of receiving a message from the A system bus 12.sub.a or alternatively from the B system bus 12.sub.b.
Another input is provided to the timeout state machine 10.sub.tm by a signal line from the MIX unit 20.sub.m. This signal is the bus interface unit data acknowledge signal. This signal indicates to the timeout 10.sub.tm state machine that the current operation has been completed and if data is being returned from the system bus (12.sub.a, 12.sub.b) to the processor 28, this data is now valid.
The timeout state machine 10.sub.tm provides a series of output signals to the related modules in the system as discussed hereinunder.
The bus interface unit processor grant signal is seen provided as an output from the timeout state machine to the processor 28. This signal indicates to the IMP processor logic that the bus interface unit 10 has accepted and loaded the command and the address and is now ready to accept the data during an operation.
There are two outputs from the timeout state machine which are fed to the bus interface unit receive state machines A and B (10.sub.ra, 10.sub.rb) by means of signals designated as the bus interface unit-not ready signal. This signal tells the BIU receive-state machine that any incoming message should get a "not ready". The timeout state machine issues this command when it will be finishing an operation in a few clocks and when it is safe to write over the internal registers, 16.sub.ai, 16.sub.bi.
There are two outputs from the timeout state machine 10.sub.tm to each of the A and B transmit state machines 10.sub.ta and 10.sub.tb. These signals are designated as the operation timeout signal. If this signal becomes active it indicates that the present operation has timed out waiting for a system bus grant or waiting for data to be returned during a read operation, or a destination module has asserted itself as not being ready for too long a period. It will be noted that this operation timeout signal is also conveyed to the return state machines 10.sub.rta and 10.sub.rtb.
The timeout state machine 10.sub.tm puts an output signal to the A and B bus output register 18.sub.a0, 18.sub.ab, which is known as the load output register signal. This signal causes the output registers for the A bus and the B bus to load data.
The final output line of the timeout state machine 10.sub.tm is a signal line to the system busses (12.sub.a, 12.sub.b,) and provides a signal designated as the system bus request signal. This signal causes a request to a system bus arbitrator in the central processing module 8 for use of one of the system busses. It will remain active until a bus is granted or else the request is timed out.
FIG. 8B is a flow chart diagram which shows the functional operations of the timeout state machine. As seen in FIG. 8B the basic function in the timeout machine is to note that when a request for data is made, then there is a waiting or a busy period available for subsequent requests until the timeout period has occurred at which case the command cycle will come to a stop.
Likewise in FIG. 8B, the situation for a Write operation shows that after a bus grant and a Write wait period, then the condition will revert to the timeout period which will result in a stop indicating that none of the resources were available to allow the command cycle to be completed.
The following is a list of inputs provided to the timeout state machine 10.sub.tm :
INPUTS: TIMEOUT STATE. MACHINE, FIG. 8B
System Bus A Grant (SA.sub.-- BGNTx.sub.-- B)
Source: System Bus Arbitrator
Dest: TIMEOUT PAL, TBXCNTR PAL, BIU-XMT PAL
Polarity: Active Low
Type: Unidirectional
Once the TIMEOUT PAL has made a system bus request, this signal, validated with A.sub.-- BUSBUSY.sub.-- B, will indicate that the operation has been granted system bus A.
System Bus B Grant (SB.sub.-- BGNTx.sub.-- B)
Source: System Bus Arbitrator
Dest: TIMEOUT PAL, TBXCNTR PAL, BIU-XMT PAL
Polarity: Active Low
Type: Unidirectional
Once the TIMEOUT PAL has made a system bus request, this signal, validated with B.sub.-- BUSBUSY.sub.-- B, will indicate that the operation has been granted system bus B.
System Bus A Busy (A.sub.-- BUSBUSY.sub.-- B)
Source: System Bus through driver
Dest: TIMEOUT PAL, BIU-XMT PAL, CACHE, TBXCNTR PAL
Polarity: Active Low
Type: Unidirectional
This signal indicates that a bus operation is currently in progress on system bus A.
System Bus B Busy (B.sub.-- BUSBUSY.sub.-- B)
Source: System Bus through driver
Dest: TIMEOUT PAL, BIU-XMT PAL, CACHE, TBXCNTR PAL
Polarity: Active Low
Type: Unidirectional
This signal indicates that a bus operation is currently in progress on system bus B.
BIU Data Acknowledge (BIU.sub.-- DACK.sub.-- B)
Source: MIX PAL
Dest: TIMEOUT PAL, TBOX 20, synchronized in BIU 10 to IMP Processor Logic 28.
Polarity: Active Low
Type: Unidirectional
This signal indicates to the receiver that the current operation has been completed and if data is being returned from the system bus to the processor logic, it is now valid.
TBOX BIU Request (T.sub.-- BREQ.sub.-- B)
Source: TBOX
Dest: TIMEOUT PAL, BIU-XMT PALS, TAGCHCK PAL, RETURN PALS
Polarity: Active Low
Type: Unidirectional
This signal indicates to the BIU 10 that the TBOX 20 would like to start sending a message onto the system bus.
IMP PROCESSOR BIU REQUEST (M.sub.-- BREQ 16.sub.-- B )
Source: CMDREQ PAL synchronized in Error Log Unit.
Dest: TIMEOUT PAL, BIU-XMT PAL, RETURN PAL
Polarity: Active Low
Type: Unidirectional
This signal validates the signals M.sub.-- CMD016 and M.sub.-- CMD116.
IMP PROCESSOR COMMAND SIGNALS (M.sub.-- CMD016, M.sub.-- CMD116)
Source: CMDREQ PAL synchronized in Error Log Unit 10.sub.u.
Dest: TIMEOUT PAL, BIU-XMT PAL, RETURN PAL
Polarity: Encoded Value
Type: Unidirectional
These signals contain the encoded values of different BIU operations. Table I . indicates values.
512 Microsecond Clock (C0.sub.-- CLK512.sub.-- U)
Source: Clock Drivers
Dest: TIMEOUT PAL
Polarity: Clock
Type: Unidirectional
This 512 microsecond clock is used to determine when bus operations have timed out.
Read Invalid Address (RDINVADR16)
Source: CMDREQ PAL synchronized in Error Log Unit 10.sub.u.
Dest: TIMEOUT PAL, RETURN PAL
Polarity: Active High
Type: Unidirectional
This signal indicates that the IMP processor has received an invalid address error and is now reading the address out of the internal registers.
IMP Data Valid (M.sub.-- DATAVAL16.sub.-- B )
Source: CONTROL PAL synchronized in Error Log Unit 10.sub.u.
Dest: TIMEOUT PAL
Polarity: Active Low
Type: Unidirectional
This signal indicates that valid data is being driven to the BIU logic by the IMP processor 28.
A Side Receiving Message (A.sub.-- RCVG.sub.-- B)
Source: BIU-RCV PAL
Dest: TIMEOUT PAL, DECODER PAL, TBOX, TBXCNTR PAL, RETURN PAL
Polarity: Active Low
Type: Unidirectional
This signal will be active whenever the BIU-RCV PAL is in the process of receiving a message from the A side system bus.
B Side Receiving Message (B.sub.-- RCVG.sub.-- B)
Source: BIU-RCV PAL
Dest: TIMEOUT PAL, DECODER PAL, TBOX, TBXCNTR PAL, RETURN PAL
Polarity: Active Low
Type: Unidirectional
This signal will be active whenever the BIU-RCV PAL is in the process of receiving a message from the B side system bus.
TBOX Retry (T.sub.-- RETRY.sub.-- B)
Source: Error Log Unit 10.sub.u.
Dest: TIMEOUT PAL, TBOX
Polarity: Active Low
Type: Unidirectional
If this signal becomes active, it causes the TBOX 20 to stop sending a message and to retry again once the signal is inactive. It causes the TIMEOUT PAL to remain in the idle state while it is active.
IMP Processor Retry (M.sub.-- RETRY.sub.-- B)
Source: Error Log Unit 10.sub.u
Dest: TIMEOUT PAL, TBOX LCA
Polarity: Active Low
Type: Unidirectional
If this signal becomes active, it causes the IMP processor logic to stop sending its operation to the BIU 10 and to retry again once the signal is inactive. It causes the TIMEOUT PAL to remain in the idle state while it is active.
The Timeout state machine also includes a number of output signal lines which are listed hereinbelow together with their function:
OUTPUTS: TIMEOUT STATE MACHINE, FIG. 8B
System Bus Request (SA.sub.-- BREQx.sub.-- B)
Dest: System Bus Arbitrator in CPM 8
Polarity: Active Low
Type: Unidirectional
This signal makes a request to the system bus arbitrator for use of one of the system buses. It will remain active until a bus is granted or it is timed out.
Operation Timeout (TIMEOUT.sub.-- B)
Dest: BIU-XMT PAL, Error Log Unit, RETURN PAL
Polarity: Active Low
Type: Unidirectional
If this signal becomes active, it indicates that the present operation has timed out waiting for a system bus grant, or waiting for data to be returned during a read type operation, or a destination module has asserted not-ready too long.
Load Output Register (BIU.sub.-- LDORG.sub.-- B)
Dest: TAGCHCK PAL
Polarity: Active Low
Type: Unidirectional
This signal causes the output registers (16.sub.ao, 16.sub.bo) for the A and B bus to load data.
BIU IMP Processor Grant (BIU.sub.-- MGRNT.sub.-- B)
Dest: DIRECT PAL, CONTROL PAL synchronized in Error Log Unit 10.sub.u.
Polarity: Active Low
Type: Unidirectional
This signal indicates to the IMP processor logic that the BIU 10 has accepted and loaded the command and address, and is now ready to accept the data during an operation.
Stop Incoming Message (STOP.sub.-- MSG)
Dest: MIX PAL (10.sub.m)
Polarity: Active High
Type: Unidirectional
This signal tells the BIU-RCV PAL that any incoming message should get a retry. The TIMEOUT PAL issues this command to prevent the internal registers from being overwritten.
BIU Not Ready (BIU.sub.-- NRDY.sub.-- B)
Dest: BIU-RCV PAL
Polarity: Active Low
Type: Unidirectional
This signal tells the BIU-RCV PAL that any incoming message should get a not-ready. The TIMEOUT PAL issues this command when it will be finishing an operation in a few clocks and it is safe to write over the internal registers, 16.sub.ai, 16.sub.bi.
The timeout state machine provides some twelve discrete functional states which are shown in FIG. 8B. The various states and the state transitions involved are listed hereinbelow together with the functions that they provide.
Described herein has been a programmable timing logic system for allocating limited and predetermined time usage of two system busses for data transfers between a central processor and/or protocol translation unit (TBOX) and data on dual system busses which move to/from external digital modules connected to the system busses. Incomplete cycles are error logged and given a specified number of retries during a limited pre-set time period, after which the allocation of system bus usage is granted to other requesting units on a time limited basis.
The bus interface unit (BIU) integrates data transfer operations between a first computer system, operating under a first message protocol and first clock speed, with a second digital system operating under a second message protocol type and second clock speed.
While a specific embodiment of the programmable timing logic system for the dual bus interface unit has been described, it should be understood that the invention is encompassed by the following claims.
Claims
What is claimed is:
1. In a network where a first resource means and a second resource means are connected via a dual channel bus interface means for communication with first and second system busses via first and second bus interface unit channels, a system for establishing time periods for command and data transfers between said first and second resource means and said first and second system busses, said system comprising: (a) means for requesting access to said first or second system busses for a preset predetermined "p" period of time wherein "p" represents a preset period of time in microseconds that the access request will be operable on a bus before said access request will no longer be accepted by said bus; (b) means for granting system bus access to commands from said first resources means and to messages from said second resource means when said first or second bus is not busy during said "p" period of time; (c) timing means for generating said predetermined preset time periods "p" during which requests for system bus access are operable; (d) and wherein said dual channel bus interface means can operate simultaneously for transmission on one bus and reception on the other bus of said first and second system busses.
2. The system of claim 1 which includes: (a) logic means for enabling said request for bus access to be re-tried "n" times in succession after each said request has exhausted its "p" microseconds of time without gaining bus access to said first or second system bus; (b) means to cancel each said request for bus access when said first or second bus is busy during said "p" microseconds period of time.
3. The system of claim 1 which includes: (a) error log unit means for signalling to and stopping said first resource means and/or said second resource means from transmitting commands or messages to said first and second system busses when said busses are busy or when a receiving unit on said first and second system busses is not ready to receive data.
4. The system of claim 1 which includes: (a) receiving logic means for enabling receipt, by said first or second channels, of messages on said first and second system busses; (b) means for inhibiting said receiving logic means when a command or message transfer operation is still being retried during said preset predetermined time period "p".
5. The system of claim 4 wherein said receiving logic means enables receipt, by said first or second channels, of messages from said first and second system busses and wherein said timing means enables messages to be transferred to said second resource means.
6. The system of claim 1 which includes: (a) a dual bus-sensitive mix signal unit for signaling said timing means that a command or message transfer has been completed between either one of said first or second system busses and said first or second resource means.
7. A programmable logic timing system for dual communication channels between first and second resource means and first and second system busses, said logic timing system comprising: (a) first means for regulating access requests of said system busses to said first and second resource means when said first and second resource means seek to transmit to said system busses; (b) second means for regulating access requests of said first and second resource means to receive data from said system busses when said first and/or second resource means are not busy; (c) timing means for setting a timing period that said first and second regulating means is permitted to initiate access, said timing period being limited to p.times.n wherein p is a preset time period in microseconds allowed for each single access request and "n" is a preset number of retry times that said access to said first and second resource means or access to said first and second system bus is preset for operability, said timing means including: (i) means to preset said value of "n" to limit the number of cycles that an access request can be re-tried; (ii) means for setting said preset time period "p" to limit the time period for each single access request.
8. The logic timing system of claim 7 wherein said first and second regulating means include: (a) means to grant access to a selected one of said first or second system busses when said first or second system busses is not busy; (b) means to enable said first or said second resource means to transmit data to said selected one of said first or second system busses.
9. The logic timing system of claim 8 where said first and second regulating means include: (a) means to enable said first or second resource means to receive data from a selected one of said first or second system busses.
10. The logic timing system of claim 9 wherein each of said first and second regulating means includes: (a) means for enabling transmission of data to said first or second system busses while simultaneously receiving messages from the other bus which is not being used.
11. The logic timing system of claim 7 wherein each one of said dual communication channels includes: (a) input register means for receiving data from said first or second system busses; (b) output register means holding data to be transmitted onto said first or second system busses; (c) and wherein each of said first and second regulating means includes: (c1) means to inhibit data transfer from said first or second system busses to said input register means while data is being transferred to said respective first or second system busses from said output register means; (c2) means to inhibit data transfer from said output register means to said first or second system busses while data is being transferred to said input register means from said respective first or second system busses.
12. The logic timing system of claim 11 which includes: (a) means to receive an acknowledgement signal from said first or second system busses when a receiving unit on said first or second system busses is presently available; (b) means, upon receiving said acknowledgement signal, to stop any data transfer from said first or second system busses into said input register means.
13. The logic timing system of claim 7 wherein said timing means includes: (a) retry means to enable "n" number of retry operations for incomplete data transfers initiated, and wherein said "n" retry operations will not exceed a total duration period of "p" times "n" microseconds.