Single-Etch Stop Process for the Manufacture of Silicon-on-Insulator Substrates

This invention pertains to silicon-on-insulator (SOI) technology and, more particularly, to SOI substrates having relatively thick device layers with moderate thickness variation.

An SOI bonded wafer has a handle wafer, a device layer, and an oxide film (layer), constituting an insulating film, between the handle wafer and device layer. It is made from two semiconductor silicon wafers each having at least one face with a specular gloss finish. An oxide layer is formed on the specular glossy face of one or both wafers, and the two wafers are joined together with the specular glossy faces facing each other and with the oxide layer being between the two wafers. One of the wafers constitutes a handle wafer and the other constitutes a device wafer. The exposed surface of the device wafer is ground and/or etched and polished until the device wafer becomes a thin layer, i.e., the device layer. The joined wafers are heated to an appropriate temperature to increase the bonding strength.

Although various approaches have been proposed for fabricating SOI substrates, each has been found lacking in some respect. In general, certain of the methods proposed to date will produce SOI wafers with defect-free device layers having relatively low thickness variation, but these methods typically produce SOI wafers in relatively low yield and at relatively high cost. Other methods which have been proposed to date will produce SOI wafers in relatively high yield and at a favorable cost, but these methods typically produce SOI wafers having device layers which have an unacceptable thickness variation or which contain defects.

Among the several objects of this invention may be noted the provision of an improved process for fabricating SOI substrates having a device layer thickness of at least about 0.5 micrometers; the provision of such a process in which the variation in the thickness of the device is no greater than about 10% of the thickness of the device layer across the surface of the substrate; and the provision of such a process which produces SOI substrates in relatively high yield and relatively low cost.

In accordance with one aspect of the present invention, therefore, a single-etch stop process for the manufacture of silicon-on-insulator substrates is provided. The process includes forming a silicon-on-insulator bonded substrate comprising a handle wafer, a device wafer, a device layer having a thickness of between about 0.5 and 50 micrometers, and an oxide layer with the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the handle wafer. The device wafer has a boron concentration of at least about 1.times.10.sup.18 boron atoms/cm.sup.3 and a resistivity of about 0.01 to about 0.02 ohm-cm. A portion of the device wafer is removed from the silicon-on-insulator bonded substrate wherein the device wafer has a total thickness variation across the surface of the wafer of less than about 2 micrometers and a defect-free surface after the removal step. The defect-free surface of the device wafer is thereafter etched away to expose the device layer, and the exposed device layer is polished to produce a silicon-on-insulator substrate having a device layer the total thickness variation of which does not exceed 10% of the thickness of the device layer.

In accordance with another aspect of the present invention, a process for etching silicon from the surface of a substrate in an etchant comprising hydrofluoric acid, nitric acid and acetic acid is provided. The process comprises contacting the substrate with a solution containing hydrofluoric acid, nitric acid and acetic acid. After the etch rate begins to diminish, the surface is reactivated by exposing the surface to air or by immersing the surface in water. The surface is thereafter contacted once again with the solution containing hydrofluoric acid, nitric acid and acetic acid.

Other objects and features will be in part apparent and in part pointed out hereinafter.

FIG. 1 is a schematic cross-sectional view of a device wafer used in a process of the present invention;

FIG. 2 is a schematic cross-sectional view of a handle wafer used in a process of the present invention; and

FIGS. 3-7 are schematic cross-sectional views of a silicon-on-insulator bonded wafer at various stages in a process of the present invention.

Corresponding reference characters indicate corresponding parts throughout the several views of the drawings.

Referring now to the drawings, and first more particularly to FIG. 1, onto a silicon device wafer, indicated generally at 20, is deposited an epitaxial layer 22. Silicon device wafer 20 is a p+ wafer, having a boron concentration of between about 1.times.10.sup.18 and about 5.times.10.sup.20 boron atoms/cm.sup.3, preferably between about 1.times.10.sup.18 and about 3 .times.10.sup.20 boron atoms/cm.sup.3, a resistivity of about 0.01 to about 0.02 ohm-cm, preferably a resistivity of about 0.01 to about 0.015 ohm-cm, a thickness of about 300 to 800 micrometers and a diameter which may be, for example, 100, 125, 150, 200 millimeters or more. Epitaxial layer 22 is preferably about 0.5 micrometers to 50 micrometers thick and of a conductivity type and resistivity type (e.g., n or p.sup.-) to allow the use of preferential etchants as described herein. Epitaxial layer 22 is formed on the p+device wafer by epitaxial techniques known in the art, such as, gas source molecular beam epitaxy ("MBE"), ultra high vacuum chemical vapor deposition ("UHCVD"), or atmospheric pressure chemical vapor deposition ("APCVD"). Standard pre-epitaxial cleaning steps such as high temperature (e.g., at least about 900.degree. C.) hydrogen pre-bakes may optionally be employed. In addition, an oxide layer may optionally be formed on epitaxial layer 22.

As shown in FIG. 2, the handle wafer 24 preferably has a diameter which corresponds to the diameter of device wafer 20 and comprises a silicon layer 26 and an oxide layer 28. Because the handle wafer merely serves as a means for handling the substrate, the conductivity type and resistivity type of silicon layer 26 is not critical. Advantageously, therefore, handle wafer may be formed from very low cost silicon. In addition, the total thickness variation for handle wafer is not critical with total thickness variations on the order of about 10 micrometers or less being acceptable. Oxide layer 28 is grown on and surrounds the handle wafer 24 and preferably has a thickness of about 500 angstroms to about 5 micrometers.

As shown in FIG. 3, the device wafer 20 is positioned on the handle wafer 24 so that the device layer 22 overlies the upper face 26 of the handle wafer and contacts the oxide layer 28. The device layer 22 is bonded to the oxide layer 28 at room temperature to form a bonded wafer, generally indicated at 30. The bond strength is thereafter increased by high temperature annealing. As shown in FIG. 3, an upper face of the device wafer 32 is exposed.

The device wafer 20 is removed from the bonded wafer 30 through a series of steps to expose the device layer 22. As will be discussed in greater detail elsewhere, the last step in exposing the device layer 22 is an etching step and it is critical that the surface being etched be defect-free. As used herein, the term "defect-free" means free from precipitated oxides and metal silicides and from defects in crystallinity such as stacking faults, partial dislocation loops, and threaded dislocations. Although the entire thickness of the device wafer 20 may be removed by selective etching, the selective etchants remove silicon at a relatively slow rate. To improve throughput, therefore, it is preferred that the bulk of the device wafer be mechanically removed by grinding and that roughness and damage created in the grinding process be removed prior to etching.

Referring again to FIG. 3, the upper face 32 of the device wafer 20 is ground with a conventional grinder using a relatively coarse grinding wheel such as a D46 grind wheel sold by Genauigkeits Machinenbau Nurnberg (Nurnberg, Germany) or a 320 grit grind wheel sold by Disco Hi-Tec America, Inc. to thin the device wafer. In this rough grinding step, a substantial portion, but not the entire thickness of the device wafer is removed. The amount of material removed in this rough grinding step is determined, in part, by the total roughness of the silicon surface, R.sub.T, after the rough grinding and the additional process steps which will be required to eliminate the roughness and damage created during the rough grinding step. Preferably, the average surface roughness, R.sub.a, after the rough grinding step is less than about 0.5 .mu.m, more preferably less than about 0.3 .mu.m, and the total surface roughness, R.sub.T, after the rough grinding step is less than about 5 .mu.m, more preferably less than 3 .mu.m. The average roughness, R.sub.a, and the total surface roughness, R.sub.T, for a rough ground surface may be determined using a profilomoter with the average roughness, R.sub.a, being measured over a one square-centimeter area.

To remove the roughness and damage created in the rough grinding step, the surface of the device wafer is preferably subjected to a second grinding step, i.e., a fine grinding step. For fine grinding, a 1200 mesh finish grinding wheel may be used. The amount of material removed in the fine grinding step is at least about three times, preferably at least about five times the total surface roughness value, R.sub.T, of the silicon surface after the rough grinding step. If the total surface roughness value, R.sub.T, of the silicon surface after the rough grinding step is between about 3 and about 5 micrometers, therefore, the amount of material removed in the fine grinding step is about 10 to about 15 micrometers, more preferably about 13 to about 15 micrometers. Fine grinding, however, imparts its own roughness and damage to the silicon surface and typically, the silicon surface after the fine grinding step will have an average surface roughness, R.sub.a, of less than 0.1 .mu.m, more preferably less than about 0.02 .mu.m, and a total surface roughness, R.sub.T, of less than about 0.75 .mu.m, more preferably less than about 0.4 .mu.m. The average roughness, R.sub.T, and the total surface roughness, R.sub.T, for a fine ground surface may be determined using a profilomoter which is capable of measuring roughness values of a nanometer or less, with the average roughness, R.sub.a, being measured over a one square-centimeter area.

Referring to FIG. 4, the thinned device wafer 20, after grinding, has an exposed surface 34 and a thickness of about 20 to about 35 micrometers, more preferably, about 25 to about 30 micrometers. In addition, the grinding process should be controlled to minimize the total thickness variation ("TTV") across the ground wafer; for a 200 millimeter diameter wafer, for example, the TTV should be less than 2 micrometers, more preferably less than 0.8 micrometers and even more preferably no more than about 0.5 micrometers.

The ground surface of the thinned device wafer is preferably polished to remove any damage to the exposed surface 34 of the device wafer 20 resulting from the grinding step(s). Polishing is carried out using conventional polishing equipment and a sodium hydroxide stabilized colloidal silica sol such as those commercially available from E.I. du Pont de Nemours & Company (Wilmington, Del.), Nalco Chemical Co. (Naperville, Ill.), and Cabot Corp. (Tuscolo, Ill.) to produce a surface having an average roughness, R.sub.a, as measured on a 1 mm.times.1 mm scan with an optical interferometer, of less than 2 angstroms, preferably less than 0.8 angstroms. The amount of silicon to be removed during the polishing step should be sufficient to remove all crystal damage remaining after the grinding steps. As a general rule, the amount of silicon to be removed should exceed about ten times the total surface roughness of the silicon surface after the fine grinding, i.e., 10.times.R.sub.T, wherein R.sub.T is the total surface roughness of the silicon surface after the fine grinding step. Preferably, therefore, the amount of silicon removed during this polishing step is about 10 to about 25 .mu.m and more preferably about 15 to about 20 .mu.m. Importantly, however, the amount removed should be sufficient to yield a defect-free surface. The existence of a defect-free surface may be determined, for example, by bright light or automated laser inspection after cleaning the polished wafer surface.

Instead of mechanically removing device wafer 20, a significant portion of the device wafer may be removed by non-selective high removal rate chemical etching using, for example, an etchant comprising hydrofluoric acid, nitric acid, and acetic acid in the ratio of 3:5:3 parts by weight (HF:HNO.sub.3 :CH.sub.3 COOH) which is commonly referred to as CP-4. CP-4 etches silicon at a rate of about 80 micrometers per minute. The remaining portion of the device wafer 20 may then be removed by smooth grinding, polishing or a combination of smooth grinding and polishing as described above. If nonselective etchants are selected, care should be taken to ensure that the etching is discontinued before the device layer is reached.

Referring to FIG. 5, the periphery of the bonded wafer 30 may optionally be abraded after grinding and prior to polishing to remove the edge margins 36, 38 which may contain areas of delamination between the device layer and the oxide layer. The width w (FIG. 6) of edge margins removed is approximately 2-10 mm. Also, the periphery of the bonded wafer 30 is preferably abraded at an angle .theta. (preferably 0.degree.-30.degree.) to form a beveled edge 40 to minimize the trapping of particles in the corner of that edge. The periphery of the bonded wafer 30 may be abraded by grinding, wet or dry etching, or by a chemical/mechanical polishing process. Masking 42 which is applied prior to the abrading process prevents debris, generated during the abrading process, from pitting or otherwise damaging the p+ device wafer 20 and device layer 22. After the periphery of the bonded wafer 30 is abraded, the masking 42 is stripped from the top surface of the bonded wafer.

Referring now to FIG. 7, the ground, polished and optionally edge-stripped device wafer 20 is immersed in a suitable etchant which preferentially etches the device wafer without etching the device layer 22. Such etchants are well known in the art and include, for example, mixtures of hydrofluoric acid, nitric acid and acetic acid in a ratio of about 1:3:6-12 parts by weight (HF:HNO.sub.3 :CH.sub.3 COOH), and more preferably about 1:3:8 parts by weight (HF:HNO.sub.3 :CH.sub.3 COOH), and at a temperature of about 20.degree. C. to about 30.degree. C. A surfactant such as FC-193 manufactured by 3M Company may be added to improve the etching performance. Autocatalytic poisoning will typically cause a reduction of the etch rate and eventually the cessation of etching after about several hundred nanometers (i.e., about 200 to about 300 nanometers) of silicon are etched from the surface. To continue the etching process, therefore, the etchant may be continuously reconditioned by adding oxidants such as hydrogen peroxide or ozone, or alternatively by withdrawing the wafer from the etchant and immersing it in water, oxygenated water, ozonated water (e.g., about 1-2% by weight ozone) or by exposing it to air or other oxidizing atmosphere for about 1 to about 10 seconds, preferably about 1 to about 5 seconds. The reactivated surface is then reimmersed in the etchant and etching proceeds vigorously until another several hundred nanometers are removed. This process of reactivating the surface and immersing the reactivated surface in the etchant is continued until the device wafer 20 is removed and the device layer 22 is exposed at which point no amount of air/water exposure will reactivate the surface. In general, the amount of silicon removed in this etching step is at least about 5 micrometers, preferably between about 5 and about 15 micrometers, and most preferably about 5 to about 10 micrometers.

Alternatively, the ground, polished and optionally edge-stripped device wafer 20 may be etched using a rotating chuck and a spray. In this embodiment, the device wafer is mounted onto the chuck and rotated. Etchant is dispensed through a nozzle array which is attached to a movable arm and directed at the surface of the rotating wafer. The exact orientation, position and movement of the nozzle array, the rate of rotation of the wafer, the composition of the etchant, and the dispense rate of the etchant can be controlled to achieve a uniform and controlled etch rate. In addition, the surface can be reactivated (if autocatalytic poisoning occurs) by dispensing water, oxygenated or ozonated water, filtered air or the like through the nozzle array instead of etchant. Upon completion of the etching, the wafer may be spun dried.

Typically, the etched surface is mildly stained. To remove the stain, the exposed device layer may be subjected to a "touch" polish. That is, only about 100 to about 500 nanometers, preferably about 200 to about 400 nanometers, and more preferably about 300 nanometers of silicon is removed in a chemical/mechanical polishing process using, for example, a dilute ammonia stabilized colloidal silica slurry and conventional polishing equipment. A preferred ammonia stabilized colloidal silica slurry is Glanzox 3900, which is commercially available from Fujimi Incorporated of Aichi Pref. 452, Japan. Glanzox 3900 has a silica content of from about 8 to about 10% and a particle size of from about 0.025 to about 0.035 .mu.m. If the ammonia stabilized silica slurry is not diluted prior to use, the polished wafer will not be as smooth as a wafer treated with a diluted slurry. A dilution of about one part silica slurry to about 10 parts deionized water is preferred.

After touch polishing, the device layer 22 has a thickness of about 0.5 to about 50 micrometers, preferably about 0.5 to about 20 micrometers, and a surface which is characteristic of a polished, conventional silicon wafer. That is, the resulting device layer has a surface with an average roughness, R.sub.a, of no more than about 0.5 to 1 Angstrom over a surface a 1 mm.times.1 mm scan with an optical interferometer and a TTV which is about 10% of the maximum thickness of the device layer for a device layer thickness of about 3 microns and less and a TTV which is less than 10% of the maximum thickness of the device layer for a device layer thickness of between 3 and 50 microns.

To getter any residual boron in the device layer, the polished surface may be thermally oxidized at a temperature greater than about 900.degree. C. Any residual boron is segregated in the oxide which is then stripped using, for example, an aqueous solution containing hydrofluoric acid.

As previously described, the high temperature annealing step (to increase the bonding strength between the device layer of the device wafer and the oxide layer of the handle wafer) may be carried out immediately after the room temperature bonding step. Alternatively, however, the high temperature annealing step may be carried out after the device wafer is etched away and the device layer is exposed. Deferring the high temperature annealing step until after the device wafer is removed advantageously minimizes the diffusion of boron from the p.sup.+ device wafer into the device layer.

In view of the above, it will be seen that the several objects of the invention are achieved and other advantageous results attained. As various changes could be made in the above constructions and processes without departing from the scope of the invention, it is intended that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.