Computer With Two-Dimensional Merge Tournament Sort Using Offset-Value Coding

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1. Field of the Invention

The present invention relates to the field of sorting and computer methods and apparatus for sorting.

2. Description of the Related Art

Sorting is important to the computer field in many applications. For example, enterprises and other users often wish to sort list of employees, customers, fries, inventory, data or other categories of information. The sort order can be by any criteria including alphabetical and numerical in ascending or descending order for one or more "fields" within the records. Because sorting is important in the computer field many methods and apparatus for sorting have been devised. Computer sorting is described in many works including, Sorting and Searching, The Art Of Computer Programming, Vol. 3 by D. E. Knuth, and Sorting and Sort Systems by H. Lorin and in Programs=Algorithms+Data Structures by N. Wirth.

The efficiency with which sort algorithms perform in computers is, in part, a function of the architecture of computer systems. Computer systems generally have an architecture which includes processing units (central processing units-CPU's) and a storage system which includes internal storage and external storage. The internal storage may include cache, primary and secondary random access memory. The external storage includes I/O units such as magnetic or optical disc or magnetic tape drives.

Information to be sorted is organized into records. The task of sorting causes all the records to be sorted to be accessed in the storage system. The processing units as part of the sort processing fetch the records from the storage system and store the records back into the storage system with an ordering determined by the sort algorithm.

For purposes of sorting, sorting algorithms have been characterized as being internal or external. An internal sort is one in which the records to be sorted are resident within internal storage of the computer system. An external sort is one in which the records to be sorted are not fully resident within internal storage and hence are stored in external storage during the sort processing.

When the number of records to be sorted is small so that the records can all be contained concurrently in the internal storage, then generally an internal sort algorithm is preferred since it performs more quickly than an external sort algorithm since, in an internal sort, time need not be wasted in accessing records from the slower external storage.

When the records to be sorted cannot be contained entirely within the internal storage system, then sorting algorithms tend to be slowed down to account for the additional time required to access records from the slower external storage. Sorting a large number of data records with an external sort usually requires a two stage process. The first stage is the initial sorting of as many data records as can be accommodated by the faster internal storage to create strings of sorted records. The second stage involves merging the strings of sorted records, with accesses to the external storage, into a final sorted sequence of records.

For external sorts, sorting algorithms have been designed to accommodate different I/O computer architectures. For example, when a computer system is limited by the access time required for accesses to disk storage, sorting algorithms which minimize the number of external storage accesses enhance the efficiency of the sort algorithm.

For internal sorts, the literature has assumed a flat random access machine (RAM) model for internal storage in which all memory accesses to internal storage are of identical computational cost. With this assumption, the literature has concluded that algorithms such as quicksort, heapsort and tournament sort provide the greatest efficiency for internal sorts. The latter two algorithms are frequently employed as replacement selection techniques for the internal sorts of external sort strings. Tournament sorts are described in the standard textbooks such as Knuth, D. E. "Sorting and Searching", The Art of Computer Programming, Vol. 3 and Lorin, H. Sorting and Sort Systems.

Contrary to the assumption of the literature, however, the flat random access machine (RAM) model is not accurate for large computers (such as main frames) nor is it accurate for even smaller computers (such as storage system servers). As architectures of computer systems have evolved, many improvements have been developed for enhancing the speed with which internal storage operates.

The internal storage system today is typically hierarchical including a plurality of different internal storage units of different speeds and designs. Typically, the internal storage system includes cache units which operate at high speed (for example, the same speed as that of the processing units), includes primary units (main store units) which operate at slower speeds than the cache units, and may include secondary units which operate at even slower speeds than the primary units. In modem storage systems, the cache units are at times organized into a plurality of cache subunits where each cache subunit may be of differing capacity and speed. Similarly, primary storage units and secondary storage units within the internal storage can be formed of multiple units, with speeds varying for different patterns and volumes of access. In addition, virtual-to-real storage address translation can cause access delays in storage systems that employ virtual addressing.

In accordance with the above background, there is a need for improved sorting methods and apparatus in computers which are particularly adaptable and efficient for sorting in computers having hierarchical storage units in the storage system.

The present invention is a computer system with two-dimensional tree sort and in a particular embodiment a merge tournament sort with offset-value coding.

The computer system includes internal storage for storing a list of records R.sub.1, . . . , R.sub.N to be sorted where each record is associated with a corresponding one of the keys K.sub.1, . . . , K.sub.N, respectively, for ordering the records. The computer system includes at least one processing unit for processing the records and keys and for controlling the internal storage.

In order to perform the sort of N records, the processing unit forms a two-dimensional tree structure, in the internal storage of nodes. The tree structure is based upon a logical tree having a binary tree structure including a single root node and a plurality of leaf nodes. Each node, except the root node, is a child of exactly one parent node. The logical tree has (2.sup.m -1) nodes (where m=ceil[log.sub.2 (N)]) and where each node is a parent node of at most two child nodes. The two-dimensional tree organizes the (m) nodes of the logical tree into a plurality of subtrees, where each subtree is formed by a plurality of the nodes organized in a binary tree structure and where, if a particular node in a particular subtree is the root node in the particular subtree, then the parent node of the particular node is a leaf node in another subtree whereby the another subtree is the parent subtree of the particular subtree. For each leaf node in the tree, there is an ancestor chain of nodes (from child to parent, from parent to grand-parent, from grand-parent to great-grand-parent, . . . and so on) that connects each leaf node to the root node.

In order to perform the sort, the processing unit stores codes representing keys into nodes in the two-dimensional tree and performs a tree sort of the keys using the codes. The codes are accessed by accessing the subtrees and processed to determine the sort order of the keys and the corresponding records.

The sort process involves traversing ancestor chains between leaf nodes and the root node, that is, a sequence of m child-parent pairs for each ancestor chain. The ancestor chain traversal can be either from the root node to leaf node or vice-versa, with the root regarded as the m-th generation ancestor of each leaf node. The ancestor chain traversal follows an initialization process that stores initial values into the nodes. Each ancestor chain traversal (between leaf node and root node) determines the next key in the sort order. Since there is a comparison at each node in the tree, each ancestor traversal requires m comparisons. Since there are N ancestor chains, there are Nm comparisons and these may entail Nm storage system accesses. Accordingly, the number of and efficiency of such accesses in the storage system hierarchy is of paramount importance in determining the efficiency of the sort process. In the present invention, to achieve sort efficiency, the number of storage system accesses (fetched lines) required for an ancestor chain traversal is kept low. The present invention only requires h accesses for ancestor chain traversals where h is the number of levels of subtrees, where h equals m/k, and where k equals the number of levels within a subtree.

Faster sorts are achieved having the ancestor chain traversals equal to h by organizing the logical binary tree of nodes into a tree of subtrees with h levels of subtrees. Each subtree has a binary tree structure, although the tree of subtrees does not necessarily have a binary tree structure since each subtree can have more than two child subtrees. The logical binary tree structure is preserved within the structure of the tree of subtrees since each subtree has a binary tree structure.

In a particular "loser-tree" tournament sort example of the invention, the ancestor chain traversal proceeds from leaf node to root node. First the tree is initialized to "automatic winners". To load with automatic winners, in one particular example, bit 0 of byte 0 of a codeword is set to "1".

Next the tree is loaded by processing codes for input keys in pairs for the input keys K1, . . . , KN. The load proceeds with pair K1 and K2, pair K3 and K4, and so on until pair K(N-1) and KN. For each comparison of codes for key pairs, the lesser of the two comparands (in a descending sort that sorts from largest to smallest) is stored at the current tree node with the code of the greater of the two comparands used in continuing the ancestor chain traversal, that is, the code of the greater of the two comparands is compared with the contents stored at the parent of the current tree node.

When all of the N input keys have been processed, the winner at the root node is the first (largest value of all the N keys). To sort the tree, the code at the parent node of the latest winner (at the root node) is compared with an "automatic loser" and the winner is placed at that parent node. The ancestor chain traversal continues until a new latest winner is produced at the root node. The process of traversing the ancestor chain continues until all keys have been ordered, that is until an "automatic loser" becomes a winner.

The computer system with two-dimensional (2-D) merge sort of the present invention has a number of advantages.

As one advantage, the key extraction is a high speed method for implementing multi-key, bi-directional sorts. The table-driven method is efficient and following the key with a sequence pointer permits a particularly effective stability that conserves the input order of equal keys since when equal codewords force actual key comparisons, no loop test is required.

As another advantage, if the tournament tree has m levels, the 2-D tree has ceil [m/k] levels of subtrees. With the usual representation of a binary tree, the parent of the element having index q is the element with index q/2, and the ancestor chain will use (m-1) or (m-2) cache lines. The present invention, however, only requires m/k (or m/k+1) accesses of cache lines. In case data accesses displace lines, the probability of miss penalties is reduced.

The invention includes an increased benefit from pre-fetching, through the asynchronous operation of the storage system and other subsystems of the computer. Because fewer lines are involved and more instructions are executed per line (the classical definition of locality of reference is satisfied), the pre-fetch mechanism (when available on a computer as is likely with evolving architectures) has time to make advance requests to the storage system for the next-required ancestor group. Note that the leaf subtrees of a common binary tree comprise half the nodes, whereas in the 2-D structure of the present invention (1/2+1/4+. . . +1/(2.sup.k)) nodes (for more than half) are contained in the leaf subtrees. Thus a single prefetch of codes for nodes in a subtree will eliminate most misses for a single ancestor chain traversal, and the leaf subtrees can, for example, be stored in the secondary cache, thus increasing the group size n which can be effectively sorted. This advantage is illustrated in Example I and Example II hereinafter.

Enhancements to the conventional tournament sort are implemented in certain embodiments having prefetch facilities. Under a uniform distribution, the current root node will be the next winner (element in sort order) with probability 1/2 and analogously 1/4, 1/8, . . . probabilities exist for the remaining objects on the path just traversed. By prefetching the leaf node subtree of its parent (which is required if the probability prediction is correct), a several-hundred cycle miss penalty can be avoided. In addition, while processing the output list for the current winner, the required leaf node for the next ancestor chain traversal can be pre-fetched.

This ability to `plan ahead` and thereby make use of prefetch facilities is not available for many sort algorithms (such as heapsort), and prefetching is also prohibitive because of the sheer number of access requests in conventional binary tree representations.

(3.) The address of the parent subtree of the current winner can be quickly calculated using the index and the fact that line sizes are a power of 2. By storing the record address with the key, rather than as an external node, advantage is taken of the property of merges of sorted subgroups that the key is likely to be brought into the cache, thus permitting the sort of variable length records or scattered database input.

(4.) A single load replaces two or three instructions for computing parent addresses. These loads can be interleaved with current subtree processing to eliminate pipeline delays.

As the j-th consecutive winner within the subgroup emerges, the codeword (-(N-j)), is used to commence the next iteration. These `dummy` nodes (automatic losers or infinity) have the property that they `win` in comparisons with other `dummy` nodes, thus producing faster branches rather than stores as the tree is depleted. In addition this loads the tree with bit 0 of all codewords=1, eliminating re-initialization for the next subgroup.

(5.) Tournament trees are frequently used for merging as suggested by Knuth and Lorin and codeword lists obtained as above are suitable for such merge algorithms, as described in Conner, "Offset Value Coding" I.B.M. Technical Disclosure Bulletin, Vol 20, No. 7, December 1977. However, Quicksort offset-value codes as described by Baer and Lin, "Improving Quicksort Performance With A Codeword Data Structure", IEEE Transactions On Software Engineering, Vol. 15, No. 5, May 1989 cannot be so employed, thus precluding efficient cache-partitioning of data. The same algorithmic device can be used to merge sorted strings in an external sort.

Note that if log.sub.2 (N), a minimal comparison (tournament) sort will usually produce m or m-1 comparisons per dement as suggested by Knuth. However, a hardware device described in I.B.M. European Patent Application #91104337.0 Database Processing System (3/20/91) must perform m comparisons.

The present invention, by way of distinction structures the merge tree as in a conventional tournament sort to provide for minimal comparisons. Since the number of merge lists is usually small relative to n, the addressing speed-up is achieved by creating on-the-fly a table of half-word relative parent pointers. By the same token, cache misses on this small tree are improbable, and the second dimension is not needed.

The implementation of the present invention in IBM BAL for System/390 for the Amdahl HURON and UTS COBOL compiler products demonstrates speed-ups of over 20 times compared with UNIX C sorts and parity or better with the most highly optimized MVS products (20% estimated average in-core sort gain over Syncsort 3.4).

On the other hand, the SPARC (Sun) implementation of the 2-D tree of the present invention executes a comparison so efficiently (3.5 cycles) that the 2-D sort is used for all merge algorithms. The Sun SPARC implementation internal sort measures a 100-200 times speedup over UNIX (Solaris OS) sort, 10-20 times over Oracle sort, and 4-7 times over Syncsort for Unix Rel 1.

The foregoing and other objects, features and advantages of the invention will be apparent from the following detailed description in conjunction with the drawings.

FIG. 1 depicts a block diagram of the computer system of the present invention.

FIG. 2 depicts a representation of a 31-node, 5-node-level binary tree for sorting 32 records.

FIG. 3 depicts a representation of the binary tree of FIG. 2 organized into a subtree structure formed of a tree of subtrees with two rows of subtrees where each subtree, other than the root subtree has three binary levels.

FIG. 4 depicts a representation of the subtree structure of FIG. 3 using the A.sub.ij 2-D notation.

FIG. 5 depicts a representation of a tree-with (2.sup.20 -1) internal nodes, with 2.sup.19 leaf nodes and 2.sup.20 keys.

The computer system 3 of FIG. 1 is composed of hardware 5 and software 6. The hardware 5 includes one or more processors 10, typically a central processing unit (CPU), internal storage control 14 and internal storage 15, external storage control 22 and external storage 19. The internal storage 18 includes one or more cache storage units 15 and is shown with a first cache unit 15-1 and a second cache unit 15-2. The internal storage 18 includes one or more primary storage units 16 that constitute the main store of the computer system and the primary storage units 17 are shown with a first primary unit 16-1 and a second primary unit 16-2 by way of example. The internal storage 18 includes one or more secondary storage units 17 that are shown with a first secondary unit 17-1 and a second secondary unit 17-2 by way of example. The external storage 19 includes one or more I/O storage units 17 and is shown with X I/0 units 23-1, . . . , 23-X.

The software 6 includes an operating system 7 and user (application) programs 8. The computer system 3 executes user programs 8 in the hardware 5 under control of the operating system 7.

Referring to FIG. 1, the operating system can be, for example, the UNIX operating system that has fries and processes that execute under the control of a kernel. A process is a computer program in a state of execution. The computer system of FIG. 1, when running the UNIX operating system, has three levels of operation: user, kernel, and hardware. Typically, application programs 8 run at user level, and request the services of the operating system 7 by means of system calls. Application programs of particular interest in the present invention employ sort algorithms.

The kernel acts as a resource manager for all of the resources of hardware 5 of the computer system 3 of FIG. 1. Primarily the kernel has two functions. The first is to provide a large degree of device independence to the application programs by masking details of the various hardware resources needed during computation. The second is to perform various supervisory and control functions so that the needed resources are scheduled as necessary. The kernel is partitioned into a process control subsystem, a file management subsystem, a memory management subsystem, and other supporting subsystems.

The process control subsystem creates or terminates processes in response to explicit or implicit user requests, controls process behavior, obtains the resources that are necessary from the other subsystems for process execution, and provides means for inter-process communication. Chief among the resources that a process needs during execution are usage of the processors 10, usage of internal storage 18, access to data stored on external storage 19, and other facilities.

The memory management subsystem regulates the use of internal storage 18 for efficient, protected, and convenient access to programs and dam, and coordinates with file management subsystem so that file data is transferred between internal and external storage as needed by processes. In most UNIX operating system versions, the memory management subsystem provides the convenient illusion of a linear space in which processes can expect to reference the data or code that they need during execution, although the internal storage 18 employed for meeting this need is neither linearly nor continuously present for a specific process. This illusion is supported by managing the internal storage in small units of allocation, called pages, and by dynamically adjusting the mapping between process generated references (also called addresses) and the pages into which the data accessed by these references reside.

The page tables maintaining these mappings may migrate within the internal storage system hierarchy during address translation, increasing the departure of a modern system from the simple RAM model of computation that has heretofore been assumed when analyzing sort algorithms.

Over the duration that the operating system executes a specific process on a processor, the processor is said to be functioning in the context of the process. The context of a process refers to the overall hardware and software state of a processor that makes it possible for the memory references generated during the process execution to map correctly to the physical addresses that contain the instructions or data needed for computation. Accordingly, the context of a process is defined by all the machine register contents that need to be saved at the time that the process control subsystem 35 disembarks the process from execution on a processor. This "saved context" information must be subsequently restored on a processor, in order to continue the execution of that process on the processor. The operation of a processor of stopping the execution of one process, saving its context, and restoring the context of a second process, so that the second process uses the processor instead of the first process, is called a context-switch.

The file management subsystem commonly comprises one or more file systems, each of which spans a single logical partition or subdivision of an external storage medium such as a disk, and which organize the data within that partition. Generally, multiple implementations of file systems are available, each providing a common set of services to the remainder of the operating system and differentiated from other implementations by virtue of specialized functions and structure that are appropriate for the specific uses intended by the implementation. The common set of services offered by various file system implementations to the other kernel subsystems is generally called the Virtual File System interface.

The transfer of data between internal storage and external storage I/O devices such as disks, terminals, or printers, and the control of such devices, is accomplished by the services of kernel modules called device drivers.

The transfer of data between internal storage units and the processors 10 is typically under control of different units that constitute the processors 10. Increasingly in computer architectures, an instruction unit (I-UNIT 11 of FIG. 1) is responsible for fetching and processing instructions, a storage unit (S-UNIT 12 in FIG. 1 ) is responsible for controlling the accessing of information in internal storage 18. Where the computer system of FIG. I organizes information in the system on a virtual basis, then the processors 10 include a virtual-to-real translation facility (V/RTF) for converting between virtual and real addresses. Typically, the V/R translation facility 13 includes a translation-lookaside-buffer 13' (TLB) that is used to assist in address translations between virtual and real addresses. Also, the processors 10 include register files 9 that include F registers 9-1, 9-2, . . . , 9-F for rapid access to information used in executing programs. Typically registers in file 9 are 32-bit or 64-bit registers.

FIG. 2 depicts a representation of a logical binary tree that is formed in internal storage 18 of FIG. 1 for sorting N records R.sub.1, . . . , R.sub.N ordered by the keys K.sub.1, . . . , K.sub.N, respectively, extracted from those records. In FIG. 2, by way of example, N equals 32. Each node A.sub.q of the tree is used to store codeword/index information, C.sub.q, representing one of the keys K.sub.1, . . . , K.sub.N.

In FIG. 2, the keys K.sub.1, . . . , K.sub.N are to be sorted by storing codes at locations defined by nodes in internal storage 18 of FIG. 1. To execute the sort process, a logical binary tree structure of binary nodes is formed. A binary node is a node with at most one parent node and two child nodes. In FIG. 2, the binary nodes are designated by an "*". The binary tree structure includes the N-1 nodes A.sub.1, A.sub.2, . . . , A.sub.q, . . . , A.sub.N-1. Each of the binary nodes in the tree structure, in general, includes one parent node and two child nodes where the parent of any child A.sub.q is A.sub.q/2. The binary tree structure has the root node A.sub.1 which has two child nodes, A.sub.2 and A.sub.3, but no parent node and includes the leaf nodes A.sub.(N/2), A.sub.(N/2+2), . . . , A.sub.(N-1) which each have a parent node but no child nodes, per se, in the tree structure. However, the leaf nodes A.sub.(N/2), A.sub.(N/2+1), . . . , A.sub.(N-1) each are associated with two keys in a parent child relationship. For example, A.sub.N/2 is associated with K.sub.1 and K.sub.2, A.sub.(N/2+1) is associated with K.sub.3 and K.sub.4 and so on with A.sub.(N-1) associated with K.sub.(N-1) and K.sub.N.

In FIG. 2, the sort process is commenced with an initialization process during which nodes A.sub.(1), . . . , A.sub.(31) are stored with initial values that are "automatic winners".

Next, in FIG. 2, the sort process traverses ancestor chains between each of the leaf nodes A.sub.(N/2), . . . , A.sub.(N-1), that is, leaf nodes A.sub.(16), . . . , A.sub.(31), and the root node A.sub.1. The ancestor chain traversal is a sequence of m=ceil[log.sub.2 (N)] child-parent pairs which, since N=32 in FIG. 2, is 5 pairs. The traversal can be either from the root node to a leaf node or vice-versa, with the root regarded as the m-th generation ancestor of the particular leaf node. By way of example, if the ancestor train traversal starts with leaf node A.sub.24, then the ancestor chain is A.sub.24 to A.sub.12, A.sub.12 to A.sub.6, A.sub.6 to A.sub.3, A.sub.3 to A.sub.1 or more succinctly A.sub.24, A.sub.12, A.sub.6, A.sub.3, A.sub.1. By way of further example, if the ancestor chain traversal starts with leaf node A.sub.16, then the ancestor chain is A.sub.16, A.sub.8, A.sub.4, A.sub.2, A.sub.1.

In FIG. 2, each ancestor traversal requires 5 comparisons (m=5). Since there are 32 ancestor chains, there are 32*5=160 (N*m) comparisons and 160 storage system accesses. The present invention reduces the number of fetches for each ancestor chain traversal from 5 fetches common in the prior art to 2 (ceil[m/k] where m=5 and k=4) for a total of 64 (32*2).

In order to achieve faster sorts, the m-node ancestor chain traversal is achieved with m/k storage system accesses, the logical binary tree of FIG. 2 is organized into a tree of subtrees as shown in FIG. 3.

The tree of subtrees structure for the logical binary tree of FIG. 2 in FIG. 3 is an example where N equals 32. In FIG. 3, two rows of subtrees are shown. The row 1 subtree 31 includes three binary nodes of FIG. 2, A.sub.1, A.sub.2, and A.sub.3 in two binary levels that form a single root subtree. Row 2 includes 4 subtrees 41, 42, 43 and 44 each subtree having 7 binary nodes in three binary levels. The tree of subtrees of FIG. 3 is not a binary tree since the root subtree 31 has four (not two) subtrees. The logical structure of the logical binary tree of FIG. 2 is preserved within the structure of the tree of subtrees in FIG. 3, since each subtree in FIG. 3 has a binary tree structure.

For a "loser-tree" tournament sort, using the 2-D tree of FIG. 3, the ancestor chain traversal proceeds from leaf node to root node. First the tree is initialized to "automatic winners". To load with automatic winners, in one particular example, bit 0 of byte 0 of a codeword is set to "1".

Next the tree is loaded by processing codes for input keys in pairs for the input keys K1, . . . , KN. The load proceeds with pair K1 and K2, pair K3 and K4, and so on up to K(31) and 32. For each comparison of codes for key pairs, the lesser of the two comparands (in a descending sort that sorts from largest to smallest is stored at the current tree node with the code of the greater of the two comparands used in continuing the ancestor traversal, that is, the code of the greater of the two comparands is compared with the contents stored at the parent of the current tree node.

To sort the tree, the code at the parent node of the latest winner (at the root node) is compared with an "automatic loser" and the winner is placed at that parent node. The ancestor chain traversal continues until a new latest winner is produced at the root node. The process of traversing the ancestor chain continues until all keys have been ordered, that is until an "automatic loser" becomes a winner. Notation used herein is as follows: ##EQU1##

In order to perform the sort, the following steps are performed:

(1.) Key extraction: The input records (from a database, fiat file, compiler internal record, or otherwise) are scanned for keys and all keys are converted to strings comparable by machine instructions, with bits of ascending keys inverted. Optionally a sequence number or record address is appended.

(2.) A tournament tree is initialized as a tree of subtrees of size 2.sup.k, where the cache line size of the given machine=2.sup.(3+k) bytes. The root doubleword (or quadword for architectures with 64-bit registers) is reserved for pointers to the ancestor chain within the subtree whose leaf node is the parent dement of the root of the current subtree. The initialization process establishes the pointers. For a doubleword architecture, a preferred embodiment contemplates line sizes from 32 to 256 bytes. The number of subtrees depends on the size of the primary cache and the presence of a secondary cache, so that the total tree size is N elements.

If log.sub.2 (N)=m and m [mod] k>0, the root subtree is adjusted to contain m [mod] k levels, so that all other cache lines are fully utilized.

(3.) The N keys are subdivided into groups of n elements, with a remainder N [mod] n. Codewords in one example formed of 8 bytes for use in computer systems having 32-bit registers are as follows:

byte 0

bit 0=reserved as indicator of "automatic winner" in load phase or "automatic loser" ("infinity") in sort phase.

bits 2-7=indicator of full word (bytes/4) offset within the key at which the loser differed from the prior comparand (initially 0).

bytes 1-4--copy of the fullword at which the inequality was detected.

bytes 5-7--three byte index of key

In the 32-bit register example above, the bytes 0-3 are conveniently stored in a first register, for example, register 9-1 and bytes 4-7 are store in register 9-2 in FIG. 1. The embodiment described does not require an expensive indirect key access of internal storage with a 1-cycle register comparison (bytes 0-3). If a second test is required of byte 4 due to the equality of the first fullword (bytes 0-3) of both comparands, then a branch is taken to a secondary comparison routine. Note that the codewords can be selected with any convenient size, for example, to maximize key length or utilize 64-bit registers in computer systems having such registers.

A sample 8-byte codeword (for keylengths of 24 for K.sub.1, . . . , K.sub.N) is as follows:

The meaning of the sample 8-byte codeword is as follows:

i) Byte 0 has offset hex 04 that indicates 4th fullword inequality detected at bytes 16-19

ii) Bytes 1, 2, 3 and 4 indicate that bytes 16-19=`ABCD`

iii) Bytes 5, 6 and 7 indicate that the loser of the comparison is K.sub.17 (17=hex 000011), whose partial key value is incorporated in codeword bytes 1-4

(4.) As each subtree is traversed, the pointers to the ancestors within the parent subtree are loaded into an alternate set of registers from those currently in use. Codewords are stored in sort order. The following LISTING 1 is a fragment of a routine that performs a nodal comparison of an ancestor chain traversal of a two-dimensional tree using offset value codes.

(5.) The sets of n keys are merged via the codeword lists.

Since there is a 1-to-1 correspondence between the nodes A.sub.i,j and in the tree of subtrees the nodes A.sub.q in the logical binary tree, the relationship between the tree of subtrees index pair (i,j) and the logical node index q can be calculated based on the following:

(a) Within a subtree i, enumerated as A.sub.i,1, A.sub.i,2, . . . , A.sub.i,L, the parent of A.sub.i,j is A.sub.i,j/2. Each level s, 0<s<k, is enumerated as {2.sup.s +p:p<2.sup.s }.

If A.sub.i,1 =A.sub.q, then

A.sub.i,j =A.sub.i,(2.spsb.s.sub.+p) =A.sub.2.spsb.s.sub.q+p, as the correspondence must preserve descendants.

(b) Let V be a subtree level. The number of subtrees on level V is ##EQU2## where: 2.sup.r =number of descendants of leaf nodes of root subtree

2.sup.k =number of descendants of leaf nodes of all other subtrees

The number of subtrees on levels 0-V is

The level of subtree i is

The number of subtrees on prior levels is:

If q.sub.0 =i-v.sub.i, (i is the q.sub.0 -th tree on level V.sub.i)

q.sub.1 =R+(v.sub.i -1)L

where q.sub.1 is the number of nodes on all prior subtree levels then,

the root of subtree i, A.sub.i,1 corresponds to A.sub.q, where: ##EQU3## For example, where 2048 records are to be sorted, N=2048

Lz=64

Cw=8

Then k=3

L=7

m=11

r=2

R=3

A.sub.45,3 =A.sub.q

Computing the logical index q for the node whose codeword is stored on the 4-th Cw multiple of subtree 45,

V.sub.i =3, since

1+4+4*8=37<45<1+4+4*8+4*8*8.

R+(4+4*8)*L=255=total number of nodes on all prior subtree levels

q.sub.0 =8

q.sub.1 =255

So q=263 and A.sub.45,1 =A.sub.263 and A.sub.45,3 =A.sub.45,2+1 =A.sub.263*2+1 =A.sub.527

Two examples of the 2-D computational advantages of the present invention are described in connection with FIG. 5.

Assume in the example that a sort is confined to 64 megabytes of main memory on a system with a 1-MB secondary cache (with 100 cycle miss penalty and 64-entry TLB) and 128-byte secondary cache line size. In the example, assume the sort consists of 1M records, and replacement selection has been adopted with offset-value coding, necessitating an 8 MB codeword tournament (or heap) tree. Log.sub.2 (N)=20, and with a conventional tree the lowest three level accesses (of the 20 comparisons in a traversal) will require main memory requests +TLB replacement+page table entry main memory request.

Assuming 25 cycle TLB penalty, the total is as follows:

With a two-dimensional structure, only the leaf subtree would miss, saving 500 cycles. Moreover, due to the economy of main memory accesses, the probabilistic pre-fetch can eliminate the remaining 225 cycles so that together in embodiments of the present invention 775 cycles are saved.

For a 100 Mhz processor, the savings is as follows:

This savings of 7.75 seconds is likely to be more than the total sort CPU time without cache misses. Moreover, a 32 MB/sec RAID device would only take 4 seconds total to read and write the file again demonstrating the significance of the savings in accordance with the present invention.

For Example II, the structure of Example I is used together with a 24k primary cache with 32-byte line size. Assume the keys are 8-digit octal numbers, so that there is a probability of 1/4096 of the first fullwords of two randomly chosen keys being found equal. Using a merge tournament sort with offset value coding, 3k codewords fit in the primary cache, so the algorithm which partitions the data into 3k quantities will not detect the equal codewords until the lists are merged. During the merge, the obligatory key access will entail the 225 cycle penalty mentioned in Example I. With a two-dimensional tree, a structure with 8k codewords is employed. Leaf subtree prefetching therefore eliminates most of the primary leaf misses, and the equal codewords with high probability will be detected during sorts of the respective partitions, with only secondary cache accesses necessary to retrieve the keys.

Note that the leaf subtrees of a common binary tree comprise half the nodes, whereas in the 2-D structure of the present invention (1/2+1/4+. . . +1/(2.sup.k)) nodes are contained in the leaf subtrees. In FIG. 5, for example, the leaf nodes in the leaf subtrees are those in subtree row 5 that include all the nodes in binary levels 20, 19, 18, and 17 (524,288+262,144+131,072+65,536).

A specific code listing useful in connection with the present invention appears in the attached APPENDIX A, KEY EXTRACTION FOR 2-D TOURNAMENT SORT and APPENDIX B, 2-DIMENSIONAL TOURNAMENT SORT WITH OFFSET VALUE CODING. A computer program including the code of APPENDIX A and APPENDIX B is executed in the FIG. 1 system first by doing the key extraction of APPENDIX A followed by execution of APPENDIX B. Key extraction is important for reducing the quantity of data that needs to be stored in higher speed cache internal storage. Also, for systems that do not provide for easy word boundary alignment, the key extraction routine is suitable for providing word boundary alignment of the information used in the actual sorting so that the speed of the sort process is materially increased.

In accordance with the above description, the present invention is a computer system including storage means in the form of internal storage 18 of FIG. 1 for storing a list of records R.sub.1, . . . , R.sub.N to be sorted where each record is associated with a corresponding one of the keys K.sub.1, . . . , K.sub.N, respectively, for ordering the records. A processing means such as processors 10 if FIG. 1 are for processing the records and keys and for controlling the storage means. The processing means includes computer software for forming a two-dimensional tree having a tree structure in said storage means formed of nodes including a single root node and a plurality of leaf nodes where each node except the root node is a child of exactly one parent node as shown in FIGS. 2-5 and wherein as shown in FIG. 2 the nodes form a logical tree having a binary tree structure where each node is a parent node of at most two child nodes. Also the two-dimensional tree as shown in FIG. 3 is organized into a tree structure of a plurality of subtrees, where each subtree is formed by a plurality of the nodes organized in a binary tree structure, and where for each particular node in a particular subtree that is the root node in the particular subtree, then said particular node has a parent node that is a leaf node in another subtree whereby said another subtree is the parent subtree of the particular subtree. In FIG. 3, the root subtree 31 is the parent of the leaf subtrees 41 to 44. The computer software of APPENDIX B includes software for storing codes representing keys into the nodes and sort software for performing a tree sort of said keys using the codes by accessing the codes in subtrees.

In accordance with the present invention, a two-dimensional merge tournament sort using offset-value coding provides increased efficiency on computers with multiple levels of storage access with hierarchical costs. Specifically, the two-dimensional structure a) increases cache locality of reference, reduces path length, and enhances pre-fetch logic; b) permits increased codeword length with allied subroutines to enhance the utility of registers as compared with prior implementations; c) employs tournament sort flags to increase low-cost branching paths; d) employs a merge routine which reduces costly secondary hierarchy penalties via pre-fetch logic; e) employs a fast stable sort (Appending Index) FIFO for equal keys.

In connection with the above, stored pointers used to reduce path length and cache lines are efficiently used by formation of natural subtrees so that ii.a) fewer cache lines are accessed per tournament tree traversal, and ii.b) probabilistic and direct pre-fetching of leaf subtrees is facilitated by increased cycles per cache line, resulting in fewer pre-fetches per unit of time.

In connection with the above, leaf subtrees comprise a higher percentage of nodes than leaf nodes of conventional binary tree structure and this condition permits larger trees with minimal secondary penalties.

The present invention usefully employs longer registers that are available with newer architectures and allows split comparison routines for registers 0 and 1 of a register pair that permits a high probability of faster execution.

Also the present invention requires fewer accesses to keys in remote storage due to codeword length.

The use of decremented counters for the equivalence with `infinity` or `automatic loser` reduces wasteful stores and tests.

Finally, potential penalties associated with key extraction are eliminated by cache-pre-fetch.

While the invention has been particularly shown and described with reference to preferred embodiments thereof it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. ##SPC1##