Method for Read Cycle Interrupts in a Dynamic Read-Only Memory

1. A method for clocking the read cycle of a memory to avoid address skew errors comprising the steps of: receiving a first one of a plurality of sample address control signals, (SMPA.), indicating an input address change; generating a primary clock signal, (START), in response to receipt of said first one of said sample address signals, (SMPA), said clock signal, (START), having a predetermined time duration; maintaining said primary clock signal, (START), active for a duration long enough to provide adequate precharge time for said memory given variations in supply voltage, temperature and manufacturing process variation and further to permit adequate discharge time for the address word line in said memory even when driven high in a previous memory cycle so that a precharge phase of said memory is begun; receiving a second one of said plurality of sample address signals, (SMPA); and continuing said precharge phase of said memory notwithstanding receipt of said second one of said sample address signals, (SMPA), by virtue of setting said primary clock signal, (START), signal high for said predetermined time period after receipt of each one of said plurality of sample address signals, (SMPA), whereby address skew errors are avoided.

2. The method of claim 1 where said step of generating said primary clock signal (START), signal further comprises the steps of setting a latch; generating secondary memory clock signals in response to setting of said latch; generating a trigger signal, (TRIG), when data within said memory can be read, said primary clock signal (START), signal having said duration of sufficient length such that said latch remains securely latched even if said second one of said sample address signals, (SMPA), is received during generation of said trigger signal, (TRIG), indicating that data in said memory is ready for output.

3. The method of claim 2 further comprising the step of floating data output signals from said memory if said second one of said sample address signals, (SMPA), is received during transition of data output signals from said memory from a previous read cycle.

4. The method of claim 1 further comprising the step of generating a plurality of secondary memory clock signals in response to generation of said primary clock signal, (START), said secondary memory clock signals being utilized within said memory to prepare said memory to read out an addressed location within said memory.

5. The method of claim 4 wherein said step of generating said primary clock signal (START), generates said primary; clock signal, (START), with a one shot multivibrator circuit, said primary clock signal, (START), being generated when an addressed interrupt occurs early within a memory read cycle, said primary, clock signal, (START), being restarted by said one shot multivibrator circuit to restart a new memory read cycle without switching said secondary clock signals except for those secondary clocks relating to new address inputs into said memory.

6. An improvement in a control circuit for generating clocks in a memory having a read cycle comprising: a one shot multivibrator or generating a (START) clock signal which goes active high at the beginning of a new read cycle; PCOK means for generating a clock signal, (PCOK), for causing said one shot multivibrator to reset said (START) clock signal low, said PCOK means for defining a predetermined duration of said (START) clock signal, said duration being of sufficient magnitude to permit adequate precharging of said memory and adequate discharge time for a word line in said memory core which is selected and was driven high in a previous memory cycle given changes in supply voltage, temperature and manufacture process variations; and secondary clock means for generating a plurality of secondary clock signals in response to said (START) clock signal, each of said secondary clock signals serving to time a precharge phase of said memory, wherein said secondary clock means comprises a latch means for generating one of said secondary clock signals, said latch means being set by said (START) clock signal and reset by a memory control signal, (TRIG), indicative of readiness of data within said memory to be output, said duration of said (START) clock signal generated by said one-shot multivibrator being sufficiently long to maintain said latch means set when a subsequent one of said sample address signals is received generating said (START) clock signal notwithstanding simultaneous receipt of said memory control signal, (TRIG), signal to reset said latch means when said subsequent one of said sample address signals is being received.