Integrated Dynamic Power Dissipation Control System for Very Large Scale Integrated (VLSI) Chips

1. Field of the Invention

The present invention is related to very large scale integrated circuit chips and more specifically to a method and apparatus for maintaining functional operation when chip temperatures exceed operating temperature specifications.

2. Prior Art

A notebook computer is a small, lightweight, portable, battery-powered, lap-top personal computer (PC) that uses a thin, lightweight, display screen such as a liquid crystal display (LCD). Notebook PCs typically run several hours on rechargeable batteries, weigh 4-7 pounds, fold up, and can be carried like a briefcase. Because of their small size and portability these small devices are often times exposed to environments where the temperature range for which the microprocessor chips were designed is greatly exceeded. This could lead to intermittent operation of the device and a shortened lifetime of the integrated circuit chips that make up the device's logical circuits.

Phase-locked loop (PLL) clocks are placed on integrated circuit chips to minimize clock delay skew between a board-level system clock and latches fabricated on the chip. The delay skew is created by the number of buffering levels needed on the chip to distribute the clock signal to all of the latches on the chip. PLL's can also change the frequency of the board level system clock so that the chip clock frequency is higher or lower than the board level system clock. It is well known that logical circuits consume power in proportion to the frequency at which they operate. The higher the operational frequency, the higher the power dissipation. By controlling the clock frequency to the logic, one can control the power dissipation.

It is therefore an object of this invention to provide a method and means for controlling the temperature of a very large scale integrated (VLSI) circuit chip by controlling phase locked loop (PLL) clock circuitry existing on the chip.

Briefly, the above object is accomplished in accordance with the invention by providing chip logic, a phase locked loop (PLL) clocking circuit, a temperature sensing circuit, and a power management circuit, all fabricated on a very large scale integrated (VLSI) circuit chip. The temperature sensing circuit directly measures the chip temperature, producing a temperature output signal. The power management circuit, which is connected to the temperature sensing circuit and to the chip logic, responds to the temperature output signal and to a functional state of the chip logic to generate a control signal to the PLL. The PLL responds to the control signal to change the operation of the PLL, by either stopping the clock or modifying the operating frequency thereof, depending upon the state of the control signal.

An advantage of this invention is that excessive system temperatures on a chip are regulated by controlling the effective duty cycle of a chip clock.

A further advantage of this invention is that it allows a device to operate at reduced system performance levels while temperatures at the chip level are being reduced.

A further advantage of this invention is that it allows a device to operate at above specified system performance levels when temperatures at the chip are below designated levels.

The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention as illustrated in the accompanying drawings.

FIG. 1 is a diagram of a prior art phase locked loop clock circuit;

FIG. 2 is a diagram of a system in which the present invention is embodied,

FIG. 3 is a flow diagram of a method of dynamically maintaining chip temperatures in accordance with the present invention;

FIG. 4 is a timing diagram of the operation of the invention in timed stop clock mode;

FIG. 5 is a timing diagram of the operation of the invention in a temperature controlled stop clock mode; and,

FIG. 6 is a timing diagram of the operation of the invention in a modify frequency mode.

FIG. 1 is a diagram of a prior art phase locked loop (PLL) clock circuit that is capable of frequency multiplication. An input signal (10) from a system clock is divided by a divide by P (/P) frequency divider (12). The PLL consists of a closed loop including a phase detector (16), a voltage controlled oscillator (VCO20), and a divide by N (/N) frequency divider (24). A phase difference and frequency difference between the signals (14) and (26) are detected in the phase detector (16) and an error signal (18) corresponding to the detected differences is output to the VCO (20). The VCO provides an output (22) that is phase-locked with the input signal(10). The /N frequency divider (24) divides the frequency of the signal (22) by N and feeds it back to the phase detector (16) so that the frequency is locked. The variables P and N of the frequency dividers can be programmed with values to provide a variable frequency output selected by the values of P and N. The /P circuit provides one pulse out for every P pulses applied. Likewise, the /N circuit provide one pulse out for every N pulses applied. The frequency out of the PLL is N*F/P, where F is the input frequency, and N and P are integers greater than zero and represent a frequency division of an applied signal.

Refer to FIG. 2 which is a diagram of a power dissipation control system in which the present invention is embodied. The power dissipation control system uses a phase locked loop (30) which is of the layout shown in FIG. 1. The PLL (30), a temperature sensor (32), a power management circuit (34), an AND circuit (36) and chip logic (38) are all fabricated on a very large scale integrated circuit (VLSI) chip. The temperature sensor (32) measures the chip temperature and generates a temperature monitoring signal (33) to the power management circuit (34). The chip logic (38) generates a chip status signal (46) to the power management circuit (34) that indicates the functional state of the chip logic. Using the temperature monitoring signal (33) and the chip status signal (46), the power management circuit determines if it is necessary to raise or lower the chip temperature. Two methods are available to the power management circuit for lowering the chip temperature. It can either stop the PLL clock for a period of time or it can reprogram the frequency divider circuits in the PLL.

Inhibiting the PLL output stops all chip logic stop functions so that no power is dissipated in the chip logic. Gating the output of the PLL with the AND (36) permits the PLL to continue operation and therefore provides a way to restart the chip clock waiting to wait for the PLL to regain lock.

Reprogramming the frequency divider circuits in the PLL to reduce the output frequency will reduce the power consumption in the chip logic. The chip logic will then function at lowered performance levels. The chip logic can also signal that it needs a higher frequency. In this case, the power management circuit can dynamically reprogram the frequency divider circuits in the PLL to increase the frequency, provided the power dissipation as measured by the temperature sensor is in an acceptable range. The chip logic will then function but at raised performance levels.

Refer now to FIG. 3 which is a flow diagram of a method of dynamically maintaining chip temperatures in accordance with the present invention. A temperature threshold level (T) is chosen for normal operation of the chip logic (52). The chip temperature is sensed (54). If the chip temperature (t) is greater than the threshold (T) the flow proceeds to decision block (58). The chip logic generates a chip status signal to the power management circuit that indicates that the chip is or is not in stop clock mode. If in stop clock mode, a yes from decision block (58) causes the flow to proceed to block (60) wherein the stop clock signal is asserted. When the temperature drops to the threshold (T) a yes occurs from decision block (62) and the stop clock signal is deasserted (64).

If at decision block (58) the chip logic did not signal stop clock mode, the flow proceeds to assert the divide by P signal to lower the PLL frequency. Reprogramming the frequency divider circuit in the PLL to reduce the frequency will change the effective duty cycle of the PLL and hence will reduce the power consumption in the chip logic.

The chip logic can also signal that it needs a higher frequency (70). In this case, the power management circuit can reprogram the divide by N frequency divider circuit in the PLL to increase the frequency, provided the power dissipation as measured by the temperature sensor is lower than the threshold (T). The chip logic will then function at raised performance levels.

Refer to FIG. 4 which is a timing diagram of the operation of the invention in timed stop clock mode. The system clock (10) of FIG. 2 is running at a frequency F in this example and the chip clock (37) is running at some fraction or multiple of the system clock frequency, 1/2 F*N/P, as described previously with respect to FIG. 1. The chip status signal line (46) of FIG. 2 indicates stop clock mode. The power management circuit (34) receives a signal (33) from the temperature sensor indicating that the temperature (t) is greater than a set threshold temperature (T). In response to the chip status signal (46) and the temperature signal (33) the power management circuit asserts the stop clock signal (44). This causes the chip clock to stop. Within the power management circuit is a timer function which deasserts the stop clock signal after a specified time period. The chip clock is gated from the AND (36) to the chip logic and operation of the chip logic resumes.

Refer to FIG. 5 which is a timing diagram of the operation of the invention in temperature controlled stop clock mode. The system clock (10) of FIG. 2 is running at a frequency F in this example and the chip clock (37) is running at some fraction or multiple of the system clock frequency, F*N/P, as described previously with reference to FIG. 1. The chip status signal line (46) of FIG. 2 indicates stop clock mode. The power management circuit (34) receives a signal (33) from the temperature sensor indicating the chip temperature (t) is greater than a set threshold temperature (T). In response to the chip status signal (46) and the temperature signal (33) the power management circuit asserts the stop clock signal (44). This causes the chip clock to stop. When the temperature (t) returns to the threshold temperature (T), the stop clock signal is deasserted by the power management circuit and the chip clock is ungated from the AND (36) to the chip logic and the operation of the chip logic resumes.

Refer to FIG. 6 which is a timing diagram of the operation of the invention in modify frequency mode. The system clock (10) of FIG. 2 is running at a frequency F in this example and the chip clock is running at some fraction or multiple of the system clock frequency, 1/2 F*N/P as described previously with respect to FIG. 1. The chip status signal line (46) of FIG. 2 indicates modify frequency mode. The power management circuit (34) receives a signal (33) from the temperature sensor indicating that the chips temperature (t) is greater than a set threshold temperature (T). In response to the chip status signal (46) and the temperature signal (33) the power management circuit asserts the stop clock signal (44). This causes the chip clock to stop. After the chip clock is stopped, the power management circuit asserts control signals /P (40) and /N (42). This reprograms the /P and /N frequency divider circuits to cause the chip PLL (30) to seek a lower frequency. The power management circuit waits for the clip PLL (30) to attain lock before deasserting the stop clock signal (44). The chip logic now operates at a reduced frequency. When the chip temperature (t) returns to the threshold temperature (T), the stop clock signal (44) is asserted by the power management circuit. This causes the chip clock to stop. After the chip clock is stopped, the power management circuit desserts control signals /P (40) and /N (42). This reprograms the /P and /N frequency divider circuits to cause the chip PLL (30) to seek a higher frequency. The power management circuit waits for the chip PLL (30) to attain lock before deasserting the stop clock signal (44). The chip logic now operates at a higher frequency.

Those skilled in the art will understand that the PLL as it is utilized in the preferred embodiment described above, can be replaced with any circuit capable of frequency multiplication or frequency division.

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made therein without departing from the scope of the invention.