Backplane Driver Circuit

The present invention relates generally to electronic circuitry and more particularly to a backplane driver for interfacing a digital circuit to a backplane.

A backplane, usually constructed as a printed circuit, is used in a computer to provide the required connections between logic, memory, and input/output modules. FIG. 1 schematically depicts a typical backplane circuit 10 comprising a main transmission line having a characteristic impedance of 50 .OMEGA. and a plurality of stubs (denoted "L1" through "L8") each having a characteristic impedance of 80 .OMEGA.. Eight circuit cards (not shown) may be coupled to the backplane via the eight stubs. The stubs in this example are positioned at intervals of one to two inches. The ends of the main transmission line are terminated with resistive loads. In practice, the backplane 10 is composed of generally similar conductive traces formed on a suitable substrate to form an N-bit wide bus, where N is determined by the computer architecture.

Any circuit coupled to the backplane 10 would employ a driver and/or receiver (or transceiver) as an interface between the circuit and the backplane. Transmit-only or output-only devices employ a driver whereas receive-only or input-only devices employ a receiver. Input/output devices employ a transceiver. The present invention particularly relates to a backplane driver, although it may be employed in a transceiver.

Digital computers and the like often include VLSI circuits which are interconnected for binary communications by a single segment or multi-segment transmission line. Drivers and receivers interface the VLSI components of such systems to the transmission line. The transmission line typically is formed by a microstrip trace or strip line having a characteristics impedance on the order of 50-70 .OMEGA.. A standard practice is to terminate the opposite ends of the main transmission line in its characteristic impedance. Thus, the output load on a driver for such a transmission line may be as low as 25 .OMEGA. to 40 .OMEGA. (i.e., the effective resistance of the parallel resistive terminations for the backplane).

The power internally dissipated by a driver is proportional to the nominal voltage swing of the binary signal it applies to the backplane and to the nominal low voltage limit of that signal (i.e., the logical "0" level). CMOS technology is attractive for fabricating VLSI circuits having relatively high gate densities, but the nominal 5 V rail-to-rail voltage swing (nominally, 0 V to 5 V) of standard CMOS circuits tends to cause the output drivers for such circuits to dissipate excessive power whenever the drivers are working into low impedance loads, such as a terminated transmission line of the above-described type. In recognition of that problem, voltage buffering drivers and voltage translating receivers for interfacing CMOS circuits to transmission lines have been proposed. Particularly, proposals have been made for carrying out binary communications at TTL (transistor-transistor logic) signal levels (nominally 0 V to 3.5 V), at PECL (positive emitter coupled logic) signal levels (nominally, 3.2 V to 4.2 V), and at BTL (backplane transistor logic) signal levels (nominally, 1.1 V to 2.0 V). PECL and BTL signaling dissipates less power than TTL signaling. However, PECL and BTL signaling are relatively difficult to implement in CMOS. TTL signaling is easier to implement in CMOS but, from a power dissipation standpoint, TTL signalling provides only a modest improvement over rail-to-rail CMOS signaling.

U.S. Pat. No. 5,023,488, Jun. 11, 1991, titled "Drivers and Receivers for Interfacing VLSI CMOS Circuits to Transmission Lines," discloses an N-channel CMOS driver and cascode CMOS receiver for interfacing VLSI CMOS circuits to transmission lines terminated by their characteristic impedances to voltage levels on the order of 1.2 to 2.0 V. These "GTL" (Gunning Transceiver Logic) drivers and receivers purportedly operate with a voltage swing on the order of about 0.8 V-1.4 V in carrying out binary communications between CMOS circuits configured to operate with standard 5 V rail-to-rail voltage swings for their internal signals. This patent discusses the use of GTL drivers and receivers with a transmission line terminated at its opposite ends, but not with a backplane having stubs connected to the main transmission line.

FIG. 2 schematically depicts how a GTL transceiver 12 would be coupled to a backplane 10 with stubs (the backplane 10 is not shown in FIG. 2). The GTL transceiver 12 comprises a GTL driver 14 and a GTL receiver 16. Supply voltages V.sub.DD and V.sub.SS are maintained on package pins 18 and 20, respectively. The GTL transceiver 12 is coupled to backplane 10 through a signal package pin 22, substrate via hole 24, stub 26, via 28, and connector 30. The stub 26 may be, e.g., a 1.5-inch, 80 .OMEGA. microstrip transmission line.

FIG. 3 is a simplified schematic diagram of the GTL driver 14. The driver 14 comprises an P-channel FET 14-1, N-channel FETs 14-2 through 14-5, inverters 14-6 and 14-7, a terminal ("DATAOUT") for receiving the signal to be output, and an output terminal or pin ("PAD"). This circuit provides an open drain output with feedback (transistors 14-4 and 14-5) to control inductive overshoot caused by quickly turning off transistor 14-3. The feedback is turned on when the output signal ("DATAOUT") switches to a high state, turning transistor 14-4 on while transistor 14-5 is already on. The feedback is intended to reduce the overshoot during a low to high transition on the signal output pin ("PAD"). Therefore, the feedback is left on only for a brief period. This period is determined by the propagation delay through inverters 14-6 and 14-7.

The present inventors have discovered that using the GTL driver in a backplane environment results in signal integrity problems when the output is switched from a low to a high state (as in FIGS. 5A and 5B, discussed below). Such problems are due to reflections resulting from mismatched impedances. (It should be noted that the GTL driver works well in an environment that has a main trace only with no stubs.) The standard GTL circuit attempts to address this signal integrity problem with a feedback path (transistors 14-4 and 14-5 in FIG. 3) that tends to turn the driver back on if the output goes above a certain voltage. This circuit is effective in controlling problems caused by the inductive effects that result from quickly turning off the output transistor (14-3 in FIG. 3). This is the primary cause of signal integrity problems in an environment with no stubs. However, in a backplane environment or any other environment with a main transmission lines and stubs of significant length, signal integrity problems will also be caused by reflections from the stubs. The standard GTL circuit is ineffective in this environment. The modified GTL driver circuit disclosed in this specification was developed to overcome this problem.

A backplane driver in accordance with the present invention comprises means for receiving a supply voltage (VDD); means for receiving a termination voltage (V.sub.term); means for receiving an output signal (DATAOUT) and in response thereto providing a drive signal to an output terminal (PAD); and means for temporarily clamping the voltage on the output terminal to approximately the termination voltage during a low to high transition of the output signal. In one preferred embodiment of the present invention, the driver comprises means for setting the driver output impedance to a high impedance state when the supply voltage (VDD) is turned off while the termination voltage (V.sub.term) is present. This embodiment also includes means for protecting the driver during hot insertion of the driver to a backplane. Other features of the present invention are disclosed below.

FIG. 1 schematically depicts a backplane of the type typically employed in a computer.

FIG. 2 schematically depicts how a GTL transceiver is coupled to a backplane of the type depicted in FIG. 1.

FIG. 3 is a simplified schematic diagram of a basic GTL driver.

FIG. 4 schematically depicts a backplane driver in accordance with the present invention.

FIGS. 5A through 5D depict waveforms representative of the performance of the basic GTL driver and the modified GTL driver in accordance with the present invention. In FIGS. 5B and 5D, multiple waveforms are depicted. These waveforms represent the voltage at the ends of stubs L1 through L8, as indicated on the righthand side of the respective plots. In each case, the driver is connected to stub L4. The other stubs are coupled to various other circuits, which are considered loads to the driver.

FIG. 4 depicts one preferred embodiment of a backplane driver in accordance with the present invention. This modified GTL backplane driver circuit is designated generally as 14', and an associated enable circuit is designated 40. The backplane driver circuit 14' comprises N- and P-channel FETs 14'-1 through 14'-11, where 14'-9 and 14'-11 each comprise two FETs connected as shown to form a transfer gate. In addition, the backplane driver circuit includes inverters 14'-15, 14'-17, and 14'-19. Except where otherwise indicated, all P substrates are tied to VDD and all N substrates are tied to VSS. This example differs from the standard GTL circuit in that the output is temporarily terminated or clamped to the termination supply voltage during a low to high transition. The termination is through transistor 14'-2 (an P-channel FET having its substrate connected to its drain and tied to V.sub.term). This termination is applied for a limited period of time, which period is determined by the delay through an inverter 14'-15 and a transfer gate 14'-11. Simulations have shown that this circuit is effective in reducing both the inductive effects of quickly turning the driver off and the effects of reflections due to the backplane stubs.

Another feature of the inventive driver circuit is that it is "hot insertable." This means that the driver can be plugged into or pulled out of a running system for maintenance without turning the system off. In order to accomplish this, the driver must be capable of going into a high impedance state when its supply voltage is turned off. The driver should also not exhibit any glitches or erratic behavior while its supply voltage is increasing, or ramping up. The circuit of FIG. 4 fulfills these requirements by providing an enable input that, when held low, ensures that the output stays in a high impedance state while the termination voltage is present, regardless of the value of the supply voltage (VDD). This also eliminates erratic behavior during any transients of the supply voltage. The external enable and V.sub.term pins facilitate glitch-free power up and ensure a high impedance at the input/output node ("PAD") when VDD is absent. This scheme requires that connections be made to ground and V.sub.term prior to connecting a GTL signal to the bus. The enable pin must also be connected to ground until the power and logic are stable. With the enable pin grounded, transistor 40-1 is off and the en.sub.-- n node is pulled up to V.sub.term by transistor 40-2. With en.sub.-- n pulled up, transistors 14'-1 and 14'-2 remain off. With transistor 14'-7 off, the gate of transistor 14'-2 is pulled up by transistor 14'-3, keeping transistor 14'-2 off as well.

The respective functions of the various elements of the circuit of FIG. 4 will now be summarized. Inverter 14'-19 serves as an input buffer. Transfer gate 14'-9 provides edge control, since the rate of change of the output voltage on the I/O pad is affected by how fast the output gate 14'-1 turns off. Transistor 14'-4 pulls down the gate of transistor 14'-1, which is used in the case of power transients. For example, this function is used for hot card insertion, where the card employs pins of different length so that ground is provided first and then V.sub.term. Inverter 14'-17 provides an output which follows the input signal "DATAOUT." This output drives transistor 14'-7 and inverter 14'-15. Inverter 14'-15 in combination with transfer gate 14'-11 provide a signal which drives the gate of transistor 14'-6. Ordinarily, transistors 14'-6 and 14'-7 are out of phase. That is, one of them is on when the other is off, and vice versa. However, due to the delay provided by inverter 14'-15 and transfer gate 14'-11, there is some period where transistors 14' -6 and 14'-7 are both on. This delay is adjustable by changing the geometry or resistance of the transistors making up the transfer gate 14'-11 and inverter 14'15. The transistor 14'-8 serves the same function with respect to transistor 14'-7 as transistor 14'-4 serves for output gate 14'-1. Transistor 14'-2 turns on when transistors 14'-6 and 14'-7 are both on, i.e., during the delay provided by inverter 14'-15 and transfer gate 14'-11. When transistor 14'-2 is on during this delay, the potential V.sub.term is connected to the I/O pad. In this manner, the I/O pad is "clamped" temporarily to V.sub.term. Finally, transistor 14'-3 ensures that transistor 14'-2 does not turn on during a power transition.

The waveforms depicted in FIGS. 5A and 5B represent the performance of an open drain driver without any feedback or clamping. The waveform of FIG. 5A is at the driver. FIG. 5B depicts a rising edge at the driver and each of the loads. These waveforms contain an overshoot above V.sub.term (1.2 volts) and resultant ringing due to the inductance of the interconnect. However, the negative excursion following the overshoot is greater in amplitude than the incident voltage due to the reflections from the stubs on the backplane. Therefore, in a backplane application where the stubs are of significant length or inductance, the driver must both clamp the overshoot and provide some termination for the reflections from the stubs.

The waveforms depicted in FIGS. 5C and 5D represent the results obtained with the inventive backplane driver depicted in FIG. 4. The waveform of FIG. 5C is at the driver and the waveforms of FIG. 5D are the rising edge at the driver and each of the loads. As these waveforms show, particularly when compared with the waveforms of FIGS. 5A and 5B, the backplane driver design of the present invention has eliminated the overshoot and reduced the effects of reflections from the stubs.

The basic GTL technology is attractive because it provides a fast driver capable of driving low impedance loads. The basic GTL driver also has a low voltage swing that reduces problems caused by cross-talk and switching current noise. For these reasons, GTL has been considered for use as a high speed signaling standard. It has also been considered by many IC vendors as a standard interface for their chips. However, the signal integrity problems discussed hereinabove have prompted the investigation of other alternatives. The present invention provides an ideal alternative to the basic GTL driver circuit.

It should also be noted that memory devices are typically packaged in SIMMs or SIPs plugged into a motherboard. This is identical to the backplane environment. Therefore, the present invention may be advantageously employed in connection with a motherboard environment.