Method of Forming Isolation Region in a Compound Semiconductor Substrate

The present invention relates, in general, to isolation regions in a semiconductor substrate, and more particularly, to isolation regions in a compound semiconductor substrate and methods of forming the isolation regions.

Generally, semiconductor device manufacturers fabricate many semiconductor devices within a single semiconductor substrate. Thus, a variety of techniques have been developed to electrically isolate one semiconductor device from another semiconductor device in the semiconductor substrate. For example, semiconductor devices manufactured in compound semiconductor substrates have used oxygen ion (O.sup.+) implants to make regions between active device regions electrically nonconductive. An important aspect in the isolation of compound semiconductor devices is the sequence of the semiconductor device fabrication steps. More particularly, fabrication steps using a self-aligned source/drain implant include forming a gate electrode in an active device region wherein the gate electrode extends over a field oxide to form a gate pad. Subsequently, a dopant is implanted into the active region to form the source/drain regions, followed by an anneal at a temperature of approximately 850.degree. C. Then, isolation regions are formed in the compound semiconductor substrate by implanting oxygen ions (O.sup.+) through the portions of the field oxide not covered by the gate electrode material and annealing the semiconductor substrate at a temperature of approximately 550.degree. C. Thus, conductive regions are implanted with oxygen ions and become non-conductive, thereby forming isolation regions.

A drawback of this technique is that the oxygen isolation implant must occur after the formation of the gate electrode to preclude degradation of the effectiveness of the isolation implant by the 850.degree. C. source/drain implant anneal. Since the region of the substrate under the gate electrode material in the field oxide region is not implanted with oxygen ions, it remains conductive. Thus, a capacitance is present between the gate pad and the substrate which degrades circuit speed and increases power consumption. In addition, connecting gates of different devices with a gate electrode material that is over the field oxide may result in semiconductor devices becoming shorted via the conductive region of the substrate under the gate electrode material. Another drawback is that separate anneals are required for the source/drain implant and for the isolation implant.

Accordingly, it would be advantageous to have a method of isolating regions in a compound semiconductor device that decreases a gate pad capacitance, reduces leakage currents, and reduces the number of processing steps required for fabricating the compound semiconductor device.

FIG. 1 illustrates a plan view of portions of a plurality of semiconductor devices in accordance with a first embodiment of the present invention;

FIGS. 2-4 illustrates highly enlarged cross-sectional views of the semiconductor devices taken along section line 2--2 of FIG. 1 during various processing steps in accordance with the first embodiment of the present invention;

FIG. 5 illustrates a highly enlarged cross-sectional view of a portion of one semiconductor device taken along section line 5--5 of FIG. 1;

FIGS. 6-8 illustrate highly enlarged cross-sectional views of a plurality of semiconductor devices fabricated in accordance with a second embodiment of the present invention; and

FIGS. 9-10 illustrate highly enlarged cross-sectional views of a plurality of semiconductor devices fabricated in accordance with a third embodiment of the present invention.

Generally, the present invention provides a method for electrically isolating monolithically integrated semiconductor devices in a compound semiconductor substrate from each other. The method of the present invention includes performing an isolation implant of, for example, oxygen ions (O.sup.+) prior to the formation of the gate electrodes and performing a single anneal step for both the isolation and the source/drain implants. Further, compound semiconductor devices having isolation regions fabricated in accordance with the present invention include isolation below the gate pads of the semiconductor devices.

FIG. 1 illustrates a plan view of portions of semiconductor devices 10 and 11 in accordance with a first embodiment of the present invention. Semiconductor devices 10 and 11 have active areas or regions 12 and 13, respectively, in which the active portions of semiconductor devices 10 and 11 are fabricated. Semiconductor device 10 is a field effect transistor (FET) and has source/drain regions 16, whereas semiconductor device 11 is also a FET and has source/drain regions 17. As those skilled in the art are aware, the source and drain regions of a field effect transistor are interchangeable, thus the regions are typically referred to as source/drain regions. Source/drain regions 16 and 17 are contacted by source/drain electrodes 18 and 19, respectively.

In addition, portions of control electrodes 21 and 22 are illustrated as being between and spaced apart from source/drain electrodes 18 and 19, respectively. More particularly, control electrode 21 is comprised of a first portion 23 and a second portion 24. Likewise, control electrode 22 is comprised of first and second portions 26 and 27, respectively. In the first embodiment, first portions 23 and 26 are over active areas 12 and 13, respectively, and second portions 24 and 27 are over portions of a field oxide 28. Control electrodes 21 and 22 serve as gate electrodes for FET's 10 and 11, and second portions 24 and 27 serve as gate contact pads. A particular advantage of the isolation regions of the present invention over those of the prior art is that gate contact pads 24 and 27 of the present invention are electrically isolated from a semiconductor substrate.

FIG. 2 illustrates a highly enlarged cross-sectional view of portions of semiconductor devices 10 and 11 during a processing step in accordance with the first embodiment of the present invention. The cross-sectional view of FIG. 2 is taken along section line 2--2 of FIG. 1. It shall be understood that the same reference numerals are used in the figures to denote the same elements. A compound semiconductor substrate 31 having a major surface 32 is provided. In the first embodiment, compound semiconductor substrate 31 is a III-V semiconductor substrate. Suitable materials for compound semiconductor substrate 31 include gallium arsenide (GaAs), indium phosphide (InP), aluminum gallium arsenide (Al.sub.x Ga.sub.(1-x) As), indium gallium arsenide (In.sub.x Ga.sub.(1-x) As), or a combination thereof. As those skilled in the art are aware, "x" is a number between zero and one. Semiconductor substrate 31 is covered with a surface protection material which serves as a surface protection layer 33. By way of example, surface protection layer 33 is titanium-tungsten-nitride (TiWN), and portions of surface protection layer 33 serve as first portions 23 and 26 of control electrodes 21 and 22, respectively, of FIG. 1.

FIG. 3 illustrates a highly enlarged cross-sectional view of the portions of semiconductor devices 10 and 11 further along in processing. Surface protection layer 33 is patterned using photolithographic and etch techniques well known to those skilled in the art to form a plurality of islands 34 and to expose portions of major surface 32. It shall be understood that surface protection layer 33 is removed from all areas of major surface 32 except over active areas 12 and 13, and that the plurality of islands 34 are metal. In addition to forming the plurality of islands 34, trenches 38 are formed between adjacent islands 34. The remaining portions of surface protection layer 33 shall be referred to as the plurality of islands 34 through the remainder of the description of the first embodiment.

A layer of insulating material 28 is conformally deposited over semiconductor substrate 31. Insulating material 28 covers the plurality of islands 34 and the exposed portions of major surface 32. As those skilled in the art are aware, layer of insulating material 28 is not planar. Accordingly, a planarization photoresist (not shown) is formed on layer of insulating material 28 using a planarization method well known to those skilled in the art. The planarization photoresist has a substantially planar photoresist surface. The planarization photoresist is etched back to the surface of layer of insulating material 28 on top of the plurality of islands 34. Thus, the planarization photoresist is removed from layer of insulating material 28 on the plurality of islands 34 but remains on layer of insulating material 28 on the portions of major surface 32 that were exposed when forming the plurality of islands 34. In particular, the surface of layer of insulating material 28 on the plurality of islands 34 and the surface of planarization photoresist remaining elsewhere are at about the same height. Using techniques well known to those skilled in the art the portions of layer of insulating material 28 on the plurality of islands 34 and the remaining portions of the layer of planarization photoresist are removed at the same rate, resulting in the exposure of the plurality of islands and insulating material 28 on major surface 32. By way of example, insulating material 28 on major surface 32 is oxide having a thickness of approximately 5000 angstroms, and is typically referred to as field oxide. It shall be understood that the surface of field oxide 28 is slightly lower than the surface of the plurality of islands 34.

An isolation implant mask layer 35 such as, for example, photoresist is formed on the plurality of islands 34 using photolithographic techniques well known to those skilled in the art. Isolation regions 37 are formed by implanting an ion selected from the group consisting of oxygen, boron, aluminum, nitrogen, and carbon into non-active device regions of compound semiconductor substrate 31. Preferably, isolation regions 37 surround active areas 12 and 13 and extend from major surface 32 into compound semiconductor substrate 31 a first distance. By way of example, isolation regions 37 are formed by implanting oxygen ions (O.sup.+) through field oxide 28. Subsequently, isolation implant mask layer 35 is removed. In a preferred embodiment, oxygen ions (O.sup.+) are implanted in a three step process. In the first step, oxygen ions (O.sup.+) are implanted at an energy of approximately 90 kilo-electron volts (KeV) and a dose of approximately 2.times.10.sup.14 ions per centimeter squared (cm.sup.2); in a second step the oxygen ions are implanted at an energy of approximately 180 KeV and a dose of approximately 2.times.10.sup.14 ions/cm.sup. 2 ; and in the third step oxygen ions are implanted at an energy of approximately 360 KeV and a dose of approximately 2.times.10.sup.14 ions/cm.sup.2. Using this dose and energy regime, the oxygen ions withstand subsequent source/drain anneals of, for example, approximately 850.degree. C. for approximately 6 seconds. Although a dose of approximately 2.times.10.sup.14 ions/cm.sup.2 has been specified, it shall be understood that a suitable range of doses is between approximately 1.times.10.sup.14 ions/cm.sup.2 and 1.times.10.sup.15 ions/cm.sup.2.

FIG. 4 illustrates a highly enlarged cross-sectional view of the portions of semiconductor devices 10 and 11 during a further processing step. A conductive layer 45 such as, for example, TiWN is deposited on the plurality of islands 34 and the field oxide 28. Conductive layer 45 and the plurality of islands 34 are patterned using lithographic and etch techniques well known to those skilled in the art to form control electrodes 21 and 22. More particularly, the plurality of islands 34 and portions of conductive layer 45 are patterned to form first portions 23 and 26 of control electrodes 21 and 22, respectively. In addition, conductive layer 45 is patterned to form second portions 24 and 27 of control electrodes 21 and 22, respectively, having first and second sides (FIG. 1). First portions 23 and 26 form gate electrodes for FET's 10 and 11, thus the regions of semiconductor substrate 31 below gate electrodes 23 and 26 serve as channel regions for the respective FET's 10 and 11. Preferably, gate electrodes 23 and 26 contact central portions of active device regions 12 and 13, respectively. However, it shall be understood that gate electrodes 23 and 26 may contact non-central portions of active device regions 12 and 13, i.e., gate electrodes 23 and 26 may be off-center in active device region 12 and 13, respectively.

A layer of insulating or dielectric material (not shown) such as, for example, silicon dioxide is deposited on gate electrodes 21 and 22, the portions of major surface 32 in active areas 12 and 13 between portions 23 and 26 of gate electrodes 21 and 22, respectively, and field oxide 28, respectively. Sidewall spacers 41 are formed adjacent portions 23 and 26 of gate electrodes 21 and 22, respectively, and adjacent field oxide regions 28 in active device regions 12 and 13 using a known anisotropic etch technique.

First, second, third, and fourth dopant regions 42, 43, 44, and 46, respectively, are formed using photolithographic and self-aligned implantation techniques known to those of skill in the art. More particularly, first dopant region 42 is formed on the first side of gate electrode 21 and second dopant region 43 is formed on the second side of gate electrode 21. Likewise, third dopant region 44 is formed on the first side of gate electrode 22 and fourth dopant region 46 is formed on the second side of gate electrode 22. Preferably, the distances of regions 42, 43, 44, and 46 into the compound semiconductor substrate from major surface 32 are substantially equal and are less than the distance of isolation regions 37 into compound semiconductor substrate 31 from major surface 32. For example, to form an N-channel FET 10, the impurity material of first and second dopant regions 42 and 43, respectively, is silicon, and to form a P-type FET, the impurity material of third and fourth dopant regions 44 and 46, respectively, is beryllium. Dopant regions 42 and 43 form source/drain regions and are illustrated as regions 16 in FIG. 1. Regions 44 and 46 also form source/drain regions and are illustrated as regions 17 in FIG. 1. In the first embodiment, FET's 10 and 11 are complementary compound semiconductor devices. Typically, the implants forming the source and drain regions are annealed at approximately 850.degree. C. for approximately 6 seconds. An insulating layer 47 such as, for example, silicon dioxide is deposited on gate electrode structures 21 and 22, exposed portions of major surface 32, field oxide 28, and sidewall spacers 41. Using techniques well known in the art, contact openings are formed in layer of insulating material 47 to expose portions of major surface 32 of doped regions 42, 43, 44, and 46. Source and drain electrodes 18 and 19, respectively, are formed by depositing a layer of conductive material such as, for example, NiGeW on layer of insulating material 47 and in the contact openings. Using techniques well known to those skilled in the art, the layer of conductive material is patterned, leaving only source and drain electrodes 18 and 19, respectively, in contact with the respective device regions 12 and 13.

FIG. 5 illustrates a cross-sectional view of a portion of one semiconductor device taken along section line 5--5 of FIG. 1. More particularly, FIG. 5 illustrates first and second portions 23 and 24, respectively, of control electrode structure 21 (FIG. 1). Second portion 24 is an extension of first portion 23 wherein second portion 24 extends over field oxide 28 having isolation regions 37 therebelow. Second portion 24 may serve as a gate pad for a FET. It should be noted that second portion 24 is over field oxide regions that are themselves over isolation regions 37. Thus, the original doping of compound semiconductor substrate 31 (whether intentional or unintentional) is made non-conductive and second portion 24, i.e., a gate pad, is electrically isolated from substrate 31. As a result, a capacitance between second portion 24 and substrate 31 is reduced or eliminated thereby improving performance of the FET. In addition, the present invention affords isolating active areas of different semiconductor devices when a control electrode structure of one semiconductor device is connected to a control electrode structure of another semiconductor device.

FIG. 6 illustrates a highly enlarged cross-sectional view of portions of semiconductor devices 55 and 60 during a processing step in accordance with a second embodiment of the present invention. What is shown is a compound semiconductor substrate 51 having a major surface 52 covered by a surface protection layer 53 such as, for example, silicon dioxide. Preferably, surface protection layer 53 has a thickness of approximately 5000 angstroms. An implant block mask is formed on surface protection layer 53 and patterned into a plurality of islands 54 which serve as isolation implant block masks. By way of example, the plurality of islands are photoresist which are patterned using techniques well known to those skilled in the art. The plurality of islands 54 are separated by openings 56 which expose portions of surface protection layer 53. In accordance with the preferred embodiment, isolations regions 57 are formed by implanting oxygen ions (O.sup.+) through openings 56 into regions of compound semiconductor substrate 51 in a three step process. In the first implant step, oxygen ions (O.sup.+) are implanted at an energy of approximately 90 keV and a dose of approximately 2.times.10.sup.14 ions/cm.sup.2 ; in a second implant step, oxygen ions are implanted at an energy of approximately 180 KeV and a dose of approximately 2.times.10.sup.14 ions/cm.sup.2 ; and in a third implant step, oxygen ions are implanted at an energy of approximately 360 KeV and a dose of approximately 2.times.10.sup.14 ions/cm.sup.2. Although a dose of approximately 2.times.10.sup.14 ions/cm.sup.2 has been specified, it shall be understood that a suitable range of doses is between approximately 1.times.10.sup.14 ions/cm.sup.2 or 1.times.10.sup.15 ions/cm.sup.2. It shall be further understood that the regions of semiconductor substrate 51 between isolation regions 57 serve as semiconductor device regions 58 and 59. Accordingly, semiconductor device region 58 is shown between two adjacent isolation regions 57 and a second semiconductor device region 59 is shown between two isolation regions 57.

FIG. 7 illustrates a cross-sectional view of portions of semiconductor devices 55 and 60 during a further processing step in accordance with the second embodiment of the present invention. Isolation implant block masks 54 are removed from surface protection layer 53. Openings 61 and 62 are formed in surface protection layer 53, wherein openings 61 and 62 expose portions of major surface 52 in first and second semiconductor device regions 58 and 59, respectively. Portions of major surface 52 above isolation regions 57 remain covered by portions of surface protection layer 53.

FIG. 8 illustrates a cross-sectional view of a portion of semiconductor devices 55 and 60 in yet a further process step in accordance with the second embodiment of the present invention. A control electrode material such as, for example, TiWN is deposited on the exposed portions of major surface 52 and on the remaining portions of surface protection layer 53, thereby filling openings 61 and 62. The control electrode material is etched to form gate electrodes 70 and 71. Although not shown, it shall be understood that gate electrodes 70 and 71 extend over a portion of surface protection layer 53. Accordingly, gate electrodes 70 and 71 form a gate electrode structure having a first portion in contact with major surface 52 and a second portion (not shown) extending over surface protection layer 53, wherein the first and second portions of gate electrodes 70 and 71 are analogous to first and second portions 23 and 24, respectively, of control electrode 21 and first and second portions 26 and 27, respectively, of control electrode 22 as shown in FIG. 1.

A layer of insulating material (not shown) such as, for example, silicon dioxide is deposited on gate electrodes 70 and 71, the exposed portions of major surface 52 in semiconductor device regions 58 and 59, and on surface protection layer 53. Sidewall spacers 63 are formed using an anisotropic etch technique well known to those skilled in the art.

First, second, third, and fourth dopant regions 66, 67, 68, and 69, respectively, are formed using photolithographic and self-aligned implantation techniques known to those of skill in the art. For example, to form an N-channel FET, the impurity material of first and second dopant regions 66 and 67, respectively, is silicon, and to form a P-channel FET, the impurity material of third and fourth dopant regions 68 and 69, respectively, is beryllium. Dopant regions 66 and 67 form source/drain regions which are analogous to regions 16 in FIG. 1 and dopant regions 68 and 69 form source/drain regions which are analogous to regions 17 in FIG. 1. Typically, the implants forming the source and drain regions are annealed at approximately 850.degree. C. for approximately 6 seconds.

An insulating layer 64 such as, for example, silicon dioxide is deposited on gate electrodes 70 and 71, exposed portions of major surface 52, the remaining portions of surface protection layer 53, and sidewall spacers 63. Contact openings are formed in layer of insulating material 64 to expose portions of major surface 52 of doped regions 66, 67, 68, and 69 using techniques well known to those skilled in the art. Source/drain electrodes 72 and source/drain electrodes 73 are formed by depositing a layer of conductive material such as, for example, NiGeW on layer of insulating material 64 and in the contact openings. Using techniques well known to those skilled in the art, the layer of conductive material is patterned, leaving only source and drain electrodes 72 and 73, respectively, in contact with the respective device regions 58 and 59.

FIG. 9 illustrates a cross-sectional view of portions of semiconductor devices 88 and 89 during a processing step in accordance with a third embodiment of the present invention. FIG. 9 shows a compound semiconductor substrate 81 having a major surface 82. A layer of dielectric material 83 is formed on major surface 82 and serves as a surface protection layer. Layer of dielectric material 83 is patterned using techniques well known in the art to form a plurality of openings (not shown) in layer of dielectric material 83 which expose portions of major surface 82. By way of example, layer of dielectric material 83 is silicon dioxide. More particularly, the openings expose first and second semiconductor device regions 85 and 86, respectively. An isolation implant block mask 84 such as, for example, photoresist is formed in the openings and covers the remaining portions of layer of dielectric material 83. Implant openings 80 are formed in the isolation implant block mask 84 to uncover the remaining portions of layer of dielectric material 83. In accordance with the preferred embodiment, isolation regions 87 are formed by implanting oxygen ions (O.sup.+) through implant openings 80 into regions of compound semiconductor substrate 81 in a three step process. In the first implant step, oxygen ions (O.sup.+) are implanted at an energy of approximately 90 keV and a dose of approximately 2.times.10.sup.14 ions/cm.sup.2, in a second implant step oxygen ions are implanted at an energy of approximately 180 KeV and a dose of approximately 2.times.10.sup.14 ions/cm.sup.2 and in a third implant step oxygen ions are implanted at an energy of approximately 360 KeV and a dose of approximately 2.times.10.sup.14 ions/cm.sup.2. Although a dose of approximately 2.times.10.sup.14 ions/cm.sup.2 has been specified, it shall be understood that a suitable range of doses is between approximately 1.times.10.sup.14 ions/cm.sup.2 or 1.times.10.sup.15 ions/cm.sup.2. It shall be further understood that the regions of semiconductor substrate 81 between isolation regions 87 serve as semiconductor device regions 85 and 86. Accordingly, first semiconductor device region 85 is shown between two adjacent isolation regions 87 and second semiconductor device region 86 is shown between two isolation regions 87. The isolation implant block mask 84 is removed, exposing major surface 82 in first and second semiconductor device regions 85 and 86, respectively.

FIG. 10 illustrates a cross-sectional view of the portions of semiconductor devices 88 and 89 further along in processing. A gate electrode material such as, for example, TiWN is deposited on the exposed portions of major surface 82 and on the remaining portions of surface protection layer 83. The gate electrode material is etched to form gate electrodes 90 and 91. Although not shown, it shall be understood that gate electrodes 90 and 91 extend over a portion of surface protection layer 83. Accordingly, gate electrodes 90 and 91 form gate electrode structures having first portions in contact with major surface 82 and second portions (not shown) extending over the remaining portions of surface protection layer 83, wherein the first and second portions of gate electrodes 90 and 91 are analogous to first and second portions 23 and 24, respectively, of control electrode 21 and first and second portions 26 and 27, respectively, of control electrode 22 as shown in FIG. 1.

A layer of insulating material (not shown) such as, for example, silicon dioxide is deposited on gate electrodes 90 and 91, the exposed portions of major surface 82 in semiconductor device regions 85 and 86, and on surface protection layer 83. Sidewall spacers 92 are formed using an anisotropic etch technique well known to those skilled in the art.

First, second, third, and fourth dopant regions 96, 97, 98, and 99, respectively, are formed using photolithographic and self-aligned implantation techniques known to those of skill in the art. For example, to form an N-type FET 88, the impurity material of first and second dopant regions 96 and 97, respectively, is silicon, and to form a P-type FET 89, the impurity material of third and fourth dopant regions 98 and 99, respectively, is beryllium. Dopant regions 96 and 97 form source/drain regions of FET 88 and are analogous to regions 16 in FIG. 1. Regions 98 and 99 form source/drain regions of FET 89 and are analogous to regions 17 in FIG. 1. Typically, the implants forming the source and drain regions are annealed at approximately 850.degree. C. for approximately 6 seconds.

An insulating layer 93 such as, for example, silicon dioxide is deposited on gate electrodes 90 and 91, exposed portions of major surface 82, surface protection layer 83, and sidewall spacers 92. Contact openings are formed in layer of insulating material 93 to expose portions of major surface 82 of doped regions 96, 97, 98, and 99 using techniques well known to those skilled in the art. Source/drain electrodes 94 and source/drain electrodes 95 are formed by depositing a layer of conductive material (not shown) such as, for example, NiGeW on layer of insulating material 93 and in the contact openings. Using techniques well known to those skilled in the art, the layer of conductive material is patterned, leaving only source/drain electrodes 94 in first semiconductor device region 85 and source/drain electrodes 95 in second semiconductor device region 86.

By now it should be appreciated that a method for forming isolation regions within a compound semiconductor substrate and a compound semiconductor device having the isolation regions has been provided. In the present invention, the original compound semiconductor substrate doping (whether intentional or unintentional) is made non-conductive by an ion implant, thereby forming isolation regions and isolating the gate pad from the compound semiconductor substrate. Accordingly, the gate pad to substrate capacitance is reduced. In addition, the active areas or regions of different compound semiconductor devices are isolated, one from another. Thus, control or gate electrode material may be used to interconnect many devices over a longer distance, allowing additional reduction of chip size and a higher device integration level with improved device performance. Also, the source/drain implant and the isolation implant anneal may be performed in a single step because the isolation is able to withstand the source/drain anneal temperature, without sacrificing the integrity of the isolation.