Apparatus and Method for Generting Negative Bias for Isolated MOSFET Gate-Drive Circuits

This invention relates to MOSFET gate drive circuits and in particular to isolated MOSFET gate drive circuits in which a negative gate bias is provided during the off time of the MOSFET to enhance its immunity to inadvertent turn-on.

A number of MOSFET gate-drive schemes utilize an active switch between gate and source to provide fast turn-off of the MOSFET. In these circuit arrangements, the gate is ordinarily clamped at zero volts with respect to the source, sometimes providing only 1.5 volts of margin against noise-induced MOSFET turn-on, depending on the actual threshold voltage of the device.

Noise susceptibility in high power MOSFET gate drive circuits becomes increasingly troublesome as switching speed and power level increase. High current switching paths and parasitic couplings superimpose spurious spikes into the gate drive circuits. Under certain conditions of polarity and amplitude, noise voltage pulses in the gate-drive circuit may be such that their effects combine to turn the MOSFET switches on at inappropriate times. Catastrophic circuit failure may then result.

A MOSFET gate drive includes circuitry to provide a negative gate bias during the off time of the MOSFET to enhance its immunity to inadvertent turn-on. The bias is generated by a self contained two terminal passive network which may be "floated" at any potential with respect to ground. This bias is automatically generated through the action of the network to the gate drive waveform, eliminating the need for an external bias supply to provide this voltage. Each bias supply is located locally, thus eliminating the need for long interconnects which may interfere with circuit operation. The bias network in one implementation is a combination of a capacitor and non-linear semiconductor device with a fixed voltage breakdown characteristic. This two-component implementation maintains the capability of producing systems with high packaging densities.

FIG. 1 is a schematic of a prior art isolated gate-drive circuit using a bipolar transistor;

FIG. 2 is a schematic of a gate drive circuit using a MOSFET for driving a power MOSFET switch;

FIG. 3 is a schematic of a gall driver circuit for driving a power MOSFET switch and including a negative bias source in the drive circuit; and

FIG. 4 is a schematic of a practical gall driver circuit driving a power MOSFET switch and including a negative bias source in the drive circuit.

An example of a prior art gate-drive circuit for driving a power MOSFET is shown in FIG. 1 and utilizes an active switch Q2 to clamp the gate of the power MOSFET to the return lead of the source voltage provided by the secondary winding of drive transformer T1. This arrangement is susceptible to the ringing occurring during clamping which may cause spurious turn-on of the power MOSFET. No negative bias source is included to counteract ringing.

Another gate-drive circuit clamping the gate to zero volts without negative bias was disclosed in the copending application disclosing a "High Performance Isolated Gate-Drive Structure for MOSFET Power Switches" by K. J. Timm, and having Ser. No. 081,278,474, filed on, Jul. 20, 1994, is shown in FIG. 2. In FIG. 2, the drive signal applied to the isolation transformer T1 is a rectangular, bipolar waveform, and has an amplitude of typically 12 to 15 V. This signal is derived from a low impedance source, e.g. totem-pole connected MOSFETs. To maintain low impedance it is desirable to have tight coupling between the primary and secondary circuits. This can be accomplished with a unity turns ratio transformer and bifflax windings, if permissible. The drive waveform can be divided into three distinct regions: A first region has a positive polarity with an amplitude of +Vpk corresponding to Q1 being "on". A second region has a negative polarity with amplitude of -Vpk corresponding to Q1 being "off" and the gall-source impedance held low. A third region has a zero amplitude or "dead- time" occurring between the first and second regions and during which dead time Q1 must be "off". Dead-time is added to ensure that destructive simultaneous (overlap) conduction between the upper (high-side) MOSFET(s) and low-side MOSFET(s), in a half or full-bridge converter topology will not occur.

The drive MOSFET Q2 exhibits high transconductance (gm) for all operational conditions, draws no steady stall gate current and imposes a minimum load on the gate driver circuits. It is therefore able to support large drain currents without incurring the base current load penalty imposed by bipolar transistor devices.

With positive voltage at the dotted ends of the transformer T1, a pulse of current flows in the gate circuit loop. This loop consists of the secondary of T1, the gate input capacitance of Q1 (Cin1) and diode CR1. Cinl is charged to +Vpk turning power MOSFET Q1 "on" when Vgs(th) is reached. At this point drive MOSFET Q2 is effectively out of the circuit.

During the dead-time interval, which may be as little as 100nS, power MOSFET Q1 is required to be "off". Capacitor Cin1 enters this time period with an initial voltage of +Vpk. When the transformer secondary voltage drops to zero at the beginning of the dead-time interval, the voltage on capacitor Cin1 causes charge to be transferred to capacitor Cin2. By design Cin1>>Cin2, so, while charge is shared between the two capacitors, there is little voltage droop and drive MOSFET Q2 turns "on" strongly. Since drive MOSFET Q2's discharge path bypasses the leakage reactance of T1, the gate voltage of power MOSFET Q1 falls very rapidly. The negative bias supply ensures that, during the dead-band period, MOSFET Q1 is turned off well before Q2 discharges its source of positive voltage, (Vbias plus the voltage on Cin1).

An improved gate drive circuit incorporating the principle of this invention is shown in FIG. 3. The improvement consists of the parallel combination of a nonlinear breakdown diode (i.e. zener diode) CR4 and a capacitor C1. With the addition of the parallel combination, assuming an N-channel power MOSFET for Q1, a negative dc voltage is applied between gate and source of the switch providing an additional degree of protection against inadvertent turn-on of the power MOSFET. In this case the noise spike would have to overcome the magnitude of the negative bias as well as attain the gate-source threshold voltage before the MOSFET can be commutated on. The introduced negative bias provides a substantial degree of protection not present by merely attempting to hold the gate at zero volts.

An enhanced version of the drive circuit for practical applications is shown in FIG. 4. The circuit is enhanced by the inclusion of R2, CR3 and R3. In this drive circuit a pulse of current flows in the loop consisting of C1, CR2, T1 secondary, R3 and the gate input capacitance of Q1 (Cin1). This current sets up a voltage across C1 equal to the voltage of a zener diode CR4. The charge on C1 is refreshed at the gate switching rate and, if C1 is large enough, there will be only a small amount of voltage droop caused by charge redistribution between C1 and other circuit capacitances. When the polarity at the transformer dots is negative, Q2 will turn on, providing a low impedance between the gate and the bias supply. The gate-source voltage of Q1 will thus be negative and equal to the bias present on C1 (set by the zener diode CR4).

While a specific example has been shown, the zener diode and capacitor negative bias generator can be added to other gate-drive circuits such as the scheme shown in FIG. 1. Various combinations will suggest themselves to those skilled in the art without departing from the spirit and scope of the invention.