Method for Controlling Clock Frequency of a Digital Logic Semiconductor According to Temperature

Digital logic semiconductor components (microcontrollers, for example) are used in many different applications--for instance, to control peripheral devices. These logic semiconductor components--frequently operated in cyclic mode--will usually need to meet very special requirements, depending on their relevant operating environment. In particular, temperature plays an important part here, as specific components will be selected, inter alia, according to their maximum permissible environmental temperature as specified by the customer; therefore, in applications where high temperature requirements are specified, or where environmental temperature conditions vary greatly--as is the case, e.g., in motor vehicle engineering applications--, specially optimized and costly components must be used for such applications.

However, high environmental temperatures usually occur only under extreme environmental conditions, and then only for a very brief period during the entire working life of the devices controlled by such logic semiconductor components; that is, the use of "high temperature" components cannot be justified from an economic and cost-effectiveness point of view.

The object of the invention is a method which enables the temperature range for the use of conventional logic semiconductor components to be significantly extended.

The above object is achieved according to the present invention by a method for operating a digital logic semiconductor component, wherein: a logic semiconductor component which may be operated in several operational modes M at fixed clock cycles depending on environmental temperature (T.sub.U), and with each operational mode (M) being allocated a clock cycle (TA) with a different clock frequency (f), is provided; each operational mode (M) is allocated a temperature dependent limit value and for each value a respective different limit temperature (T.sub.G), which when reached causes a change in the operational mode (M); and the clock frequency (f) is reduced when changing to an operational mode (M) with an increased limit temperature (T.sub.G), and increased when changing to an operational mode (M) with a lower limit temperature (T.sub.G). Further advantageous applications and features of this method are likewise disclosed.

The method presented here will define several different operational modes M for a digital logic semiconductor component: each operational mode M will be allocated a processor clock cycle TA with a specific clock frequency f and a limit temperature T.sub.G ; when this temperature T.sub.G is reached, the operational mode M will change. In operational modes M with a higher limit temperature T.sub.G --or, which is the same, with a higher permissible environmental temperature T.sub.U --, the functional range of the computing program or software will be reduced; as this reduction of the functional range will lead to shorter program run times, clock frequency f in operational modes with higher permissible environmental temperatures T.sub.U can be reduced--to such an extent, in particular, that program run times will return to their original values. Limit temperatures T.sub.G for the operational modes M will be determined by the relevant specified or preselected clock frequency f, as the permissible environmental temperature T.sub.U for the logic semiconductor component, and thus also the limit temperature T.sub.G, for each operational mode M will be dependent on power dissipation P.sub.V ; this again will be dependent on clock frequency f. For a linear relationship between power dissipation P.sub.V and clock frequency f, the following will apply:

where a and b will be constants dependent on the manufacturing process of this semiconductor component.

For a given thermal contact resistance R.sub.th and a given maximum junction temperature T.sub.S of the logic semiconductor component, a relationship between maximum permissible environmental temperature T.sub.U and power dissipation P.sub.V can be stated as follows:

Equation (1) thus yields a linear relationship between maximum permissible environmental temperature T.sub.U and clock frequency f:

For limit temperature T.sub. (T.sub.G .ltoreq.T.sub.U), this will yield the relation:

Equations (1) to (3) show that reducing clock frequency f will lead to a significant reduction of power dissipation P.sub.V and thus a significantly higher permissible environmental temperature T.sub.U for the logic component. For a given clock frequency f, limit temperature T.sub.G may be selected within the range determined by equation (4); for a given permissible environmental temperature T.sub.U, this limit temperature T.sub.G will preferably be selected as the maximum possible temperature (T.sub.G =T.sub.U).

Reducing the clock frequency, and thus the power dissipation, will increase the maximum permissible environmental temperature for logic semiconductor components; even for high temperature requirements, therefore, cost-effective conventional logic semiconductor components may be used. No specialist specifications will be required. Furthermore, reducing power dissipation for a given environmental temperature enables the junction temperature to be decreased and thus a significant increase in the life of these logic semiconductor components.

The method presented here will hereinafter be further explained using the enclosed drawing. FIG. 1 shows a block diagram containing all components necessary for operating the logic semiconductor component, and FIG. 2 shows a timing diagram to illustrate mode switching.

As shown in FIG. 1, oscillator 3 which generates processor clock cycle TA will apply clock signal TS via circuitry 2 to the digital logic semiconductor component 1 controlling devices 4. The logic semiconductor component 1 may be operated in two operational modes M: a normal mode M.sub.N with full functional range and normal (operational) clock frequency f.sub.N, and a high temperature mode M.sub.H with reduced functional range and reduced clock frequency f.sub.H.

When the limit temperature is reached, switching signal US generated by the logic semiconductor component 1 will cause oscillator 3--by means of circuitry 2--to switch over from clock cycle TA.sub.N with the higher "normal" clock frequency f.sub.N (normal operation) to clock cycle TA.sub.H with reduced "high temperature" clock frequency f.sub.H (high temperature operation). Circuitry 2 will coordinate ramp synchronous switching over between clock cycle TA.sub.N and clock cycle TA.sub.H : according to FIG. 2, switching signal US given at time t.sub.1 will only have an effect on clock cycle TA at time t.sub.2, as both clock cycles TA.sub.N and TA.sub.H will be ramp synchronous at this point. In an example embodiment--a microprocessor-controlled gear transmission system in a motor vehicle--, and for a maximum permissible environmental temperature of 150.degree. C., the following will apply: when a limit temperature T.sub.G of 125.degree. C. is exceeded, switch-over from normal mode M.sub.N with a clock frequency f.sub.N =40 MHZ to high temperature mode M.sub.H with a clock frequency f.sub.H =20 MHZ will occur.