US 5,479,577 AGrant
Neural Device
Issue Date:1995-12-26
•3 Claims
•2 Drawing Sheets
Abstract
A large scale integrated neural device has a number of processor elements, each with a number of input lines and a single output line. The neural device also has a local bus with a number of conductors. Each conductor receives one of the output lines from each processor. Any input line of any processor element may be connected to any bus conductor through a switch element. Each processor element generates, as an output, an integrated result of weighted input signals. The switch element ON/OFF state may be programmed from external signals.
Metadata
Assignee
- Ezel Inc.
Inventor
- Weikang Yang
Application Information
Application Number:US 2756552
Filing Date:1994-07-15
Priority Date:1992-03-06
Art Unit:239
Classifications
IPC:
G06F 1580
Field of Search:
39524;27
Patent Drawings (2 sheets)
Description
Field of the Invention
This invention relates to a neural network device, especially to one comprising multiple processor elements which output weighted integrated results of a signal input from an input line which connects these processor elements through a local bus.
Background of the Invention
When electronic hardware is used to realize a neural network, the amount of information communicated among processor elements increases, especially when a high degree of parallel processing is applied with the large number of processor elements. In this case, communication delays become large.
On the other hand; in order to accelerate communication while maintaining the degree of parallel processing, it is conceivable that multiple processor elements may be formed in a single LSI. However, that single LSI cannot comply a large portion of a network because the conditions are fixed between processor elements in LSI.
Summary of the Invention
This invention solves the above mentioned conventional problems, and has an object to provide a neural device that is able to adapt to a composition of wide neural network while setting multiple processor elements in a LSI.
The neural device relating to this invention sets a local bus in a LSI: the local bus sets multiple conductors Lc arranged in parallel corresponding to the output line of each processor element, connects one of the output lines to each conductor, and connects all the input lines of each processor element to each conductor through the switch element.
According to the above description of this invention, it is possible to adapt to the wide neural network while setting a plural number of processor elements in a LSI.
Brief Description of the Drawings
FIG. 1 is a block diagram showing an embodiment of neural device relating to this invention;
FIG. 2 is a block diagram showing details of switch element in the embodiment in FIG. 1; and
FIG. 3 is a block diagram showing another embodiment of switch element.
Preferred Embodiment of the Present Invention
Hereinafter, an embodiment of a neural device according to this invention is explained with reference to the attached drawings.
The neural device multiple processor elements PE are connected through local bus B, as shown in FIG. 1.
Processor element PE has a number of input lines Li and a single output line Lo. The processor element integrates input data from input lines Li to generate the output signal. This integration is accomplished by multiplying input data by weights and transforming the result according to a predetermined function. Sigmoid function S<> can be used, giving the processing element the following function:
Y=S<.SIGMA.XiWi+.theta.
Y: output
Xi: i-th input
Wi: i-th weight
.theta.: offset
Output line Lo of each processor element PE is connected with one of the conductors in local bus B. The output signal may be input through the conductor into the other processor elements, input lines of each processor element PE may be connected to any conductors Lc through switch elements SW according to an ON/OFF state of the switch elements.
FIG. 2 shows that a switch element SW has transistor T whose gate G is connected to a reference voltage and to a fuse F for grounding the gate. The switch element SW turns off while this fuse F connects the gate to ground. At the beginning, the LSI is fabricated with fuse F connecting the gate to ground. There are several methods for blowing a fuse. One of them connects a power source Sb with fuse F. Another impresses a negative voltage -V on conductor Lc, which in turn leads electric current from gate G of a transistor.
By controlling the switch element ON/OFF state, each processor element PE may be set as intended. The ON/OFF state is controlled by a status signal from a source external to the LSI. A status signal is once registered in an LSI and fuse F is fused according to the status signal after the status signal has been registered.
FIG. 3 shows another embodiment of switch element SW. Each switch element SW.sub.n connects the output Mo memory cell Mn to a gate G of a transistor T. Each switch element SW.sub.n is ON when the output Mo of memory cell Mn at a high level. A status signal is input to memory cell M.sub.n from outside of the LSI, and an output for each switch element is set according to this status signal. By storing a status signal in a memory cell, the connectedness of each processor element can be changed as desired.
A neural device relating to this invention has a local bus in a LSI. The local bus has a number of conductors Lc arranged in parallel. The output line of each processor element connects to one bus conductor. Any input lines of any processor element may be connected to any bus conductor through the switch elements. Therefore, the neural device may be adapted to a wide variety of neural structures, as well as incorporating a number of processor elements in a single LSI.
Claims
What is claimed is:
1. A neural device comprising: a plurality of processor elements for processing input signals and generating an output signal responsive to said processing, each processor element including a plurality of input lines and an output line; a local bus having a plurality of conductors, each conductor being connected to one of said processor element output lines; and a plurality of switch elements, each switch element selectively connecting a local bus conductor to one of said processor element input lines, said switch elements defining network connectivity; where each said switch element comprises a transistor having a gate for receiving a first voltage and a fuse for connecting said gate to a second voltage, where said transistor is set to an OFF state when an externally-generated status signal changes said fuse to an open state, and where said processor element generates an output based on integrated weighted signals which are input from said input lines, and said switch elements switch ON or OFF in accordance with said status signal, said network connectivity being reconfigured based on said switching of said switch elements.
2. A neural device as in claim 1 wherein said status signal changes the fuse to an open state by connecting a power source to said fuse.
3. A neural device as in claim 1 wherein said status signal changes the fuse to an open state by impressing a negative voltage on an emitter of the transistor through a local bus conductor.
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