Double Scan Circuit for Inserting a New Scan Line Between Adjacent Scan Lines of a Television

The present invention relates to a double scan circuit, and more particularly, to a double scan circuit for inserting a new scan line obtained by interpolating adjacent interlacing scan lines into the space between lines and scanning the lines at double speed in a television.

A double scan method is generally used to maintain the resolution of an image when the screen size of a television set is increased. According to the double scan method, a television repeatedly scans the respective pixels of the screen (or the respective points on the scan line) with the same image information, so as to improve the visibility of the screen.

An example of a conventional technology for double scanning is shown in FIG. 1, showing the constitution of the technology currently used. For double scanning, the speed for a reading operation must be twice that for a writing operation. First-in-first-out (FIFO) line memories are generally used to accomplish this.

When scanning using a FIFO line memory, the reading speed must be twice the writing speed. For this, first and second FIFO line memories 102 and 103 are controlled by a write controller 101 and a read controller 105.

Write controller 101 counts the pulses of the write clock and produces a write address signal for first and second FIFO line memories 102 and 103. Read controller 105 counts the pulses of the read clock and produces a read address signal for first and second FIFO line memories 102 and 103.

In accordance with a write starting pulse and the write clock generated from write controller 101, the real line data (original line data) is input to the first FIFO line memory 102. Also, the interpolated line data is input to the second FIFO line memory 103. The data input to the first and second FIFO line memories 102 and 103 is read out in accordance with the control of read controller 105.

In other words, when reading out the data recorded in the first and the second FIFO line memories 102 and 103, control is performed by read controller 105 and is independent of the write control. Read controller 105 generates a read starting pulse according to the read clock whose frequency is double that for write control, and applies it to first and second FIFO line memories 102 and 103. Read controller 105 reads out the original data of first FIFO line memories 102 and the interpolated data of second FIFO line memories 103, in the same order as that for recording and outputs them to a multiplexer 104. Multiplexer 104 selects alternatively the outputs of first FIFO line memory 102 and second FIFO line memory 103 in accordance with the selection control signal applied to the selection control port (S) thereof and outputs the selected output as double scan data.

On the other hand, when using a double scan circuit in an image apparatus circuit, the circuit should be integrated into a single chip for easy application and cost reduction. For this, the double scan circuit should have a constitution suitable for integration, such as in the case of VLSI circuits. However, as shown in FIG. 1, in the conventional technology, the circuit for controlling FIFO line memories is complex and a large number of memory cells is required for incorporating FIFO-type line memories within a chip, which leads to a problem for VLSI implementation.

Meanwhile, U.S. Pat. No. 5,177,609 discloses an image processing system for performing a time-based compression of an image and sampling the compressed image at double speed. Also, U.S. Pat. No. 5,115,312 discloses a circuit for sequentially scanning an interpolated chrominance signal (or its luminance signal) and an original chrominance signal (or its luminance signal) at double speed, using line memories in the double scan circuit of a television.

It is an object of the present invention to provide a circuit for solving the above problems.

It is another object of the present invention to provide a double scan circuit for inserting a new scan line obtained by interpolating the interlaced scan signals between the original signal lines and then sequentially scanning, line by line, in order to prevent image quality deterioration in a large screen.

It is still another object of the present invention to provide a circuit for performing double scanning, using a general random access memory (RAM) chip.

To attain the above objects of the present invention, there is provided a double scan circuit comprising:

a first data generator for generating real line data;

a second data generator for generating interpolated line data by line-interpolating an interlaced scanning signal and;

a controller for generating a control signal for discriminating between the real line data and the interpolated line data every horizontal line period, a write clock having a predetermined frequency, and a read clock whose frequency is 2m times the frequency of the write clock;

a first data converter for converting n-bit real line data into 2n-bit real line data;

a second data converter for converting n-bit interpolated line data into 2n-bit interpolated line data;

a first memory for storing the converted real line data, and reading out the stored data in accordance with the read clock;

a second memory for storing the converted interpolated line data, and reading out the stored data in accordance with the write clock;

a memory controller for generating a read/write control signal for the first and second memories, a write address and a read address being 2m times the speed of that for the write address, in accordance with the real/interpolated line control signal and the write clock, for applying them to the first and second memories, and for generating a mixing control signal for mixing the original line data with the interpolated line data stored in the first and second memories for double scanning; and

a double scan data generator for selecting one between the 2n-bit real line data and the 2n-bit interpolated line data in accordance with the mixing control signal and real/interpolated line control signal and for producing the selected one as n-bit double scan data.

The above objects and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which:

FIG. 1 is a block diagram of a conventional double scan circuit;

FIG. 2 is a circuit diagram of a double scan circuit according to one embodiment of the present invention;

FIG. 3 is a detailed circuit diagram of the memory controller shown in FIG. 2; and

FIGS. 4A-4U constitute a timing diagram for the memory controller shown in FIG. 3.

In FIG. 2, a real/interpolated line control signal (R/I) and a write clock (WC) of a system controller 200 are connected to a memory controller 201. A first address output port (RADDR) and a first control signal output port (RRW) of memory controller 201 are coupled to a first RAM 204. A second address output port (IADDR) and a second control signal output port (IRW) of memory controller 201 are coupled to a second RAM 205.

The input of a first data converter 202 is coupled to the output of a real data generator 209, and an output port RD thereof is coupled to first RAM 204. The input of a second data converter 203 is coupled to the output of an interpolated data generator 210, and an output port ID thereof is coupled to second RAM 205. A read clock (RC) output port of system controller 200 is coupled to first and second RAMs 204 and 205.

In a double scan data generator 206 constituted by a multiplexer, first and second data input ports I0 and I1 thereof are coupled to second RAM 205, third and fourth data input ports I2 and I3 are coupled to first RAM 204, a first selection control port S0 is coupled to an MSB/LSB signal output port of memory controller 201, a second selection control port S1 is coupled via a delay 207 and an inverter 208, to the R/I output of system controller 200, and sequential data (Dout) is produced at double speed through an output port thereof.

The operation of the circuit shown in FIG. 2 is as follows.

Referring to FIG. 2, memory controller 201 is a block for generating memory control signals (IRW and RRW) and address signals (IADDR and RADDR) for controlling first and second RAMs 204 and 205 as double scan memories, and a selection control signal for controlling the selection of multiplexer 206. The detailed composition and operation of memory controller 201 will be explained later, referring to FIG. 3.

For the currently input original real line data (hereinafter called "real data") and interpolated line data (hereinafter called "interpolated data"), first and second data converters 202 and 203 convert the existing 8-bit data into 16-bit data for securing a sufficient timing margin (the timing margin for proper memory operation). The converted data of first data converter 202 is written into first RAM 204 by control signal RRW and address signal RADDR generated in memory controller 201, and the data written into first RAM 204 is read out. The converted data of second data converter 203 is written into second RAM 205 by control signal IRW and address signal IADDR generated in memory controller 201, and the data written into second RAM 205 is read out.

At this time, the write frequency is 7.16 MHz (2 fsc), which allows for memory processing such that no timing problems exist in the operation of first and second RAMs 204 and 205. In addition, the read speed of first and second RAMs 204 and 205 is made double the write speed by the control of memory controller 201, so that 16-bit data is read out from first and second RAMs 204 and 205 at the speed corresponding to 14.3 MHz (i.e., 4 fsc, or double the write frequency).

Also, in the embodiment of the present invention, the timing for RAM operation should be about 30 nanoseconds or more. For processing 8-bit data without any data conversion in first and second data converters 202 and 203, the read speed of first and second RAMs 204 and 205 is 8 fsc. (Here, since 8 fsc timing is shorter than 30 nanoseconds, the RAM cannot operate properly.) Accordingly, first and second data converters 202 and 203 convert the 8-bit real and interpolated data into 16-bit real and interpolated data, in order to maintain the minimum securable operating margin for RAMs 204 and 205.

The real/interpolated line control signal input through the R/I port to memory controller 201 is generated for every line (or 1 H) in the real video signal and is a signal for discriminating between the processing intervals of the real data and the interpolated data. The real/interpolated line control signal is input through a delay 207 and an inverter 208 to second selection control port S1 of multiplexer 206.

To convert an original 1 H period of a video signal from the interlacing scanning type into the sequential scanning type, multiplexer 206 must scan and output data of two lines per 1 H period. In other words, multiplexer 206 receives the second selection control signal and the first selection signal output from the MSB/LSB port of memory controller 201, and converts the 16-bit data read out from first and second RAMs 204 and 205 into 8-bit data, and then produces the double scan data.

FIG. 3 is a detailed circuit diagram of the memory controller 201 shown in FIG. 2.

In FIG. 3, the data input port of a first D flip-flop (F/F) 211 is coupled to the real/interpolated line control signal input port (R/I) of memory controller 201. The Q output of first D flip-flop 211 is coupled to the data inputs of second and third D flip-flops 212 and 215 and to a first input of each of an XNOR gate 213 and a NAND gate 216. The write clock port (WC) of memory controller 201 is coupled to the clock ports of first and second D flip-flops 211 and 212 and first and second counters 217 and 220, to a first input of each of first and second AND gates 219 and 220, and to the input of an inverter 214. A second input of XNOR gate 213 is coupled to the Q output of second D flip-flop 212 and the output thereof is coupled to the load (LD) control signal input of second counter 220. The second input of NAND gate 216 is coupled to the Q output of second D flip-flop 212 and the output thereof is coupled to the load control signal input of first counter 217. The clock input of third D flip-flop 215 is coupled to the output of inverter 214, the Q output thereof is coupled to the second input of second AND gate 219, and the Q output is coupled to the second input of first AND gate 218. The data inputs of first and second counters 217 and 220 are both coupled to ground, and their Q outputs are respectively coupled to the first (I0) and second (I1) selection input ports of first and second multiplexers 221 and 222. The selection control ports (S) of first and second multiplexers 221 and 222 are coupled to the outputs of first and second AND gates 218 and 219, respectively, and their outputs (Y) are coupled to the address input ports (A) of first and second RAMs 204 and 205, respectively. The inputs of an OR gate 223 are respectively coupled to the outputs of first and second AND gates 218 and 219, and the output thereof (MSB/LSB) is coupled to the first selection control port (S0) of multiplexer 206 shown in FIG. 2. The data input port (D) of first RAM 204 is coupled to the output port RD of first data converter 202 shown in FIG. 2, the address input port (A) is coupled to the output port (Y) of first multiplexer 221, the write enable signal input port (WE) thereof is coupled to the output of first AND gate 218, and the chip enable (CE) input is coupled to the read clock port (RC) of system controller 200. The data input port of second RAM 205 is coupled to the output port ID of second data converter 203 shown in FIG. 2, the write enable signal input port thereof is coupled to the output of second AND gate 219, the address input port (A) is coupled to the output port (Y) of second multiplexer 222 and the chip enable input is coupled to the read clock port (RC) of system controller 200.

The operation of memory controller 201 shown in FIG. 3 will be explained with reference to FIG. 2 and FIGS. 4A-4U.

FIG. 4A shows the real/interpolated line control signal input through input port R/I of FIG. 3. This real/interpolated line control signal is latched in first D flip-flop 211 in accordance with the clock input (FIG. 4B) through the write clock port WC of memory controller 201, and the latched signal is output to XNOR gate 213, NAND gate 216, and second and third D flip-flops 212 and 213.

XNOR gate 213 receives the outputs of first and second D flip-flops 211 and 212 (FIG. 4C) and produces the signal LDR shown in FIG. 4D which is output to the load input of second counter 220. The LDR signal is reset at every transition of the real/interpolated line control signal (shown in FIG. 4A) input through the R/I port, which corresponds to every 1/2 horizontal line period (0.5 H) of a video signal.

Second counter 220 used for generating a read address counts the pulses of the write clock (FIG. 4B) in accordance with the load control signal LDR (FIG. 4D), and produces a 9-bit read address counting data RCNT, as shown in FIG. 4E, which can represent up to 512 addresses.

The NAND gate 216 receives the Q output, DFF2Q (shown in FIG. 4F) of second D flip-flop 212 and the Q output of first D flip-flop 211, and thereby produces the load control signal LDW (FIG. 4G) for first counter 217. The LDW signal is reset every horizontal line period (1 H).

Since the write speed is half of the read speed, first counter 217 generates write addresses by using only the upper 9-bits of its 10-bit output. Here, first counter 217 counts the pulses of the write clock (FIG. 4B) in accordance with the load control signal LDW (FIG. 4G) and produces the write address counting data WCNT, as shown in FIG. 4H.

Third D flip-flop 215 latches the real/interpolated line control signal latched in first D flip-flop 211, in accordance with the inverted write clock (shown in FIG. 4I) output from inverter 214.

Second AND gate 219 performs a logical AND operation on the output (DFF3Q shown in FIG. 4J) of third D flip-flop 215 and the write clock shown in FIG. 4B, and applies the signal (IRW) shown in FIG. 4K to the selection control port of second multiplexer 222 and the write enable signal input port of second RAM 205.

Also, first AND gate 218 performs a logical AND operation on the inverted output (DFF3Q shown in FIG. 4M) of third D flip-flop 215 and the write clock shown in FIG. 4B, and applies the signal (RRW) shown in FIG. 4N to the selection control port of first multiplexer 221 and write enable signal input port of first RAM 204.

Therefore, second AND gate 219 produces pulses (shown in FIG. 4K) only when the real/interpolated line control signal (shown in FIG. 4A) is high, and applies this IRW signal to the selection port of second multiplexer 222. First AND gate 218 produces pulses (shown in FIG. 4N) only when the real/interpolated line control signal (shown in FIG. 4A) is low, and applies this RRW signal to the selection port of first multiplexer 221. Also, the outputs of first and second AND gates 218 and 219 are applied to first and second RAMs 204 and 205 as write enable signals, respectively.

First and second multiplexers 221 and 222 select one between the read address and the write address generated from first and second counters 217 and 220, in accordance with selection signals RRW and IRW generated from first and second AND gates 218 and 219, respectively, and apply the selected one to first and second RAMs 204 and 205. At this time, the data written into first and second RAMs 204 and 205 are the real data and the interpolated data, respectively, which are converted by first and second data converters 202 and 203 shown in FIG. 2, respectively.

The read/write operation of the interpolated data output from second data converter 203 from/to second RAM 205 occurs when the real/interpolated line control signal (shown in FIG. 4A) is high.

When the logic high state of the output (IRW shown in FIG. 4K) of second AND gate 219 is input to the selection control port of second multiplexer 222 and the write enable signal input port of second RAM 205, second RAM 205 is write-disabled. At this time, second multiplexer 222 selects the read address data (R0-R.sub.2n-1) of second counter 220, which is shown in FIG. 4L and input through second selection input port I1, and applies the selected one to second RAM 205, to thereby read out the address data stored in second RAM 205 as 16-bit interpolated data IOUT.

When a logic low state of output (shown in FIG. 4K) of second AND gate 219 is input to the selection control port S of second multiplexer 222 and the write enable signal port WE of second RAM 205, second multiplexer 222 selects the write address data (W.sub.0 -W.sub.2n-1) of first counter 217 shown in FIG. 4L, and applies the selected one to second RAM 205, so that second RAM 205 performs a writing operation.

Accordingly, if second multiplexer 222 selects the write address and the read address input through first selection input port I0 and second selection input port I1 and applies the selected one to second RAM 205, the interpolated data is sequentially written to or read out from second RAM 205.

Writing or reading out the real data output from first data converter 202 to or from first RAM 204 is done only when the real/interpolated line control signal (shown in FIG. 4A) is low.

At this time, when the logic high state of the output (shown in FIG. 4N) of first AND gate 218 is input to the selection control input of first multiplexer 221 and the write enable signal input port of first RAM 204, first RAM 204 is write-disabled, and the first multiplexer 221 selects the read address data (R.sub.0 -R.sub.2n-1) of second counter 220, which is shown in FIG. 40 and is input through second selection input port I1, and applies the selected one to first RAM 204, so that the first RAM 204 performs a reading out operation.

When a logic low state of the output (shown in FIG. 4N) of first AND gate 218 is input to the selection control port of first multiplexer 221 and the write enable signal port of first RAM 204, first multiplexer 221 selects the write address data (W.sub.n -W.sub.2n-1) of first counter 217 shown in FIG. 40 and applies the selected one to first RAM 204, so that first RAM 204 performs a writing operation. Accordingly, first RAM 204 sequentially writes or reads out the real data in accordance with write/read addresses selected in first multiplexer 221.

The address input to second RAM 205 is as shown in FIG. 4L and the address input to first RAM 204 is as shown in FIG. 40. For second RAM 205, when the real/interpolated line control signal (shown in FIG. 4A) is high, read/write operations are interchangeably performed, and when low, only the write operation is performed. Conversely, for first RAM 204, when the real/interpolated line control signal (shown in FIG. 4A) is high, a write operation is performed, and when low, the read/write operations are interchangeably performed.

On the other hand, the read operation according to the read address input in the first and second RAMs 204 and 205 receiving read/write address for interpolation data and read/write address for the real data which are selected and output by first and second multiplexers 221 and 222, is controlled by the read clock input (FIG. 4P) to the chip enable ports of first and second RAM 204 and 205.

At this time, the period of the read clock (shown in FIG. 4P) input to chip enable port of first and second RAMs 204 and 205 is shorter than that of the write clock (shown in FIG. 4B).

First and second RAMs 204 and 205 read out real data or interpolated data in synchronization with the falling edge of the read clock (shown in FIG. 4P) which is input to the memory chip enable ports, when the write enable signals IRW and RRW shown in FIGS. 4K and 4N goes "high" after being "low" for 0.5 H period.

Therefore, the output of second RAM 205 is as shown in FIG. 4Q, and the output of first RAM 204 is as shown in FIG. 4R. The outputs of first and second RAMs 204 and 205 are applied to multiplexer 206 shown in FIG. 2.

OR gate 223 performs a logical OR operation on the outputs of first and second RAMs 204 and 205 and applies the signal as shown in FIG. 4S to first selection control port S0 of multiplexer 206.

The output (shown in FIG. 4S) of this OR gate 223 is used for dividing the data output from first and second RAMs 204 and 205 into the upper and lower eight bits.

Real/interpolated line control signal (shown in FIG. 4A) is delayed by delay 207 shown in FIG. 2, and the signal (shown in FIG. 4T) which has been inverted by inverter 208 is applied to second selection port S1 of multiplexer 206.

Multiplexer 206 makes a selection in accordance with the states of the input selection signals. In more detail, when the second selection control signal is "low" the interpolated data is selected and alternately applied to the first or second selection input ports I0 or I1 in accordance with the first selection control signal which is shown in FIG. 4S. When the second selection control signal shown in FIG. 4T is "high", the real data is selected and alternately applied to the third or fourth selection input ports I2 or I3 in accordance with the first selection control signal which is shown in FIG. 4S. As a result, 8-bit double scan data as shown in FIG. 4U is generated. In other words, discrimination is made between the period for the real data output RDT and the period for interpolated data output IDT.

In addition, during 1 H period of a video signal, 910 pixels can be scanned with a 14.3 MHz clock, so 910 or more address regions are required for the real 8-bit data. Since 8-bit data is converted into 16-bit data due to the read/write timing restriction of memory (corresponding to first and second RAMs 204 and 205), the number of required address regions for first and second RAMs 204 and 205 may be reduced to 455, so the number of bits for a read/write address may be set to nine. First and second RAMs 204 and 205 each can be implemented by 455.times.16 bits of RAM memory.

The present invention can be applied to a monitor for a large screen television or an LCD display.

As described above, the present invention facilitates VLSI implementation compared with the conventional double scan circuit using FIFO-type memories. Also, in the method for controlling RAM, the read/write control is not independently made for the real and the interpolated line data, but it is commonly made for the real and the interpolated line data, which results in simplifying the circuit. In addition, according to the present invention, one chip implementation of an Application Specific Integrated Circuit (ASIC) can be easily realized, by designing such that the required operating frequency of the memory is reduced to half of the ordinary one, to reduce the power consumption.