US 5,468,669 AGrant
Integrated Circuit Fabrication
Issue Date:1995-11-21
•6 Claims
•2 Drawing Sheets
Abstract
A semiconductor integrated circuit, and process for its manufacture, are disclosed which contains both n.sup.+ and p.sup.+ gates that do not pose a risk of dopant interdiffusion. Both n.sup.+ and p.sup.+ gates may be fabricated by conventional means. The gate structures are severed over the tub boundaries. A titanium nitride interconnective layer is deposited and patterned over the gates. The interconnective layer preserves connectivity between the n.sup.+ and p.sup.+ gates without risk of deleterious dopant interdiffusion.
Metadata
Assignee
- AT&T Corp.
Inventors
- Kuo-Hua Lee
- Horng-dar Lin
- Ran-Hong Yan
- Chen-Hua D. Yu
Application Information
Application Number:US 145272&
Filing Date:1993-10-29
Priority Date:1993-10-29
Art Unit:114
Classifications
IPC:
H01L 21253H01L 21335
Field of Search:
437148195;200;56;57;52;192;193;190;956DIG. 147;DIG. 20
Patent Drawings (2 sheets)
Description
Technical Field
This invention relates to methods for semiconductor integrated circuit fabrication and to semiconductor integrated circuits.
Background of the Invention
Many CMOS integrated circuits utilize n.sup.+ gate material for both PMOS and NMOS devices. However, as gate lengths shrink, there is an increasing trend to the use of p.sup.+ gates for both PMOS and NMOS devices. PMOS transistors with p.sup.+ gates (i.e., surface channel devices) exhibit good short channel performance, threshold voltages, and sub-threshold swings which are less dependent upon channel length than PMOS devices with n.sup.+ (i.e., buried channel devices) gates. NMOS transistors with p.sup.+ gates have also been found satisfactory in various CMOS applications.
Some CMOS integrated circuits may utilize both n.sup.+ and p.sup.+ gates.
However, when a gate having an n.sup.+ doped region is in contact with a gate having a p.sup.+ doped region, interdiffusion of the dopants may occur, and there is an associated loss of control of the work function. The problem is expected to occur, for example, at those locations where a gate crosses a tub boundary. That portion of the gate over the p tub may be doped n+, while that potion of what is materially the same gate may be doped p.sup.+ over the n tub.
Some manufacturers have attempted to solve the problem by capping a continuous gate runner with a titanium nitride conductor, thus preserving conduction across the tub boundary should interdiffusion occur. However, with this approach, there is still a need to limit the thermal processing budget to retard the possibility of interdiffusion.
Summary of the Invention
The present invention alleviates this problem by, illustratively, forming a dielectric layer over a substrate and forming a first conductive layer over the dielectric layer. An opening is formed in the conductive layer. Then a second conductive layer is formed overlying the first conductive layer. The first and second conductive layers are patterned together to form two gates which are electrically connected by the second conductor and not the first conductor.
Brief Description of the Drawings
FIGS. 1, 2 and 4 are partially perspective, partially cross-sectional views depicting an illustrative embodiment of this invention; and
FIG. 3 is a partially perspective, partially cross-sectional view of FIG. 2 taken along the line 3--3 further including conductive layers.
Detailed Description
In FIG. 1, reference numeral 11 denotes a substrate which may be silicon, doped silicon, epitaxial silicon, etc. In general, the term substrate is used herein to denote a material upon which other materials may be deposited or formed. Reference numeral 13 denotes a p tub, while reference numeral 15 denotes an n tub. As will be appreciated by those of ordinary skill in the art, the invention is also applicable to single tub CMOS devices and processes. Reference numeral 17 denotes a field oxide.
After definition and formation of field oxide 17, a gate oxide layer 19 having a thickness of approximately 100 .ANG. is grown. Next, a polysilicon layer 21, illustratively having a thickness of approximately 1000 .ANG., is deposited atop gate oxide 19. Finally, a refractory metal silicide layer, illustratively tungsten silicide, is formed (typically by sputtering) atop polysilicon layer 21. Reference numeral 23 denotes the silicide layer. That portion of polysilicon layer 21 over p tub 13 is doped with n type dopants; that portion of polysilicon layer 21 over n tub 15 is doped with p type dopant. A variety of techniques may be utilized to perform the doping procedure. For example, before formation of the silicide, a resist may be patterned covering the polysilicon over one of the tubs, and the exposed polysilicon doped by ion implantation.
A preferred method of doping polysilicon layer 21 is to wait until after formation of the silicide 23. Then the silicide 23 is masked and appropriate dopants injected into the silicide by ion implantation. Later, the dopants are driven out of the silicide 23 into the underlying polysilicon 21.
After the blanket deposition of layers 19, 21 and 23, an opening 60 shown in FIG. 2 is created over field oxide 17 straddling the boundary 61 between tubs 13 and 15. Opening 60 may be created by conventional photolithography including etching of layers 19, 21 and 23 to expose the top of field oxide 17.
Next, referring to the cross-sectional view of FIG. 3, a blanket layer 31 of, for example, titanium nitride (or another material with sufficiently low sheet resistance and low diffusivity) is deposited. Layer 31 is desirably covered by a material suitable for hard mask etching, illustratively a dielectric such as plasma enhanced TEOS, for example, layer 33.
Next, referring to FIG. 4, using layer 33 as a hard mask (although other photolithography processes may also be used), gate 41 in FIG. 4 is defined. (For example, layer 33 may be etched through a patterned photoresist. Then, using patterned dielectric 33 as a hard mask, the underlying layers 31, 23, 21 and 19 are etched.) The mask used to create gate 41 is aligned with opening 60 so that polysilicon 521 does not contact polysilicon 421.
Gate 41 has polysilicon layer 421 which is n.sup.+ doped over p tub 13 and polysilicon layer 521 which is p.sup.+ doped over n tub 15. As mentioned before, the etching process is aligned and performed so that there is no material continuity between polysilicon layer 421 and polysilicon layer 521 (or between oxides 419 and 519 or between silicides 423 and 523).
It will be seen from an examination of FIG. 4 that layer 31 effectively preserves electrical continuity between n.sup.+ polysilicon layer 421 and p+ polysilicon layer 521 without permitting interdiffusion of n and p type dopants. N.sup.+ polysilicon layer 421 is separate from p.sup.+ layer 521 (due to the creation of opening 60 earlier in FIG. 2).
Illustratively, subsequent processing may involve formation of junctions 33 and 35 by ion implantation or other means. Subsequent semiconductor integrated circuit processing such as dielectric deposition and runner formation may then be performed.
Claims
We claim:
1. A method of integrated circuit fabrication comprising: forming a dielectric layer overlying a substrate; forming a first conductive layer over said dielectric layer; forming an opening in said conductive layer; forming a second conductive layer overlying said first conductive layer; patterning said first and second conductive layers together to form first and second gates, said gates being electrically connected to each other by said second conductive layer and not connected by said first conductive layer; and further in which said substrate has an n tub and a p tub, there being a boundary between said tubs and in which said opening overlies said boundary.
2. The method of claim 1 in which a field oxide is formed between said substrate and said dielectric layer.
3. The method of claim 1 in which said first conductive layer is polysilicon.
4. The method of claim 1 in which said second conductive layer is titanium nitride.
5. The method of claim 1 in which a layer of a refractory metal silicide is formed between said first and second conductive layers and patterned together with them.
6. A method of integrated circuit fabrication comprising: forming an n tub and a p tub in a silicon substrate; there being layer a boundary between said tubs; forming a field oxide over said boundary; forming a blanket oxide layer over said substrate; forming a blanket polysilicon layer contacting said oxide layer, whereby that portion of said polysilicon layer overlying said n tub is p-type and that portion of said polysilicon layer overlying said p tub is n-type; forming a blanket tungsten silicide layer contacting said polysilicon layer; forming an opening through at least said tungsten silicide layer and said polysilicon layer, exposing oxide, said opening having sides and a bottom; forming a blanket layer of titanium nitride contacting said layer of tungsten silicide and contacting said sides and bottom of said opening, patterning said titanium nitride layer and said tungsten silicide layer and said polysilicon layer and said oxide layer together whereby that portion of said polysilicon layer overlying said n tub is severed from that portion of said polysilicon layer overlying said p tub and that portion of said tungsten silicide layer overlying said n tub is severed from that portion of said tungsten silicide layer overlying said p tub; and further whereby said titanium nitride layer maintains electrical conduction between the said severed portions of said polysilicon layer and said tungsten silicide layer.
Patent Citations (4)
Non-Patent Literature (2)
- Wolf, Silicon Processing, Lattice Press, 1990, vol. 2, pp. 587-593, 623-635.
- Wolf, Silicon Processing, Lattice Press, 1986, vol. 1, pp. 384-386.