US 5,465,375 AGrant
Multiprocessor System With Cascaded Modules Combining Processors Through a Programmable Logic Cell Array
Issue Date:1995-11-07
•2 Claims
•7 Drawing Sheets
Abstract
In a multiprocessor data processing system, modules are cascaded by means of intermodule buses. Each module comprises a data processing unit, a first memory, a logic cell array programmable into four input/output interfaces, a second memory and a specialized processing unit such as a digital signal processor (DSP). A first interface, the first memory and the data processing unit are interconnected by a module bus. A fourth interface, the second memory and the specialized processing unit are interconnected by another module bus. A feedback bus connects the second and third interfaces in the last and first modules for constituting a ring. Such a system is particularly intended for image recognition, such as digitalized handwritten digits for postal distribution.
Metadata
Assignee
- France Telecom
Inventors
- Andre Thepaut
- Gerald Ouvradou
Application Information
Application Number:US 0045829
Filing Date:1993-01-14
Priority Date:1992-01-14
Art Unit:235
Classifications
IPC:
G06F 1516
Field of Search:
395370364200;325;80053;85.9137
Patent Drawings (7 sheets)
Description
Background of the Invention
1. Field of the Invention
This invention relates to multiprocessor data processing systems in general.
2. Description of the Prior Art
The increasingly greater computational throughput requirements in data processing systems for applications such as image processing or scientific computation, have led computer designers to introduce new processor architectures: parallel architectures. Three basic principles are used for introducing this parallelism in the new achitectures. The distinction is made between:
segmented (or pipeline) architectures: this consists in breaking a task down into plural steps and in performing these steps independently by different processors. Every time an intermediary result is obtained after performance of a step, it is transmitted to the next processor and so on. When a step is completed, the processor in charge of performing it is freed and thus becomes available to process new data. Presupposing the respective durations of performance of the different steps to be substantially equal, the period required to obtain the final results is then the duration of performance of one step, and not the duration of performance of the task;
array processor architectures or SIMD (Single Instruction, Multiple Data Stream) architectures. In this type of architecture, the increase in computational throughput is obtained by having the same instruction performed by a large number of identical processing units. This type of architecture is particularly well suited to vectorial processing; and
multiprocessor architectures or MIMD (Multiple Instruction, Multiple Data Stream) architectures. In such an architecture, several processors perform respective streams of instructions independently of one another. Communication between the processors is ensured either by a common memory and/or by a network interconnecting the processors.
Pending European Patent Application No. 433,142 filed Dec. 6, 1990 discloses an architecture of a multiprocessor data processing system in which the bus is shared between plural processor stages and is interfaced in each stage by a programmable LCA Logic Cell Array configurated into plural input/output means and a switching means. The main advantage of such an architecture is to dispense each processor from bus request and management tasks, the latter being carried out in the logic cells array associated with the processor. Nonetheless, this architecture is not optimal for the multiprocessor approach to scientific computation applications. Each processor is in fact entrusted with all the tasks to be performed (excepting management of the bus). Numerous multiprocessor applications require considerable computational means and a single unspecialized processor per stage restricts performances.
Objects of the Invention
The main object of this invention is to remedy the preceding disadvantages.
Another object of this invention is to provide a data processing system optimizing the multiprocessor approach for each stage of the above-mentioned architecture.
Summary of the Invention
Accordingly, there is provided a multiprocessor data processing system embodying the invention including a plurality of cascaded modules.
Each of the cascaded modules comprises
a data processing unit connected to other data processing units in immediately adjacent downstream and upstream modules by way of a communication network. Each of the cascaded modules further comprises;
a first memory,
an additional processing unit,
a second memory,
a logic programmable cell array. The programmable logic cell array is configurable into first, second, third and fourth input/output interfaces for temporarily memorizing data into memorized data, and into a central processing and switching circuit for processing the memorized data into processed data and switching the processed data towards one of the input/output interfaces. Each cascaded module further comprises;
a first module bus for interconnecting the data processing unit, the first memory and the first input/output interface, and
a second module bus for interconnecting the additional processing unit, the second memory and the fourth input/output interface.
The second and third input/output interfaces in each of the modules are interconnected to the third input/output interface in the immediately adjacent downstream module and the second interface in the immediately adjacent upstream module by two intermodular buses, respectively.
According to another embodiment, given that, on the one hand, the processing and switching means is configurated for once and for all for a given application and, on the other hand, that several successive multiprocessor processings can be carried out by the processing units on a same data stream, the data already processed according to a first processing must be redistributed to the different modules for a next processing. In this case, the second and third input/output interfaces respectively in the programmable logic cell arrays of the last and first modules of the plurality of cascaded modules are connected by way of a feedback bus.
The invention also relates to a data processing method implemented in a multiprocessor data processing system embodying the invention. The method comprises:
an first step further consisting in loading a respective set of weights into the second memory of each of the cascaded modules via the communication network, and the input data into the first memory of the first module, and
at least one set of second and third steps,
the second step consisting in carrying out partial processings on the input data in the additional processing unit of each cascaded module as a function of the respective set of matrix multiplication weights in order to determine partial data, and
the third step consisting in downloading the partial data to any one of the programmable logic cell arrays or any one of the first and second memories in the cascaded modules via the intermodular buses and the feedback bus.
Brief Description of the Drawings
Further features and advantages of the invention will be apparent from the following particular description of two preferred embodiments of this invention with reference to the corresponding accompanying drawings in which:
FIG. 1 is a modelized diagram of an artificial neural network;
FIG. 2 is a diagram of a layered architecture of the modelized representation in FIG. 1;
FIG. 3 is a block diagram of a multiprocessor data processing system with reconfigurable active bus according to the prior art;
FIGS. 4A and 4B are two respective block diagrams of two embodiments of a data processing system with specialized coprocessor embodying the invention;
FIG. 5 is a diagram of feature maps obtained for successive processings in the layers of an artificial neural network;
FIG. 6 is a diagram of connections associated with synaptic weights between two adjacent layers of an artificial neural network;
FIG. 7 is a loading diagram of synaptic weights relating to two successive layers in a data processing system according to a preferred embodiment of the invention; and
FIG. 8 is a diagram of algorithms relating to the processing of the connections between two successive layers used in the system according to FIG. 7.
Description of the Preferred Embodiments
The multiprocessor data processing system embodying the invention is described hereinafter for a particular embodiment concerning artificial neural networks.
A very general model representing a multilayer neural network is represented in FIG. 1: a certain number of elementary units . . . N.sub.i-1, N.sub.i, N.sub.i+1 . . . called neurons and defined by their respective outputs . . . S.sub.i-1, S.sub.i, S.sub.i+1 . . . constitute the nodes of the network. Each neuron N.sub.i is activated by a "potential" V.sub.i defined by the equation: ##EQU1## in which s.sub.j represents an output level of a neuron N.sub.j "connected " to the neuron N.sub.i, and W.sub.ji designates a synaptic weight of the connection between the neurons N.sub.j and N.sub.i. With this potential V.sub.i is associated the output level S.sub.i corresponding to the neuron N.sub.i defined by the relation:
in which f is a non-linear function.
In practice and by analogy with the human brain, these neurons are not organized anarchically, but are grouped in layers in the form of "columns", connections between two adjacent layers being assigned to a particular function, as shown in FIG. 2. This figure represents n layers of superimposed neurons comprising two end layers LAYER 1 and LAYER N, and (N-2) hidden layers LAYER 2 to LAYER (N-1) included between the two end layers. The end layer 1 is commonly called the "retina " or "input layer " and receives an input vector whereas the end layer LAYER N, or output layer, produces a corresponding output vector. In this representation, each neuron of a given layer n is connected to each of the neurons of the immediately adjacent upper layer (n+1), the integer n lying between 1 and N-1. As specified, with reference to FIG. 1, a respective synaptic weight W is attributed to each of these connections.
In practice, and by way of an example, the neural network can be used for recognition of digits such as 0, 1, 2, . . . , 8, 9. In this case, the input vector is a block of digital pixels of a digitized image of a given digit written by any person whomsoever. To each connection between neurons is attributed a respective synaptic weight W deduced during a learning phase of the network. These synaptic weights correspond to values of coefficients of multiplication matrix applied to pixels of the image. The output layer LAYER N produces an output vector which is a binary information identifying the "recognized " digit. Outputs of neurons of a respective layer produce a feature map which has "filtered " features of the feature map produced from the outputs of the neurons of the lower adjacent layer. Each step in the implementation of this model for the multiprocessor data processing system embodying the invention will be described in greater detail further on.
A multiprocessor data processing system according to the prior art, as described in pending European Patent Application No. 433,142 filed Dec. 6, 1990, is shown in FIG. 3. The multiprocessor system comprises a plurality of modules in cascade, of which two adjacent modules M.sub.i and M.sub.i+1 are represented in FIG. 3. Each of the modules M.sub.i, M.sub.i+1 includes a processor PR.sub.i, PR.sub.i+1, called a transputer, a RAM memory ME.sub.i, ME.sub.i+1 and a programmable logical cell array LCA.sub.i, LCA.sub.i+1. The respective processors of the various modules are interconnected by means of an interprocessor communication network RC. This communication network RC notably ensures the transfer of monitoring/control information between processors. For a given module M.sub.i, the processor PR.sub.i, the memory ME.sub.i and the logic cell array LCA.sub.i are interconnected by means of a respective module bus BM.sub.i. This module bus BM.sub.i is composed of three specialized elementary buses which are a data bus, an address bus and a control bus, and interconnects the processor, the memory and a first input/output interface in the logic cell array LCA.sub.i. Programmable logic cell arrays (LCA) are known to those skilled in the art and are constituted by configurable logic, combinational and sequential circuits. The configuration of the programmable logic cell array (LCA.sub.i) is set up by the module processor PR.sub.i.
According to the above-mentioned architecture, the programmable logic cell array is configurated into three input/output interfaces and a central data processing and switching circuit (hereinafter, the central circuit). The input/output interfaces notably carry out temporary data storage functions. The central circuit ensures data switching functions between the interfaces, and elementary processing functions (data format modification, encoding, precomputed functions) e.g. in pipeline mode. The first interface of the logic cell array constitutes the interface between the module bus BM.sub.i and the central circuit whereas the second and third interfaces respectively interface the central circuit with two intermodular buses BIM.sub.i and BIM.sub.i-1. The buses BIM.sub.i and BIM.sub.1-1 are then respectively connected with a third interface in the logic cell array of an immediately adjacent downstream module M.sub.i+1 and a second interface in the logic array of an immediately adjacent upstream module M.sub.i-1.
The introduction of a programmable logic cell array in each module of such a multiprocessor architecture is particularly interesting in that its induces a fine grain of parallelism between modules while assigning the low-level tasks (access to the intermodular bus, elementary functions) to the logic array LCA.sub.i.
FIG. 4A shows the first embodiment of a data processing system according to the invention for the carrying out of an artificial neural network within the scope e.g. of recognition of digits included between 0 and 9. The system comprises I modules 2.sub.1 to 2.sub.I in a cascaded architecture.
Each module 2.sub.i, i being an integer varying between 1 and I, comprises a data processing unit in the form of a processor 20.sub.i, a first RAM type memory 21.sub.i, a programmable logic cell array 22.sub.i, a second memory 23.sub.i, and a digital signal processor constituting a coprocessor or dedicated specialized processing unit 24.sub.i. Within the module 2.sub.i, the processor 20.sub.i, the memory 21.sub.i and an input/output interface 221.sub.i of the programmable logic cell array 22.sub.i are interconnected by means of a common module bus 25.sub.i. Typically, this common bus is constituted by the three elementary buses, i.e., address bus, data bus and control bus.
By comparison with the foregoing description in reference to the prior art according to FIG. 3, the programmable logic cell array 22.sub.i is programmed into four input/output interfaces 221.sub.i, 222.sub.i, 223.sub.i and 224.sub.i and a central data processing and switching circuit 220.sub.i. According to this embodiment, the input/output interfaces 221.sub.i to 224.sub.i principally constitute temporary storage means or buffer means. The central circuit 220.sub.i is configurated to switch data from and to the input/output interfaces 221.sub.i to 224.sub.i, and to conduct elementary processing of the data received through the input/output interfaces.
The first input/output interface 221.sub.i is connected to the module bus 25.sub.i. This input/output interface 221.sub.i is e.g. used for:
temporary storage of data transmitted by the processor 20.sub.i in order to free the latter for other tasks; and
direct memory access (DMA) to the memory 21.sub.i connected to processor 20.sub.i by means of the logic cell array 22.sub.i.
The second and third interfaces 222.sub.i and 223.sub.i in the logic cell array 22.sub.i of the ith module 2.sub.i are respectively connected to a third input/output interface 223.sub.i+1 of an immediately adjacent downstream module 2.sub.i+1, and a second input/output interface 222.sub.i-1 of an immediately adjacent upstream module 2.sub.i-1. These connections are respectively made by means of two intermodular buses BI.sub.i(i+1) and BI.sub.(i-1)i. The I programmable logic cell arrays are thus cascaded by means of intermodular buses BI.sub.12, . . . , BI.sub.(I-1)I. According to this first preferred embodiment, the third input/output interface 223.sub.1 of the first module 2.sub.1 and the second interface 222.sub.I of the I.sup.th module 2.sub.I are connected by a feedback bus BR.
The intermodular buses BI.sub.12 to BI.sub.(I-1)I in series with the feedback bus BR thus constitute a ring. The second and third interfaces 222.sub.i and 223.sub.i can e.g. be used during a transmission of data between processors 20.sub.i of non-adjacent modules and thus confer high-speed communication node functions upon the logic cell arrays 22.sub.i.
In each module 2.sub.i, the digital signal processor 24.sub.i, the second memory 23.sub.i and the fourth input/output interface 224.sub.i are interconnected by means of a common bus 26.sub.i.
With reference to FIGS. 5, 6, 7 and 8, the operation of the data processing system embodying the invention will now be described for the preferred embodiment concerning artificial neural networks.
FIG. 5 shows typical results obtained within the scope of artificial neural networks for the recognition of handwritten digits included between 0 and 9. Such an application can e.g. concern the recognition of zipcodes for "automated " postal distribution. In the diagram in FIG. 5, the vertical ordinate axis relates to the numbers of neuron layers in an architecture such as that presented in reference to FIG. 2. In this diagram, the number of neuron layers is presupposed equal to 5. The input vector is an input block having (28 by 28) pixels representing any digit whatsoever, 0 in this instance, written by a person and digitized. The network is composed of 4,634 neurons.
Each neuron in the input layer (LAYER 1), called retina, respectively receives a pixel of the input vector. The first hidden layer LAYER 2 is divided into 4 sub-layers of (24 by 24) neurons. Each neuron of each sub-layer receives (5 by 5) neighboring pixels of the input block after multiplication by a line matrix of respective synaptic weights. It is recalled that these synaptic weights are used for processing into matrix multiplication coefficients. Four blocks of (24 by 24) pixels are thus supplied by the respective outputs of the four sub-layers of neurons of LAYER 1.
The synaptic weights applied between the outputs of the neurons of the layer LAYER 1 and the four sub-layers of the second layer LAYER 2 relate to specific processings on the image of (28 by 28) input block pixels. Respective synaptic weights between the four sub-layers of LAYER 2 and four sub-layers of LAYER 3 relate to averaging and subsampling by two processings. Respective outputs of the neurons of the four sub-layers of LAYER 3 thus produce four image blocks of (12 by 12) pixels.
Details of LAYER 3 and LAYER 4 will not be provided. It should nevertheless be remarked that the role of each layer consists in extracting fundamental features from the digitalized (28 by 28) pixel block of a handwritten digit. As shown in FIG. 5, an output layer of 10 neurons produces ten pixels in black and white, the rank of the sole white pixel produced by one of the ten neurons being representative of the "recognized " input digit subsequent to the various "digital filtering " steps respectively performed by the neuron layers.
In reference to FIGS. 6, 7 and 8, the installation of an artificial neural network in the multiprocessor data processing system embodying the invention, as shown in FIG. 4A, will now be described. According to this preferred embodiment, the neural network comprises three layers of 256, 40 and 10 neurons respectively. The neurons of the first layer, called input layer, and of the second layer each set up connections (each assigned to a respective synaptic weight) respectively with each of the neurons of the immediately adjacent upper layer, i.e., the second layer and the third layer, called output layer. The input vector is a block of (16.times.16)=256 pixels of a digitalized image of a handwritten digit included between 0 and 9.
As shown in FIG. 6, all the connections assigned to respective synaptic weights between two adjacent layers respectively having J and J' neurons are fully defined by a single rectangular matrix of size (J.times.J'). Each weight W.sub.jj, of the rectangular matrix, j being included between 1 and J, and j' between 1 and J', corresponds to a value of a synaptic weight of the connection between a neuron of rank j and a neuron of rank j' of the two adjacent layers respectively.
In compliance with the preferred embodiment, two respective matrices of (J.times.J')=(256.times.40) and (J.times.J')=(4.times.10) synaptic weights between the first and second layers and between the second and third layers are then used, i.e., a total of 10,640 weights or connections.
For indicative purposes, these synaptic weights for particular embodiments (recognition of digits, . . . ) are obtained during a learning phase by a gradient back-propagation algorithm. Summarily, this algorithm performs the recognition computations for synaptic weights given initially. The results of these computations are compared to expected recognition results. The weights are modified taking this comparison into account. After several iterations, the synaptic weights converge towards optimal recognition values. This learning phase is generally very costly as regards time.
According to the first preferred embodiment, the data processing system embodying the invention (FIG. 4A) comprises I =10 modules 2.sub.1 to 2.sub.10. In a first step, as shown schematically in FIG. 7, each module 2.sub.i, i lying between 1 and 10, is assigned to the processing relating to all the connections between the input layer and respectively one of the ten quadruplets of neurons in the second layer (4.times.10=40). The matrix computations: ##EQU2## where k varies between 1 and J=(16.times.16) and p varies between 1 and J'=40,
are carried out by the same digital signal processor for four set values of the index p, and therefore in relation to the four neurons of a respective quadruplet.
One advantage of the invention is that these matrix multiplications are performed by the digital signal processors 24.sub.i to 24.sub.I=10.
Further to this first processing (connections between the first and second layers), each digital signal processor 24.sub.i to 24.sub.10 is assigned to the processing of the matrix multiplications relating to the connections between the neurons of the second layer and a respective neuron of the third layer, called output layer (1.times.10=10).
The utilisation of a digital signal processor or specialized coprocessor 24.sub.i frees the processor 20.sub.i which can perform other tasks.
In reference to FIGS. 8 and 4A, the implementation and operation of an artificial neural network in the multiprocessor data processing system embodying the invention will now be described.
Prior to the operation of the system as an artificial neural network in the recognition mode, the system is initiated at the initiative of a master computer 1 connected to the first processor 20.sub.1. This initiation is established by the computer 1 via the interprocessor communication network RC. The initiation comprises:
with regard to each processor 20.sub.1 to 20.sub.10 :
loading of an operating program in the respective memory 21.sub.1 to 21.sub.10 via the bus 25.sub.1 to 25.sub.10 ;
configurating of the associated logic cell array 22.sub.1 to 22.sub.10 ;
loading of programs (matrix multiplication, . . . ) relating to the operation of the digital signal processor 24.sub.1 to 24.sub.10 in the associated memory 23.sub.1 to 23.sub.10 via the network 22.sub.1 to 22.sub.10, and
loading of a respective set of synaptic weights such as previously described and relating to the digital signal processor 24.sub.1 to 24.sub.10, in the associated memory 23.sub.1 to 23.sub.10 ;
as well as the loading of the first input vector constituting input data e.sub.1 to e.sub.J to be recognized by processing (block of 16 by 16 pixels), in the memory 21.sub.1 of the processor 20.sub.1 of the first module 2.sub.1.
In the case of a sequential processing of plural input data vectors to be recognized, the latter are memorized as they become available in the memory 21.sub.1 connected to the processor of the first module 2.sub.1. Each of the input vectors is e.g. supplied by the master computer 1 subsequent to a preprocessing (linear processing to normalize the 16 by 16 size of the initial blocks supplied by a video camera) on the initial blocks via the communication network RC.
The diagram of algorithms relating to a first processing of connections between first and second layers of neurons in FIG. 8 enables the operation of the multiprocessor data processing system embodying the invention as an artificial neural network to be grasped. Each of the "tables " in FIG. 8 relates to an algorithm performed by one or more of the processors 20.sub.i, digital signal processors 24.sub.i, or logic cell arrays 22.sub.i of the system.
It has been seen previously that the input data vector is initially loaded in the memory 21.sub.1. The processor 20.sub.1 reads this vector in the memory 21.sub.1 and writes it in the first input/output interface 221.sub.1 of the programmable logic cell array 22.sub.1 of the first module 2.sub.1. The central processing and switching circuit 220.sub.1 of network 22.sub.1 then switches this vector towards the second interface 222.sub.1 and this second interface 222.sub.1 retransmits it to the third interface 223.sub.2 of the logic cell array 22.sub.2 of the second module 2.sub.2 and so on so forth. The vector is thus broadcast in the ring BI.sub.12 to BI.sub.(I-1)I successively to the adjacent modules immediately above. Each of the central means of the networks switches and takes via the fourth interface 224.sub.i the set of (16 by 16) pixels of the vector towards the memory 23.sub.i associated with its digital signal processor 24.sub.i. The data input vector used by each module 2.sub.i in the configuration previously described is thus memorized in the respective memory 23.sub.i associated with the digital signal processor 24.sub.i.
The first step (step 1) of the algorithm relating to each of the digital signal processors 24.sub.i, with i lying between 1 and I, consists in computing the potential V.sub.i relating to the neurons attributed to the module 2.sub.i, then in writing the potential thus computed in the input/output interface 224.sub.i of the logic cell array 22.sub.i of the same module 2.sub.i. Each 220.sub.i of the central circuit of the logic cell arrays configurated for this purpose gradually transmits the results of the potential computations V.sub.1 to V.sub.i to the next logic cell array 22.sub.i+1 until all the results V.sub.1 to V.sub.I have been received by the third input/output interface 223.sub.i of the logic cell array of the first module 2.sub.1 via the feedback bus BR (step 2).
Then the input/output interface 223.sub.i of the first module 2.sub.1 writes the potential computation results received in the memory 23.sub.1 and alerts the digital signal processor 24.sub.i (step 3). The processor 24.sub.1 computes the value of the sigmoid function (non-linear f function based on hyperbolic tangent functions defined from the model initially presented in the specification) for each "pixel " or neuron potential V.sub.i produced by the processors 24.sub.i (step 5) for obtaining the output levels of all the neurons in the second layer for this first processing. At the same time and as each digital signal processor 24.sub.i writes the computed potentials specific to the four neurons of the second layer which it simulates in this first processing, in the associated memory 23.sub.i, the processors 20.sub.1 to 20.sub.I then read the neuron potentials respectively memorized in the memories 23.sub.1 to 23.sub.I when all the potentials have been computed (step 2').
According to the embodiment, two processings relating to the first and second layers and to the second and third layers are provided. In this way the outputs of the neurons in the second layer of the chosen configuration memorized in the memory 23.sub.i are reprocessed by the digital signal processors 24.sub.1 to 24.sub.I for new potential computations after broadcasting in the ring of the neuron outputs as computed during the first processing.
According to the second embodiment shown in FIG. 4B, the addition of an additional module 2.sub.0 to the initial modules 2.sub.1 to 2.sub.I is proposed upstream of the latter. This additional module comprises a processor 20.sub.0, a memory 21.sub.0 and a programmable logic cell array 22.sub.0. This module is provided in order to directly inject the pixel images to be processed into an input/output interface 223.sub.0 of the programmable logic cell array 22.sub.0. This injection enables an increase of the flow of images to be processed since the images then do not transit via the master computer 1 and, furthermore, do not require utilisation of the communication network RC. A data (images) acquiring system, such as a video camera or scanner (not shown), is then directly connected to the third input/output interface 223.sub.0 of the programmable array 22.sub.0 of the additional module 2.sub.0 via a bus BI. The memory 21.sub.0, the processor 20.sub.0 and a first input/output interface 221.sub.0 of the programmable logic cell array 22.sub.0 in the additional module 2.sub.0 are interconnected in identical manner to the interconnections in the other modules 2.sub.1 to 2.sub.I, by means of a bus 25.sub.0. The images to be processed which are injected via a bus in the third input/output interface 223.sub.0 of the programmable logic cell array 22.sub.0 can undergo a first preprocessing (16 by 16 formatting), in a processing and switching circuit 220.sub.0 of the logic cell array 22.sub.0 by programming of the latter. The second interface 222.sub.0 is connected to the third interface 223.sub.1 of the first 2.sub.1 of the modules in cascade 2.sub.1 to 2.sub.I via an additional intermodular bus BI.sub.01.
For identical reasons to those of the first embodiment, a feedback bus BR can also be provided. The latter interconnects the second input/output interface 222.sub.I of the programmable logic cell array 22.sub.I of the last module 2.sub.I to the fourth input/output interface 224.sub.0 of the logic cell array 22.sub.0 of the additional module.
For indicative purposes, a recognition of a digitized handwritten digit in (16 by 16)pixels by the data processing system embodying the invention simulating 10,640 neurons requires 175 .mu.s. Durations of the order of a tenth of millisecond are usually required for conventional systems.
Claims
What we claim is:
1. An input data processing method implemented in a multiprocessor data processing system, said multiprocessor data processing system comprising a plurality of cascaded modules, each of said cascaded modules comprising: a data processing unit connected to other data processing units in immediately adjacent downstream and upstream modules by means of a communication network, a first memory for storing data, an additional processing unit, a second memory for storing data associated with said additional processing unit, a programmable logic cell array configurable into first, second, third and fourth input/output interfacing means for temporarily memorizing data into memorized data, and into a central processing and switching means for processing said memorized data into processed data and switching said processed data towards one of said input/output interfacing means, a first module bus for interconnecting said data processing unit, said first memory and said first input/output interfacing means, and a second module bus for interconnecting said additional processing unit, said second memory and said fourth input/output interfacing means, said second and third input/output interfacing means in said each of said cascaded modules being interconnected to the third input/output interfacing means in said immediately adjacent upstream module and the second input/output interfacing means in said immediately adjacent downstream module, by two intermodular buses, respectively, said second and third input/output interfacing means respectively in said programmable logic cell array of a last module and a first module in said plurality of said cascaded modules being connected by means of a feedback bus, said input data processing method comprising: a first step further consisting in loading a respective set of matrix multiplication weights into said second memory of each of said cascaded modules via said communication network and said input data into said first memory of said first module, and at least one set of second and third steps in each of said cascaded modules, said second step consisting in carrying out partial processings on said input data in said additional processing unit of said each cascaded module as a function of said respective set of matrix multiplication weights for determining partial data, and said third step consisting in downloading said partial data to any one of said programmable logic cell arrays or any one of said first and second memories in said cascaded modules via said intermodular buses and said feedback bus.
2. An input data processing method implemented in a multiprocessor data processing system, said multiprocessor data processing system comprising a plurality of cascaded modules, each of said cascaded modules comprising: a data processing unit connected to other data processing units in immediately adjacent downstream and upstream modules by means of a communication network, a first memory for storing data, an additional processing unit, a second memory for storing data associated with said additional processing unit, a programmable logic cell array configurable into first, second, third and fourth input/output interfacing means for temporarily memorizing data into memorized data, and into a central processing and switching means for processing said memorized data into processed data and switching said processed data towards one of said input/output interfacing means, a first module bus for interconnecting said data processing unit, said first memory and said first input/output interfacing means, a second module bus for interconnecting said additional processing unit, said second memory and said fourth input/output interfacing means, said second and third input/output interfacing means in said each of said cascaded modules being interconnected to the third input/output interfacing means in said immediately adjacent downstream module and the second input/output interfacing means in said immediately adjacent upstream module by two intermodular buses, respectively, and an additional module, a data acquiring means and an additional intermodular bus, said additional module including a data processing unit, a first memory and a programmable logic cell array configurable into first, second, third and fourth input/output interfacing means, said acquiring means being interconnected with said third input/output interfacing means in said programmable logic cell array of said additional module, said additional intermodular bus interconnecting said second input/output interfacing means in said programmable logic cell array of said additional module and said third input/output interfacing means in a first of said plurality of said cascaded modules, wherein said second input/output interfacing means in said programmable logic cell array of the last module in said plurality of said cascaded modules and said fourth input/output interfacing means in said additional module are connected by means of a feedback bus, said input data processing method comprising: a first step further consisting in loading a respective set of matrix multiplication weights into said second memory of each of said cascaded modules via said communication network and said input data into said first memory of said first module, and at least one set of second and third steps in each of said cascaded modules, said second step consisting in carrying out partial processings on said input data in said additional processing unit of said each cascaded module as a function of said respective set of matrix multiplication weights for determining partial data, and said third step consisting in downloading said partial data to any one of said programmable logic cell arrays or any one of said first and second memories in said cascaded modules via said intermodular buses and said feedback bus.
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