Solid State Disk Memory Using Storage Devices With Defects

This invention relates generally to data storage systems for computers, and more particularly to a solid-state disk memory storage system.

As it is known in the art computer systems generally use several types of memory systems. For example, computer systems generally use so called main memory comprised of semiconductor devices typically having the attribute that the devices can be randomly written to and read from with comparable and very fast access times and thus are commonly referred to as random access memories. However, since semiconductor memories are relatively expensive, other higher density and lower cost memories are often used. For example, other memory systems include magnetic disk storage systems. With magnetic disk storage systems generally access times are in the order of tens of milliseconds whereas main memory the access times are in the order of hundreds of nanoseconds. Disk storage is used to store large quantities of data which can be sequentially read into main memory as needed. Another type of disk like storage is solid state disk storage. Solid state disk storage is comprised of solid state memory devices which are accessed as though they were magnetic disks. One advantage over magnetic disk however is that they are much faster than magnetic disk memory systems. So called solid state disks memory systems are also more expensive than magnetic disk devices.

As it is also known in the art, memory systems including the aforementioned solid state disk memory storage system traditionally use storage devices with no "hard" faults. That is, the system is constructed to account for temporary or "soft" errors, but if the storage device has a hard or permanent fault, the device is replaced, or addressing is configured to map around the hard or permanent fault location. Since dynamic memory devices, DRAMs, are susceptible to radiation-induced soft failures, simple error detection and correction techniques are often used to withstand single-bit per word errors. Such non-permanent failures can be "scrubbed" by writing the corrected data back into the memory location. In such a memory system, the typical failure mechanism is the combination of a hard error and a soft failure in the same memory location.

In the DRAM manufacturing process, any given lot yields some percentage, typically large but less than 100%, of devices with no defects. The bulk of the failing devices have only a single storage location that is defective, although many other failures that affect more than one location are possible. The failing devices are typically sent to a crusher and destroyed, although some uses for devices in digital audio have developed, i.e., so-called Audio RAMs.

Several methods have been proposed to allow the use of DRAMs having defective bits. For example, in U.S. Pat. No. 4,992,984, a method of identifying and mapping around bad locations is disclosed. The overhead imposed by the need for finding the faults and then translating addresses for mapping around faulty locations in a memory results in lower performance in the overall system.

A goal of semiconductor integrated circuit designers for many years has been so-called "wafer scale integration." Enormous economies could result from using an entire wafer in undivided form, rather than scribing and breaking into individual chips, then packaging the chips. However, the likelihood of an entire wafer having no defective cells is minuscule, so some mechanism is needed to account for defective parts of the wafer. Usually, the method of accounting for defects is to locate the defective cells by testing, then mapping around the defects. That is, the addresses of the defective locations are stored in the memory system, as in a section of non-volatile memory, and attempts to access these locations are mapped to spare locations.

A technique of this type was disclosed by Anamartic, Ltd. for dealing with wafer-scale memories. The technique is to break the memory into subsections, called "tiles," where the size of a tile is a tradeoff between overhead circuitry and the amount of storage lost in the case of a memory fault (typical sizes are 8 KB to 64 KB). The memory system includes sufficient spare tiles so that a given capacity can be guaranteed in the face of errors. Each tile contains logic that can be used to disable that tile if a fault is found in the tile. This configuration logic is set up on initialization from a map that is stored in a non-volatile media such as magnetic disk or EEPROM.

Error correcting codes have been used in memory sub-systems to enhance the reliability of memory. That is, ostensibly perfect memory elements have associated failure rates (usually soft errors caused by alpha particle hits in DRAMs) which could cause the memory system to return faulty data, if it were not for the error correcting code. The Hamming code single bit error correction normally used in memory has the virtue that it is not too complex to implement in a way that minimizes its impact on memory performance, while substantially improving the main memory reliability.

Often in memory systems complex error correcting techniques are used. In particular so called non-binary block codes such as a Reed Solomon code is used. With these codes data are grouped in "symbols" which are data from several data words such as the i.sup.th bit of N words. Data formatters are used to convert from data word format to symbol format. One problem is that such formatters are not generally configurable. With solid state disk it often occurs that different DRAM's are used in a disk.

In accordance with the present invention a method of operating a solid state disk memory apparatus includes the steps of providing an array of memory cells of random access memory devices, generating in response to a first plurality of multi-bit symbol data, a second plurality of multi-bit symbols of error correcting code check bits associated with said symbol data, and applying multi-bit symbol data and associated check bit symbols read from said array of memory cells of said random access memory devices to a network that can detect and correct N errors in said read symbol data and associated check bit symbols, where N is an integer greater than 1. With such an arrangement, a high performance error correction technique is applied to correct multiple symbol errors in read symbol data. Accordingly, with one aspect of the invention, through the use of said techniques solid state disk devices can be constructed using semiconductor RAMs such as dynamic RAMs (DRAMs) having known defective cells. By using multiple-symbol error correcting codes in the solid state disk it is no longer necessary that all storage devices be ostensibly perfect devices. Instead, a certain density of defective memory cells or locations can be tolerated in the solid state disk, yet the solid state disk memory system will return perfect data due to the multi-symbol error correct code techniques used.

In accordance with a further aspect of the present invention, a solid state disk memory apparatus includes a plurality of semiconductor random access memories. The solid state disk memory apparatus further includes means for controlling read and write requests to and from said plurality of memories, with said controlling means including means, responsive to data symbols to be stored in said plurality of memories, for providing multi-bit symbols of error correcting code check bit symbols associated with said data symbols to be stored. The controlling means further includes means for correcting symbol errors in data symbols read from said plurality of memories and associated check bit symbols, comprising a network that can correct up to N symbol errors, where N is an integer greater than 1. With such an arrangement a network is provided to correct symbol errors occuring in data read from said plurality of memories. This network permits the use of semiconductor memory devices having a certain density of defective memory locations. It is believed that the added cost of the correction network, and additional storage for the check bit symbols will be more than offset by using DRAM's or SRAM's having manufacturing defects, since such defective devices could be purchased at a large discount.

The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as other features and advantages thereof, will be best understood by reference to the detailed description of a specific embodiment, when read in conjunction with the accompanying drawings, wherein;

FIG. 1 is a block diagram of a computer system which uses a memory arrangement according to one embodiment of the invention;

FIG. 2 is a diagram of access times for various parts of the hierarchical memory of the system of FIG. 1;

FIG. 3 is a block diagram of a memory controller for a main memory used in the system of FIG. 1;

FIG. 4 is a memory map of the memory space of the CPU of the system of FIG. 1;

FIG. 5 is a block diagram of an error detection correction (EDC) circuit used in the main memory controller of FIG. 3;

FIG. 6 is a block diagram of a syndrome generator used in the error detection correction (EDC) circuit of FIG. 5;

FIG. 7 is a block diagram of a circuit used to calculate coefficients of an error location polynomial in the EDC circuit of FIG. 5;

FIG. 8 is a diagram which shows the relationship of FIGS. 8A, 8B, 8C, 8D, 8E, and 8F;

FIGS. 8A-8F are portions of a Galois Field multiplier circuit used as one of the multiplier circuits in a Galois field multiplier bank in the circuit of FIG. 7;

FIG. 9 is a block diagram of a circuit to provide exclusive or combinations of coefficients of an error location polynomial based on the number of errors in the data and a circuit to correct the errors in the raw data;

FIG. 10 is a schematic diagram of a typical error correction circuit used in the circuit of FIG. 9;

FIG. 11A is diagram of a wafer including a wafer-scale integrated memory which may be used in the system of FIG. 1;

FIG. 11B is a top view of a chip or die in the wafer of FIG. 11A;

FIG. 12 is a block diagram of a memory controller for a solid state disk for use in the system of FIG. 1;

FIG. 13 is a block diagram of a data formatter for converting between symbol data format and memory data format;

FIG. 14 is a block diagram of an array used with the formatter of FIG. 13; and

FIGS. 15A-15D are diagrammatical representations of the array for various formatter functions.

Referring to FIG. 1, a computer system 9 is shown to include a CPU 10, usually constructed in a single integrated circuit chip, coupled by a system bus 11 to a main memory 12. A memory controller 13 handles the interface between the system bus 11 and the main memory 12. Read and write requests are sent by the CPU 10 to the memory via the bus 11.

In particular, the main memory 12 is comprised of semiconductor memory devices. The main memory is an example of a memory apparatus which can be characterized as comprised of storage locations which should return during a read cycle, true or correct data. Illustrative examples of devices which can be used in such a memory apparatus includes random access memory devices (RAM) whether so-called "dynamic" (DRAM) or "static" (SRAM). They can be volatile or nonvolatile types such as the emerging ferroelectric based memory devices. For other types of memory systems not using RAM, the devices could include programmable devices, such as PROMs, EPROMs and in particular flash EEPROMs (flash electrical erasable programmable read only memories). Other types of memory include ROM (read only memory). Other memory technologies could also be included such as magnetic bubble, CCD (charge coupled devices), and CDROM.

In the following discussion DRAMs for use in a computer are used as an example although other memory devices for other memory systems could also be used. Further, the memory system does not need to be directly associated with a computer CPU. For example, high definition television and graphics processors could also use an embodiment of the memory system.

The memory controller 13 may include an error correcting code (ECC) circuit 14 to add ECC check bits to the data being stored, in response to a write request, before this data is written to here the DRAM arrays of the main memory 12, in a manner so that the DRAM devices used in the main memory 12 may contain hard faults. Upon receiving a read request, the controller 13 causes reading of data and ECC bits from the memory 12, and these pass through an EDC circuit 15 to detect errors caused by faulty bits in the memory 12 and to correct these bits before true data is sent back to the CPU 10 on bus 11. The memory hierarchy of the CPU, as discussed below, includes a register set 16, an on-chip primary cache 17, and an off-chip secondary cache 18 operated by a cache controller 19.

The computer 9 further includes a bus interface 31 including a main storage adapter 24a and a standard interconnect such as a Small Computer System Interconnect (SCSD 24b typically used to interface main storage sequential access memories such as disks to bus 11. Here the storage adapter 24a and SCSI 24b interface a solid-state disk 20 operated by a disk controller 21 and a magnetic disk 25 operated by a disk controller 26 to the CPU via the bus 11. Blocks of write data from the CPU 10 pass through storage adapter 24a and SCSI 24b to an ECC circuit 22 in the controller 21. The data are stored in the solid state disk along with ECC check bits generated in the circuit 22. Blocks of read data and check bits from the disk 20 pass through an EDC circuit 23 where errors are detected and corrected as will be described. An EDC circuit 23 and the ECC circuit are here used as described in U.S. Pat. No. 5,107,503 assigned to the assignee of the present patent and incorporated herein by reference. The solid-state disk 20 further includes banks of semiconductor memories here dynamic random access memories (DRAMs). The "disk memory" provided by these banks of DRAMs is partitioned to define storage sectors and optionally "tracks" so that a magnetic disk is simulated. Data is stored as sequential blocks rather than as randomly addressed bytes or words. The response time of the solid-state disk to read and write requests however is orders of magnitude faster than a mechanical-driven magnetic disk. Here the banks of DRAMs used to provide the solid state disk 20 may be comprised of DRAM devices which have a rather high level of faulty bits, i.e., hard errors.

As also mentioned above the computer 9 includes bulk storage in the form of the magnetic disk 25, operated by the disk controller 26. While, the magnetic disk 25 is generally less expensive than the solid state disk 20 it is also slower. The solid state disk 20 therefore is used as a cache of a subset of pages of data from the magnetic disk, or pages of data may be swapped between the solid-state and magnetic disks as needed by the tasks executing on the CPU, but in either event the object is to store those data blocks most likely to be used by the CPU in the solid-state disk so access to those data blocks by the CPU will be faster than storing on or retrieving, from the magnetic disk 25.

The CPU 10 of the system of FIG. 1 may be, for example, of the VAX.TM. architecture as described by Levy and Eckhouse in "Computer Programming and Architecture: The VAX", 2nd Ed., Digital Press, 1989. A single-chip CPU of the VAX architecture is disclosed in U.S. Pat. No. 5,006,980, issued to Sander, Uhler & Brown, assigned to Digital Equipment Corporation. The CPU 10 also may be of an advanced 64-bit RISC architecture. Microprocessor devices of this type are manufactured by Digital Equipment Corporation under the designation or part number "21064." Alternatively, of course, the CPU may be of many other types, such as the Intel 386 or 486 architecture, Motorola 68030 or 68040 architecture, or MIPS R3000 or R4000 RISC architecture, as examples.

The system bus 11 may be any of the standard bus specifications used for any of the many commonly-used CPUs, but in an example embodiment is a VAX bus. That is, the bus 11 may be of the type in which addresses, data and commands or controls are multiplexed on a single bi-directional bus of, for example, 182-bits width, or 64-bits width. Alternatively, separate address, data and control busses may be included in the system bus 11.

The CPU 10 operates with a hierarchy of memory resources of differing speeds. The fastest memory is the most costly, so the hierarchy goes from small amounts of fast, costly memory, down to very large amounts of slow, low-cost memory. The fastest memory is the register set 16 which is part of the CPU architecture, directly accessible by instructions of the instruction set. The register set, containing perhaps sixteen or thirty-two registers, typically has an access time 28a that is within a CPU cycle time 28b, i.e., accessed in a time which is a fraction of a cycle or a few nanoseconds. The fastest memory accessed as part of the memory space of the CPU is a memory apparatus generally referred to as the primary cache 17 which is on the same chip as the CPU 10. This cache is accessed in a time 28c corresponding to one or a few CPU cycles. Memory references not found in the primary cache 17 are sought in the secondary cache 18 accessed via the cache controller 19, and the access time 28d of the secondary cache is perhaps several CPU cycles. When a memory reference does not produce a cache hit in the secondary cache 18, the cache controller 19 sends the memory request out on the system bus 11 to the main memory 12, a third example of a memory apparatus. Typically, the response time 28e of the main memory 12 is about ten bus cycles, where a bus cycle on the system bus 11 is usually a multiple of a CPU cycle, e.g., three CPU cycles per bus cycle. Thus, the memory 12 is accessed in about thirty CPU cycles in an example embodiment. Accordingly, the latency introduced by the ECC circuit 14 and the EDC circuit 15 should be small compared to the ordinary response time of the main memory 12 without the EDC added, so that the performance of the CPU will not be impaired due to delays in the EDC function.

The memory hierarchy in the system of FIG. 1 also includes the solid-state disk 20 and the magnetic disk 25 mentioned above. Since a virtual memory management system is ordinarily implemented on the CPU 10, a memory reference to a location in virtual memory that is not present in the main memory 12 is handled by accessing a page from disk storage and writing it to memory 12. The access time 28g for data in the magnetic disk storage is usually measured in several milliseconds when magnetic disks are used, a million times greater than that of the main memory 12. Another level in the memory hierarchy is therefore provided as the solid state disk 20, accessed through the solid state disk controller 21. Here the solid state disk 20 may be comprised of banks of DRAMs containing faulty bits, and ECC circuit 22 and EDC circuit 23 provide check bits and to detect and correct errors in data read from the solid state disk 20. The response time 28f of the solid-state disk 20 is only about a small multiple of that of the main memory 12, allowing for the latency due to the EDC function. In an example, the EDC latency is about 100-.mu.sec.

The width of the data path in the bus 11, in a preferred embodiment, is the same as, or a small submultiple of, a cache line in the cache 18, e.g., 64-bits, 128-bits or 256-bits. It is of course preferable if a single read request on the bus 11 will function as a cache fill, replacing an entire cache line in one operation (or at most two read cycles). When a read miss occurs in the cache 18, a memory read request is passed on to main memory 12 via the system bus 11. The line containing the read request location is accessed from main memory and written to the cache 18, with the requested data being sent on to the CPU from this line.

Referring to FIG. 3, the memory controller 13 for the main memory 12 includes a hi-directional bus interface 31 for coupling to the system bus 11, from which write data is applied by lines 32 to the input 33 of the ECC generate circuit 14. The ECC generate circuit 14 functions to produce check bits on output 34 which are combined with the original data on lines 32 here using multiplexer 35. The ECC circuit is implemented using conventional combinatorial parity tree logic networks. The full write-data block including original data and check bits is applied by bus interface 36 to the read/write data lines 37 going to the DRAM memory banks 38 of the memory 12. Memory control circuit 39 generates memory control signals on row address select (RAS), column address select (CAS), read/write (R/W) and chip select (CS) lines 40 going to the DRAMs. Also, row and column addresses are applied to the banks of DRAMs via the memory controller 39 and lines 41, based on the addresses delivered to the bus interface 31 from bus 11 as parts of the read and write requests from the CPU. In particular, the memory controller 13 is here used to control "main memory." It could also be used to control other memory apparatuses that have relatively fast access times.

An important feature of one embodiment is the ability to do multiple-bit error correction in the EDC circuit 15, using combinatorial logic rather than iterative (sequential) logic. Ordinarily the EDC circuitry used in memory systems in typical computers is so-called SEC/DED or "single error correction, double error detection." The EDC circuit in such case is able to produce corrected data only if no more than a single error is detected, but is able to detect two or more errors and to signal to the CPU that a non-correctable error situation exists so that a fault routine can be entered. Multiple-bit error corrections using binary Bose Chaudhufi Hocquenghem (BCH) codes are discussed in depth in Chapter 9 (p. 269+) of Peterson & Weldon, "Error Correcting Codes," 2nd Edition, MIT Press, 1972. In a preferred embodiment, a 5-bit error correcting, 6-bit error detecting code is employed, with a 182-bit data width plus 41 check bits (ECC bits). That is, the data path width at the lines 32 is 182-bits, and the ECC circuit 14 adds 41-bits, so the lines 37 going to and from the memory 12 are 169-bits wide.

It is important to note that the 169-bit memory blocks (128-bits of data, 41-bit check bit field) stored in the DRAM banks 38 (FIG. 3) (each representing a cache line or submultiple) at address locations 42 which to encompass the entire memory space of the real (physical) memory deemed by the configuration of the CPU 10. This memory space 42 is shown in FIG. 4, having memory address locations going from 00000000 to xxxxxxxx, in a linear fashion, where each address increment is populated by a 169-bit location 43 in the memory banks 38. There are no locations 43 skipped or mapped around, even though faulty bits 44 might exist at various places in each location 43. In contrast to most prior constructions, no attempt is made to "map" the addressing 41 to exclude locations 43 having hard faults 44.

To understand the calculations made to provide the check bits and to detect and correct errors in the data it should be pointed out that in the combinatorial logic networks used herein "modulo 2" arithmetic on a bit by bit basis is used. Addition in "modulo 2" is equivalent to a logical "exclusive or" whereas multiplication in "modulo 2" is equivalent to a logical "and".

The code employed for error detecting and correcting in the preferred embodiment uses Galois field arithmetic over GF(2.sup.8). A check bit generator polynomial for the ECC generator 14 is chosen here to be G.sub.1 (x)=x.sup.8 x.sup.5 x.sup.3 +x.sup.2 +1, a preferred polynomial from primitive, eighth degree polynomials, because it is somewhat easier for combinatorial multiplication in GF(2.sup.8). Let .alpha. be a root of G.sub.1 (x). If the generator polynomial for the full code is G(x), then

G(x)=G.sub.1 (x) G.sub.3 (x) G.sub.5 (x) G.sub.7 (x) G.sub.9 (x) (x+1)

where

G.sub.3 (x) has .alpha..sup.3 as a root=x.sup.8 +x.sup.7 +x.sup.5 +x+1

G.sub.5 (x) has .alpha..sup.5 as a root=x.sup.8 +x.sup.7 +x.sup.5 +x.sup.4 +1

G.sub.7 (x) has .alpha..sup.7 as a root=x.sup.8 +x.sup.6 +x.sup.3 +x.sup.2 +1

G.sub.9 (x) has .alpha..sup.9 as a root=x.sup.8 +x.sup.6 +x.sup.5 +x.sup.4 +x.sup.2 +x+1 thus,

G(X)=X.sup.41 +X.sup.40 +X.sup.39 +X.sup.38 +X.sup.37 +X.sup.36 +X.sup.34 +X.sup.32 +x.sup.31 +x.sup.28 +x.sup.26 +x.sup.21 +x.sup.20 +x.sup.19 +x.sup.17 +x.sup.14 +x.sup.12 +x.sup.3 +x+1

(77262416450013 in octal notation).

This generator polynomial is calculated in the standard way for BCH codes as described in Peterson and Weldon. Thus, during a write to main memory data are passed through the ECC circuit 14 comprising a combinatorial logic parity tree network to form error correcting check bits C.sub.i <40:0> which are associated with a particular string or blocks of data bits D.sub.i <169:41>. The check bits and data are stored in the DRAM's 38. Each of the data bits D.sub.i are "exclusive or'ed" with others of the data bits in three levels of exclusive or gates. The outputs of the three levels of exclusive or gates are applied to one of 41 parity tree generator circuits to generate the 41 check bits of the check code C.sub.i. The exact inputs (i.e. bits of input data) that are applied to each "exclusive or" gate in each bank or level of such gates is given in Appendix I by Tables A-1 through A-6 corresponding to check bits <40:34>; <33:27>; <26:20>; <19;13>; <12:06>; and <05:00>. Preferably, the correcting codes are generated through the ECC circuit 14 over an approximately write cycle-time of the memory apparatus.

During a read operation from the memory 38, the read data D.sub.i and associated code words C.sub.i are applied to an error detection circuit 15 that uses combinatorial logic to correct any errors up to N errors. The maximum number of possible errors that may be corrected (i.e. 2 errors up to 5 and more) depends upon the number of data bits D.sub.i, check bits C.sub.i and complexity of the EDC circuit. Here as an example a 5-bit error correcting cyclic, block, binary BCH codes implemented in combinatorial logic is used.

As in normal BCH decoding the following steps are required, in combinatorial logic implemented in the circuit 15: ##EQU1##

Step #1 is implemented by conventional parity trees, all combinatorial. In a similar manner as was used to provide the checkbits, a combinatorial logic network (as will be described in conjunction with FIG. 6) is used to calculate the syndromes S.sub.1, S.sub.3, S.sub.5, S.sub.7, and S.sub.9.

Step #2, calculation of the coefficients of the error location polynomial (.sigma..sub.i from the syndromes S.sub.i is discussed in Peterson & Weldon, pp. 283-288, with simplifications for the binary case on pp. 299-301. However, the algorithms given are not combinatorial. Note that iterative solutions require some kind of sequential state machine to implement, resulting in time delays that are not acceptable for main memory applications. To achieve a combinatorial solution, a different method is needed. Starting with the equations given on p. 300 of Peterson & Weldon, for Newton's identities (equations 9.54): ##EQU2##

Now for arithmetic in GF(2.sup.8) we have S.sub.2n =S.sub.n.sup.2 and addition is the same as subtraction and ##EQU3##

With these changes, every other one of the prior equations becomes redundant. For 5-bit errors all .sigma..sub.i for i>5 are equal to zero. Hence, the equations for the syndromes become (for 5-bit errors):

.sigma..sub.i =S.sub.1

.sigma..sub.3 +S.sub.1 .sigma..sub.2 +S.sub.1.sup.2 .sigma..sub.1 =S.sub.3

.sigma..sub.5 +S.sub.1 .sigma..sub.4 +S.sub.1.sup.2 .sigma..sub.3 +S.sub.3 .sigma..sub.2 +S.sub.1.sup.4 .sigma..sub.1 =S.sub.5

S.sub.1.sup.2 .sigma..sub.5 +S.sub.3 .sigma..sub.4 +S.sub.1.sup.4 .sigma..sub.3 +S.sub.5 .sigma..sub.2 +S.sub.3.sup.2 .sigma..sub.1 =S.sub.7

S.sub.1.sup.4 .sigma..sub.5 +S.sub.5 .sigma..sub.4 +S.sub.3.sup.2 .sigma..sub.3 +S.sub.7 .sigma..sub.2 +S.sub.1.sup.8 .sigma..sub.1 =S.sub.9

By theorem 9.11 at p. 300 of Peterson & Weldon, these equations can be solved for both 5-bit and 4-bit errors, but not for fewer errors. Since these are linear equations in the S.sub.i and .sigma..sub.i (the S.sub.i are known) determinants can be used to solve.

For 2-bit and 3-bit errors the equations are:

.sigma..sub.1 =S.sub.1

.sigma..sub.3 +S.sub.1 .sigma..sub.2 +S.sub.1.sup.2 .sigma..sub.1 =S.sub.3

S.sub.1.sup.2 .sigma..sub.3 +S.sub.3 .sigma..sub.2 +S.sub.1.sup.4 .sigma..sub.1 =S.sub.5

and for 1-bit error:

.sigma..sub.1 =S.sub.1

The determinants are: ##EQU4## Hence ##EQU5## and the error location polynomial for 4-bit and 5-bit errors becomes ##EQU6## but division is difficult in GF(2.sup.8) in combinatorial logic, so the equation is multiplied by F (F must be non-zero by theorem #9.11 in Peterson and Weldon):

F(.sigma.(x))=Fx.sup.5 +Ex.sup.4 +Dx.sup.3 +Cx.sup.2 +Bx+A

Since only the solutions for .sigma.(x)=0 are of interest, this equation is just as good as the original error location polynomial, and much easier to calculate.

The corresponding determinants for 2-bit and 3-bit errors are: ##EQU7## For the 1-bit error case: .sigma.(x)=x+S.sub.1

Calculating the determinants: ##EQU8##

Thus, Step #2 is reduced to the sub-steps of (a) calculating the determinants, (b) determining how many bits are in error, and (3) selecting a set of the determinants based on the number of errors. Each of these sub-steps can then be implemented in combinatorial logic.

Step #3 requires trying all data bits in .sigma.(x) to find .sigma.(.alpha..sup.N)=0 (for the bits in error). Note that the stored data plus check bits (with no errors) is a code word of the form ##EQU9## where the C.sub.i have been chosen so that CW(x) is evenly divisible by G(x). Therefore, we must evaluate

and test if .sigma.(.alpha..sup.N) is zero for that N.

Suppose K=K.sub.7 .alpha..sup.7 +K.sub.6 .alpha..sup.6 +K.sub.5 .alpha..sup.5 +K.sub.4 .alpha..sup.4 +K.sub.3 .alpha..sup.3 +K.sub.2 .alpha..sup.2 +K.sub.1 .alpha. is a member of GF(2.sup.8), now .alpha..sup.N.K is given by:

where f.sub.i (K,N) is one of 255 combinations of sums (modulo 2) of the K.sub.0. . . K.sub.7 and N is the bit position number (from bit-41 to bit-168 for data) which determines which combination to use.

Hence, the block diagram of the EDC mechanism 15 for combinatorial multi-bit correction is shown in FIG. 5. The 169-bit block returned from the memory array 38 in response to a read request appears on input lines 46, with data bits <127:0> and check bits <40:0>. The syndromes are generated in circuit 47 which is constructed of parity trees, implementing Step #1 as discussed above. That is, combinations of selected bits of the 169-bit input produce each 8-bit syndrome. The output of the circuit 47 includes five 8-bit syndromes on lines 48, labelled S.sub.1 <7:0>, S.sub.3 <7:0>, S.sub.5 <7:0>, S.sub.7 <7:0>, S.sub.9 <7:0>.

Step #2 is implemented using a logic circuit 49 to calculate the determinants, again merely using combinations of selected bits of the syndromes to produce the values A-J, each of which is 8-bits wide, so the output 50 is fifteen 8-bit values A-J. A logic circuit 51 determines the number of errors. Outputs 50 and 52 from the circuits 49 and 51 are applied to a block of multiplexers 53 that selects equation coefficients based on the error count, producing an output 54.

Step #3 is implemented in a logic circuit 55 which forms exclusive-OR combinations of each coefficient. A logic circuit 56 receives the outputs from the circuit 55, and also the data bits <127:0> from the input 46, and produces corrected data on output 57. That is, coefficients A-J, syndrome S1, and error counts are applied to multiplexer bank 53 which in response to error count chooses coefficients for the error location polynomial .sigma.(x). At the output 54 of the multiplexer bank is the proper error location polynomial coefficients A-J, S1 provided on outputs X.sub.5, X.sub.4, X.sub.3, X.sub.2, X.sub.1, and X.sub.0. Equation coefficients (solutions to the determinants) are associated with X.sub.5, X.sub.4 . . . X.sub.0 in accordance with the error count as given by Table B below. Unused coefficients are outputted as zeros, "0". The circuit 56 is repeated 128-times, once for each data bit.

A combinatorial logic circuit 55 is used to provide all possible "exclusive or" combinations of the coefficients of .sigma.(x). These "exclusive or" combinations represent all possible coefficients of the equation (.alpha..sup.N.K) given above. A combinatorial logic circuit 56 is used to test each bit position by forming the exclusive or of certain combinations of these coefficients of (.alpha..sup.N.K) selected based upon bit position N for an error in bit position N. If the "exclusive-or" of these coefficients is zero "0" than an error in bit position N is indicated. The error in bit position N is corrected by inverting bit (N-41) of data bits <127:0> to provide the corrected bit on output 57.

The error count determined in circuit 51 is based on certain observations. Since x+1 is a factor of G(x), an overall parity check of all data and check bits will determine whether there are an odd or even number of bits in error: ##EQU10##

As an example the decoding of multiple bit error correcting codes as described above with combinatorial logic can be accomplished by using high density integrated circuit gate array technology. In particular, for the example described above using 128 bits of data requires a check bit field of 41 bits using a block, cyclic, BCH binary code as described. A combinatorial logic circuit using approximately 87,000 logic gates can be provided to correct 5 bits in error and detect 6 bits in error.

Referring now to FIG. 6, a circuit to provide syndromes using combinatorial logic is shown to include a plurality of levels of 112a, 112b, . . . 112i of banks of "exclusive or" .sym. gates. The first level or bank 112a is a single deep bank of exclusive or gates which are fed data bits D000-D127 as well as corresponding check-bits COO-C440 and form many combinations of the check-bits and data-bits. The output from the first level 112a of exclusive or gates are thus exclusive or'ed combinations of the data-bits and check-bits. These combinations are fed to a second level of exclusive or gates to form additional combinations by exclusive or'ing the outputs from the previous or first level of exclusive or gates. The outputs from the second level of exclusive or gates are fed to a subsequent level of exclusive or gates here the subsequent level being a third level of exclusive or gates to form exclusive or combinations from the outputs of the preceding level. These outputs are then exclusive or together and fed to a bank of odd and even parity circuits and associated "exclusive or" gates as needed to form the syndromes as S.sub.1 <7:0>, S.sub.3 <7:0>, S.sub.5 <7:0>, S.sub.7 <7:0> and S.sub.9 <7:0>. It is to be noted that the above nomenclature S.sub.1 <7:0> corresponds to here the first syndrome 51, bits 7 to 0. Noting that the code word CW(x) is as given above including checkbits C.sub.i and data D.sub.i, the data read from the memory will have the same code word plus an error polynomial E(x). Read Data=CW(x)+E(x) The syndromes are thus:

S.sub.1 =Read Data (.alpha.)

S.sub.3 =Read Data (.alpha..sup.3)

S.sub.5 =Read Data (.alpha..sup.5)

S.sub.7 =Read Data (.alpha..sup.7)

S.sub.9 =Read Data (.alpha..sup.9)

Noting that each data and checkbit may or may not contribute to any bit of each syndrome S.sub.1, S.sub.3, S.sub.5, S.sub.7, S.sub.9 and that each syndrome is an 8-bit member of GF(2.sup.8). Thus, a syndrome may be viewed as a member of GF(2.sup.8) which contains information about the errors and location of errors. The syndromes are logically manipulated in the circuits of FIG. 5 and as will be further described below, to extract the error information in a form which the circuit 56 (FIG. 5) can use to correct any errors.

For the check bits (i=0 to 40) the contribution to a syndrome K is given by H(i,K)=.alpha..sup.i,k

For the data bits (j=0 to 127) the contribution to syndrome K is given by H(i,k) =.alpha..sup.(j+41).K Each of the H values above is a member of GF(2.sup.8). That is each H is an eight bit vector whose non-zero elements indicate which syndrome bit's parity tree requires that data bit or check bit for an input. The combinations of bits which are exclusive or together are set forth in Appendix II Tables C-1 through C-5 for syndromes S.sub.1, S.sub.3, S.sub.5, S.sub.7, and S.sub.9 respectively.

Although circuits such as ECC generate circuit 14 are conventional it should be noted that here circuit 14 is implemented using combinatorial logic in a similar manner as the syndrome generator circuit 47, as levels of "exclusive or" gates and "parity tree circuits" (not shown). Again noting that the code word CW(x) is as given above, it should be recalled that CW(x) is evenly divisible by G(x). Accordingly, given D.sub.j (the data bits) C.sub.i the check bits are chosen so that CW(x) is evenly divisible (no remainder) by G(x). Each data bit may or may not contribute to the particular parity tree that provides each check bit. For each data position D.sub.j <127:00>X.sup.j+41 is divided by G(x). The results are a quotient (which is discarded) and a remainder polynomial of degree 40 or less (since G(x) is of degree 41). The non-zero terms of the remainder polynomial indicate which check bit parity trees should have D.sub.j as an input.

Referring now to FIG. 7 syndromes S1, S3, S5, S7, S9 are fed to a bank of GF(2.sup.8) multipliers as well as a bank 122 of GF(2.sup.8) "powers" banks 124. The multiplier bank 122 is comprised of a plurality of GF(2.sup.8) multipliers that multiply two inputs on a bit by bit basis providing the product of two inputs here two syndromes illustratively S1 and S3. The multiplier bank 122 has a sufficient number of multipliers such that all necessary multiplications as given by the calculated determinants A-J, mentioned above, are provided.

Similarly, the powers bank 124 is provided to form powers of the syndromes S1, S3, S5, S7, S9 as required by the equations A-J mentioned above. Thus, for example S1.sup.2 is required in several of the equations A-J. Equations A-F also require S1 to be raised to other powers. These powers of S1 are provided by using a plurality of circuits which can raise S1 to a power. Similarly, such circuits are also provide to raise others of the syndromes S3, S5, S7, and S9 as necessary to powers. The outputs from the multiplier banks and power banks are fed to a second bank of multipliers 126 to form the product terms in the equations A-J mentioned above. These product terms are fed to a bank 128 of GF(2.sup.8) adders which is comprised of a bank of exclusive or gates to add these selected ones of these terms to form each of the equations A-J mentioned above. Thus, using equation J as an illustrative example a term S3 will be added to the third power of S1 by an element in the adder bank 128.

Circuit 51 is also fed selected products of the syndromes, as shown for the equations discussed above in connection with the technique for determining the error count. The error count circuit is a bank of exclusive or gates and "and" gates and is used to evaluate each of these equations to determine whether the syndromes indicate 1, 2, 3, 4, or 5 or 6 or more bits in error. The bank 51 provides error enable signals E.sub.1 to E.sub.n. At the output of the adder bank 128 is provided all of the possible equations coefficients for the error location polynomial. Outputs of circuit 128 are thus fed to a bank of multiplexers with each bank of multiplexers having an output representing a coefficient X.sub.i of the error location polynomial .sigma.(X). Each coefficient X is 8-bits wide and accordingly the bank 53 of multiplexers comprises a plurality of multiplexers arranged as a first set of multiplexers 130a-130g corresponding to the coefficient X0<7:0> through multiplexers 135a-135g corresponding to coefficient X5 bits <7:0>. The error count circuit 51 provides signals E.sub.i which are fed to the select inputs of each of the multiplexers in bank 53 to choose appropriate ones of the coefficients formed from the GF(2.sup.8) adder bank 128. The coefficients fed through the outputs of the multiplexers in bank 153 are thus determined based upon the error count as described above.

Referring now to FIG. 8 and FIGS. 8A through 8F, an illustrative example of a multiplier circuit which can be adapted to provide a power circuit is shown to include a first bank 142 of here "nand" gates (for low level assertion logic) of which 8 of said gates are shown but it is to be understood that each gate shown represents a vector of 8 additional gates which can be viewed as coming out of the page towards the reader. The inputs to each of these gates are the bits of 2 polynomials A<7:0> and B<7:0>. Selective ones of each of the combinations of these bits accordingly are nand'ed together where here the function is used is for low level assertion corresponding to a logic level one, to provide a plurality of multiplicative bit-by-bit combinations as shown at the outputs of gates 142A. These multiplicative bit-by-bit combinations are fed to a bank 144 of exclusive or gates to form "exclusive or" sums of selected ones of the bit-by-bit multiplications. The outputs of these exclusive or gates are fed to a second bank of exclusive or gates 146 with said banks 146 being several levels deep of "exclusive or" gates, as shown to form an output polynomial Z<7:0>. This illustrative example of multiplication in GF(2.sup.8) can be adapted to provide other multipliers to form the other products required by the multiplier bank 122. Similarly, this multiplier circuit can be adapted to provide powers bank 124 by changing the inputs on the circuits.

Referring now to FIG. 9, a circuit 55 to form an exclusive or combination of each of the coefficients X1<7:0> to X5<7:0> is shown to include here 3 levels 152, 154, 156 of exclusive or gates with each of said levels of exclusive or gates comprised of 5 banks of exclusive or gates 152a-152e, as for example for level 152. Such banks are provided for each of the coefficients X1-X5. At the last bank 156 of exclusive or gates are provided exclusive or'ed combinations of each of the preceding outputs from bank 154. These values are thus grouped together on a bit-by-bit basis for each of the error location polynomial coefficients .alpha..sup.N X1, .alpha..sup.2N X2, .alpha..sup.3N X3, .alpha..sup.4N X4, .alpha..sup.5N X5 to provide the coefficients A<7:0>-E<7:0> corresponding to terms of equation .sigma.(X) . These values as well as the coefficient X0<7:0> are fed to a bank of error correction circuits 162. Here bank 162 includes a plurality of circuits 162.sub.0 -162.sub.127. That is one correction circuit is provide for each bit of data in the data field. Here since the data field is 182-bits wide, 128 circuits are provided.

An illustrative one of those circuits 162.sub.i is shown in FIG. 10 to include a first bank 164 of exclusive or gates which are fed the polynomials A<7:0>-E<7:0> as well as X0<7:0>. The bank 164 is comprised of 8 levels of exclusive or gates. Thus, it can be pictured that the "exclusive or" gates have 8 levels of gates coming out of the page towards the reader. Each one of the exclusive or gates has one of the bits A0 -A7 and B0-B7 fed to the respective ones of the inputs of the gates as shown. Outputs of each of said exclusive or gates of which there are 32 here and of bank 164, are fed to corresponding inputs of one of here 8 multiplexers in a bank 166 of multiplexers. The each of the outputs of the eight multiplexers are fed to one input of two four input NAND gates 167a, 167b. Depending upon the evaluation of the exclusive or combinations of the coefficients A-E and X0 if an error occurs in the bit being corrected, the outputs of gates 167a and 167b will be 00 thus choosing path D0 of a multiplexer 168. Multiplexer 168 also has inputs D1 to D3 fed from a buffer 171 to feed the raw data from the memory. The raw data is also fed to a multiplexer 172 which provides a compliment of the data at its output. Multiplexer 172 provides the compliment of the data read from the memory. Accordingly for the situation where the outputs of nand gates 167a, 167b are both 0, the D0 position of the multiplexer 168 is chosen by the select inputs A,B coupling the output of the multiplexer 168 and thus the complimented version of the raw data from the memory through the multiplexer to line CDXXX, providing a corrected bit of data. If the evaluation at the nand gates 167a, 167b rams up either one or both of the outputs of said gates as being a logic 1 then the data is fed through lines D1, D2 or D3, and the true version of the data was read from the memory and is fed to the output.

It will now also become apparent to one of skill in the an that depending upon the degree of confidence desired in the memory system, the level of defects which may be tolerated in the memory devices, and the width of the data words, a larger number or smaller number of bits can be corrected and correspondingly detected by use of the above circuits using different values for the parameters. Thus, for example, if it is desired to provide a higher degree of confidence in the 128 bit wide field, a wider check bit field can be employed such as 49 bits to detect the presence of seven errors and correct six errors in data. Alternatively, a smaller check bit field can be provided such as 25 bits wide to correct three errors and detect the presence of four errors for the 128 bit wide data field given as the example. That is, in GF(2.sup.8) arithmetic eight bits per error plus an additional bit are needed to correct and detect errors. Thus, for 5 errors 5.times.8+1 or 41 bits are needed, as mentioned above. Alternatively, for wider data fields such as 256 data bits, GF(2.sup.9) arithmetic using 46 check bits to correct five errors (5.times.9+1=46) and detect six errors could be used. The exact scheme and hence logic network employed will thus be dependant upon the system requirements set out by the designer.

Referring to FIG. 12, a controller 21 for the solid state disk 22 is shown to include a bus interface 33 (modules 24a, 24b) which interfaces the controller to a system bus 11. A converter or data formatter 34 is provided and is used to receive illustratively 16-bit data words via the bus interface 33 and convert the 16-bit data words into 10-bit symbols for use in the error correction code circuit 22. These 10 bit symbols are also fed to a first input of a multiplexer 38. The formatter 34 collects 10, 16-bit data words received through bus interface 33 and sequentially outputs 10-bits of data for each ordered position of the original 16-bit data word. Thus, each 10-bit symbol comprises the I.sup.th location of the 10, 16-bit data words fed to the formatter 34. These 10-bit symbols are fed to the ECC error correcting code check bit generator circuit 22 to produce error correcting code symbols of ten bits along bus 37 which are fed to a second input of the multiplexer 38. The 10-bit data symbols are also fed along bus data path 35 to the first input of the multiplexer 38, as mentioned above. The multiplexer 38 channels the data symbols to a converter 31 which converts the data words back from 10-bit symbols to 16-bit data words for storage in the DRAM banks 41 as will be described. Correspondingly, after all the data in a block has passed through the ECC circuit 22, the error correcting code check bit symbols provided from the error correcting code circuit 22 are likewise converted to 16-bit words in converter 31 and stored in DRAM's 41. It should be noted that the controller 21 operates on blocks of data. Illustratively, 512 BYTEs of data can comprise one block. A preferred circuit for generating the ECC check bits is described in the U.S. Pat. No. 5,107,503, mentioned above. Other error encoder and decoder circuits can be used such as a 8-error Correcting Reed--Solomon Codec, part number L64710 from LSI Logic, Inc. Milpitas, Calif.

As indicated above the symbol data and associated error correcting code check bits are then reformatted in formatter 31 into 16-bit or other suitable data words to be stored in the DRAM modules 41. During a read operation from the DRAM banks 41 data from the DRAMs banks 41 are fed through the data interface 39 to the formatter circuit 45. The formatter circuit 45 here converts 16-bit data words into 10-bit symbols as similarly described above for converter 34 that is the formatter 45 obtains 10 16-bit data words and outputs 16 10-bit symbols. The string of 10-bit symbols representing the block of data read from the DRAM bank 41 as well as its associated check bit symbols are applied to error detection and correction circuit 23 and to a buffer 48. The output of the error detection and correction circuit 23 is coupled via a data path 47 to an exclusive or circuit 50 as is the output of the buffer 48 via the data path 49. Corrected symbols if any are provide from the error correction detection circuit 23 and the original data symbols are provided on lines 49 sequentially to inputs of the exclusive or circuit 50. If the original data is correct as is the instance in the vast majority of cases, the output of the exclusive or circuit 51 will be unchanged. However, if an error was detected for the symbol it will be corrected by performing an "exclusive or" of the symbol in error provided from lines 49 with a correction vector provided by error correction circuit 23. Converter 52 is fed 10-bit correct symbol data via data path 51. The converter 52 converts the 10-bit symbol data into 16-bit or alternatively 32-bit, 64-bit, or 182-bit wide format to send to the bus interface 33 as was generally explained for converter 31. The exact conversion provided by converter 52 is dependant upon the bus width 11.

A preferred example of the formatter 52, formatter 34, ECC generator circuit 22, and EDC circuit 23 are described in U.S. Pat. No. 5,107,503 assigned to the assignee of the present ind EDC circuit 23 are described in US Patent 5,107,503 assigned to the assignee of the present invention and incorporated herein by reference. Using the above described patent, EDC circuit 23 would use a Reed-Solomon code on 10-bit symbols and associated error correcting code check bit symbols to correct errors from here a solid state disk. Further in the above patent only two formatters between the CPU bus and the controller are used. Here the circuit is modified somewhat to include two additional formatters between the DRAM banks 41 and the controller 21, since the patent describes and application using a magnetic disk which stores data serially, rather than semiconductor, DRAM's that generally store data in parrallel words. The outputs from the storage portion of the solid state disk (DRAM banks 41 ) and associated check bit symbols are fed to an syndrome generator (not shown here). The syndromes are applied to an error locator computer (not shown here) which calculates the error location and a correction vector for the data held in the buffer 48. The correction vector is exclusive or'ed with the buffered data in circuit 50 to provide correct data which are fed to a converter 52. Converter 52 converts the 10-bit symbol data into 16bit wide data segments. As just mentioned, the described circuit in US patent 5,107,503 does not however include the converters 31 and 45 which convert the 10-bit symbol data to 16-bit data for storage in the DRAMs and provide a conversion to take 16-bit data and convert it into 10-bit symbol data to be fed to the EDC circuit 23, respectively. These converters 31 and 45 however are similar to the converters 52 and 34, respectively. That is converter 31 provides an equivalent formatting function as converter 52 and converter 45 provides an equivalent formatting function as converter 34. The above described patent implements in sequential logic a Reed-Solomon code to correct and detect up to 32 symbols in error per block of data where a block is comprised of 413 data symbols. The circuit implements a symmetric, sequential ReedSolomon code over the Galois Field GF(2.sup.10). Alternatively, any error correcting block, non-binary code may altematively be used to provide error correction detection in the controller 21.

Still referring to FIG. 11, the solid-state disk controller 21 has a bidirectional bus interface 33 for coupling to the system bus 11, from which write data is applied to converter 34 to form 1 0-bit symbols for use in the ECC generate circuit 22. The 10-bit symbols are applied by lines 35 to the input 36 of the ECC generate circuit 22. The ECC generate circuit 14 functions to produce sixty-seven 1 0-bit symbols of check bits on output 37 for each data block, which are associated with the original symbols of data on lines 35. The 10-bit wide data path 37 may be changed in a converter to 16-bits wide or other format ff the DRAM storage uses something other than the 10-bit symbols as input/output. In any event, the write data is applied by data interface 39 to the read/write data lines 40 going to the DRAM memory banks 41 of the memory 12. Control circuit 42 generates memory control signals on Row Add (RAS), Col Add (GAS), Read/Write (R/W) and Chip Select (CS) lines 43 going to the banks of DRAMs. Also, row and column addresses are applied to the banks of DRAMs via the controller 42 and lines 44, based on the addresses delivered to the interface 33 from bus 11 as part of the mad and write requests from the CPU. Conversion between sector addresses and memory bank addresses are made by the controller 21 (FIG. 1 ) using conventional techniques. A preferred technique for packing symbols in DRAMs is described in U.S. Patent Application Serial No. 652,870 filed Feb. 1991 and incorporated herein by reference.

The data processed in the ECC circuit 22 for storing in the solid-state disk 20, in one embodiment, results in sectors in the solid-state disk formatted as 512-bytes of data and 84-bytes of ECC check bits (plus 2-bits extra), but of course these have been converted from symbols of 10-bits processed in the ECC circuit 22 and on lines 35-37. This means 41 0-symbols (1 0-bits per symbol) of data, generating 67-symbols of ECC check bits, provide the content of a sector. This level of coverage can correct (in a sector) up to thirty-two symbols having errors.

A read request sent by the CPU 10 on bus 11 to the solid-state disk 20 via the storage adapter 24a and SCSI 24b is interpreted by the bus interface 33 and control circuit 42 to generate an address on lines 44 and controls on lines 43 to retrieve the sector requested, so data is returned on data I/O lines 40 and data interface 39 in I5 whatever format used in the DRAM banks 41, then converted back to 1 0-bit symbols in converter 45, producing 10-bit wide symbols clocked in sequence onto lines 46. The EDC circuit 23 receives the 41 0-symbols of data followed by 67-symbols of ECC check bits of this sector from lines 46, and produces corrected symbols on lines 47 ff errors are detected in the symbols. In the example for a data block of 410 symbols, 10-bits wide, 67 symbols, 10-bits wide of check bits can detect and correct up to 32 symbol errors if present. Ten bit wide symbols of a GF(2.sup.a.degree. ) Galois Field are used as an example. Altematively smaller and hence less complicated symbols can be used to correct errors. For example, an 8-bit wide symbols using GF(28) Galois Fields can be used to correct errors in a block of size of 128 symbols. Altematively, three eight bit GF(2.sub.8) code word fields may be used to correct symbols in a block of up to 512 symbols including check bit symbols. This could be accomplished by intefieaving the symbol data among the three code word fields such that each third symbol contributes to one of the three code word symbol fields. The above mentioned LSI, Inc circuit could here be used.

The 41 0-symbols of read data on lines 46 from the DRAM banks is also stored in a buffer 48 for the latency period (about 100-.mu.sec as an example) of the EDC circuit 23 and then clocked out in sequence on lines 49. Corrected symbols from EDC circuit 23 on lines 47, and original data symbols on lines 49, are applied synchronously to inputs of the exclusive-OR circuit 50, so ff the original data is correct (as will be true in the vast majority of cases) it is applied unchanged to output lines 51, while if an error was detected for a symbol it will be replaced by corrected data from the EDC circuit. Data on the output lines 51 of the exclusive-or circuit 50 is converted back to 32-bit (or 64-bit, or 128-bit) wide format in converter 52 before being returned to the system bus 11. It should also be noted at this juncture that these error correction techniques could be implemented in hardware as describe or fLrrnware under control of a microprocessor.

It is important to note that sectors (512-bytes of data, 84-bytes of check bits) stored in the DRAM banks 41 are addressed by lines 44 to encompass the entire address space of the array of DRAM devices in the DRAM array. This address space 55 is shown in FIG. 4, going from 00000000 to xxxxxxxx, in linear fashion, where each address increment is populated by a sector location 56 in the memory banks 41. There are no locations 56 skipped or mapped around, even though faulty bits 57 might exist in various symbols in the sectors 56 throughout the address space 55. These faulty bits can exist in locations where the data symbols and the check bit symbols are stored. This is in contrast to prior solid-state disks of this general construction. Ordinarily sectors having hard errors are mapped around, i.e., theft addresses are stored in a table of bad sectors in non-volatile storage so that the location is never used but instead a substitute location is referenced whenever the address points to a faulty location identified from the table. Techniques which detect bad sectors and avoid using of these bad sectors maybe also advantageously employed in a solid stand, i.e., theft addresses are stored in a table of bad sectors in non-volatile storage so that the location is never used but instead a substitute location is referenced whenever the address points to a faulty location identified from the table. Techniques which detect bad sectors and avoid using of these bad sectors maybe also advantageously employed in a solid state disk system incorporating the features of the invention. With the above arrangement, DRAMs having known bad bits may be used to provide the DRAM banks 41, and these DRAM devices need not be permanently mapped around or excluded from operating use.

Advantages of the present invention will now become apparent. For the main memory controller of FIG. 3, the array of memory devices associated with that memory may have bits which are known to be defective for any reason. Assuming a 5-bit correction, 6-bit detection EDC circuit 15 is used, various levels of defective bits can be tolerated in a memory system depending on the distribution of errors and the degree of confidence needed in the manufacture of the main memory system. The distribution of faulty bits in 169-bit blocks of memory, assuming a certain level of bad bits, can be calculated. For example, if 0.100% of the bits are defective (1-of-1000), assuming random distribution, in 16 Meg code blocks 43 of 169-bits each, there would be a distribution of code blocks as seen in Table D. It is seen that there would be 14,167,310 code blocks with zero defects, 2,396,672 with two bad bits, etc. There is on average less than one bad code block with six bad bits in 16 Meg blocks. Six bad bits are not correctable in the example implementation given above. Thus, a memory system of 16 Meg blocks, 128-data-bits per block, i.e., 256-MBytes of main memory 12, would be marginally possible at this level of defects; about one of two boards would work. Still, this is an extremely high defect density, 0.100% of bits faulty is 4000 bad bits in a 4 Mbit DRAM, whereas DRAMs are ordinarily sold with zero bad bits (indeed, a 4 Mbit DRAM device with one bad bit is usually considered trash, unless sold as an "audio RAM").

Another example is illustrated in the data of Table E. Here the defect density is assumed to be 0.010%, or 400 bad bits in a 4 Mbit DRAM (one bad bit about every sixty 169-bit blocks), still a very large number of defects. The statistical prediction for this level of defect density is that there would be 16,496,049 code blocks with no defects (16 Meg is 16,777,216), 140,581 blocks with one bad bit, 590 with two bad bits, one with two bad bits, etc. Only one 256 MByte memory system in ten million such systems would exhibit a non-correctable hard error detection of 6-bits. This would of course be an acceptable level for economical production of such memory systems. Indeed, it is expected that defect densities of much lower than 0.010% can be produced by DRAM manufacturers at costs of substantially less than the current cost of DRAMs with zero bad bits.

The statistical data of Table E shows that an EDC circuit 15 which produced 4-bit correction, 5-bit detection would be acceptable; only three of one thousand systems would have 4-bits faulty, and only five of a million systems would be fatally defective, exhibiting 6-bits faulty and thus uncorrectible. Of come, soft errors will occur due to alpha particles, and these will be in addition to the defect density assumed in the calculations. Therefore, to be assured of an adequate margin of error, it is expected that an EDC circuit 15 that will correct at least three errors will be needed for an economical large system.

Further advantages of the present invention will now become apparent. For the solid state disk memory controller of FIG. 12, the array of memory devices associated with that memory may have bits which are known to be defective for any reason.

Assuming that a certain level of error detection and correction is provided by the circuits of FIG. 12 a given level of defects can be tolerated in the memory devices of the solid state disk. The distribution of faulty bits in 512-symbol code blocks of memory, assuming a certain level of bad bits, can be calculated. For example, assume that a 204-Mbyte solid-state disk is to be constructed, using 16-Mbit DRAMs. Referring to Table F, assume that 1% of the symbols have a bad bit or bits, which is a rather high fault rate. This 204-Mbyte disk will have 417,792 code blocks of 512-symbols per code block. In this case, calculating the distribution, only 2433 code blocks will have zero bad symbols. 12,583 will have one bad symbol, 32,476 will have three, etc. As expected, the highest probability (73,563) is that of having five bad symbols in 512 symbols (1%). The probability of having more than thirty-two bad symbols in any code block of the 512 is very, very low, however (one per many billion systems constructed) so systems could be economically manufactured using this level of faulty bits in DRAMs.

Another example is illustrated in Table G, where the defect density is assumed to be 0.1% bad symbols. This would be 400 bad bits in a 4-Mbit DRAM, or one bad bit about every 10,000 symbols. It is seen that 250,316 code blocks have no bad symbols, 128,290 have one bad symbol, etc. Virtually no blocks have more than ten bad symbols. Thus, at this level, a detecting and correcting mechanism which corrects much less than the 32-symbols mentioned above would be adequate for economical manufacture of systems. Indeed, a level of ten or twelve would seem to be acceptable.

The ability to use memory devices such as DRAMs having hard faults in either main memory 12 or the solid state disk 20, without a mapping mechanism for removing the bad location, sectors or symbols from the address space of the DRAM array 41, may make wafer-scale integration economically feasible. A wafer 60 as seen

in FIG. 11A contains a large number of DRAM memory arrays 61 in undivided form, each device containing perhaps a 4 Mbit or 16 Mbit array of cells. Thus, the entire wafer 60 may contain perhaps several hundred megabytes of DRAM memory. It has been previously proposed to utilize a wafer in undivided form, instead of scribing and breaking into individual chips which are then packaged. However, when the system requirement is that all bits be good, then some mechanism has to be provided to work around the inevitable bad bits or chips having bad bits. Such a mechanism results in added interconnections to the DRAM devices, in order to individually select devices so that bad devices may be deselected. The ability to use all of the devices radically changes the interconnection scheme needed, and thus changes the economics of manufacture of wafer-scale integrated DRAM memory systems for solid-state disk or the like.

Referring to FIG. 11B, an individual die 61 in the wafer 60 has a number of pads 62 which in an individually packaged device are used for bonding to a lead frame, as by small gold wires. For a 4 Mbit DRAM, the number of address bits needed is eleven (multiplexed row and column addresses) and the number of control bits is usually five (RAS, CAS, R/W, CS, OE), plus power supply Vdd and Vss, and a data I/O connection (or separate dam-in and data-out connections, or by-4 or by-8 parallel data I/O connections). The total connections to a 4 Mbit-by-1 device are thus nineteen or twenty. A 16 Mbit device needs one more address bit (multiplexed). In undivided form in the wafer 60, instead of bonded connections to a lead frame as used in conventional packaged DRAMs, buses must be provided on the wafer 60 to all of these nineteen pads 62 per die 61 by another level of metallization. The die 61 need not be individually selected by addressing lines, however, because the same 11-bit address may be applied to all 150 -or-200 or so die on the wafer 60, and since the data input/output is perhaps 64-bits or 182-bits wide, then perhaps the only address selection is all of the die on a wafer 60, or half of the die on a wafer, for a given address. Individual chip-select signals thus need not be routed to every chip, but instead only a few chip select signals may be bussed to all die in common. This reduces the overhead of interconnections, compared to a situation where all bits must be good and certain die 61 must be mapped around.

Construction of a wafer-scale integrated DRAM unit for a solid-state disk 20 where a level of bad bits of perhaps 0.02% is present is therefore greatly simplified. The wafer 60 is tested at the probe stage, where the pads 61 are available (not yet covered) to see if all die on the wafer meet the 0.02% level (or whatever level is specified). This is quite likely to be almost all wafers. If there are 200 die per wafer, and the yield of die with all good bits is, say, 80%, then the likelihood of getting a wafer with all good die is minuscule, but if 32-symbols are bad per 512 is acceptable, and the most common failure (90% of bad die) is 1-bit or two bits bad, then the likelihood of a wafer being acceptable can be calculated to be reasonably high. A wafer-scale integrated memory device is thus practical and economical.

Referring now to FIGS. 13 and 14, a data formatter 70 preferred for use in the memory controller 21 of the solid state disk memory 20 in particular for converters 31 and 45 is shown to include a control logic circuit 72 including a counter 73 and a logic array decoder 72a. Logic circuit 72 as well as a formatter array 80 are provided in a gate array circuit. The logic array decoder is fed by data MEMTYP which indicates the type of memory used in the DRAM banks 41 (FIG. 3). That is the decoder 72 is fed a code here from boards (not shown) of the memory banks 41 which indicate the configuration of the memory chips used in the memory bank 41. Illustrative examples include memory chips configured as X.times.1 bit, X.times.4 bits, and X.times.8 bits, for example. The described formatter 70 permits the memory controller 21 to be used with various configurations of DRAM. All that is necessary is to specify the memory type to the control logic of the formatter. Here data are fed into decoder 72 along lines MEMTYP. Three or four bits of data can be decoded to indicate the type of memory currently being serviced by the memory controller 21. The control logic 72 also is fed by a signal on line R/W which is used to indicate whether a read or write is occurring.

A clock signal is fed the logic array decoder 72a. The logic array decoder 72b in response to the decoded MEMTYP bits, R/W and clock signals provides multiplexer enable signals along lines MUXEN00 to MUXEN22. Selected ones of these lines are used to select data paths for elements of a formatter array 80. Counter 74 is used to keep track of the number of symbols or the number of words loaded or read from the array as will be described. The control logic 72 includes a second counter 73 which issues addresses to the control logic array 72. Logic array 72 uses these addresses to issue in a proper sequence the various MUXEN signals number of the word or symbol. Accordingly, it is noted that the formatter counter 73 counts symbols read or written in the array 80.

As illustrated in FIG. 13, a typical array element 82 includes a data selector or multiplexer 82a and a single bit storage element here a D flip-flop. The flip-flop changes state via the clock signal CLK and thus loads the output of the MUX 82a. Here a three input MUX 82a having inputs 82', 82", and 82'" is shown, however most of the array elements in the array will have only two inputs that are selected between by the MUXEN signals. The MUXs are here used to permit the data in array 80 to be shifted left or down depending on the particular circumstance, although shifting right and up could have been provided by appropriate connection of the array elements 82. That is the MUXs permit multiple data paths to exist in the array. The MUXEN signals are issued synchronously with the clock, via the register 76.

Referring now to FIG. 14, the array 80 is shown with some of the elements 82.sub.ij present and the data paths used to interconnect them. The array 80 is shown to include external lines IS00 to IS09 and IS'00 to IS'09 used in input symbol data during each of two phases of a symbol to data word conversion. The formatter array 80 also includes lines WO00 to WO15 and WO'00 to WO'15 used to output convert data words from the array 80 during each of two phases of the conversion. The formatter also includes lines WI00 to WI15 and WI'00 to WI'15 used to input data words and SO00 to SO09 and SO'00 to SO'09 used to output the convert symbols during each of two data word to symbol conversion. This permits data to be formatted from symbol data to memory data and vis-a-versa. It also permits data to be read from the array while the next burst of data is being written into the array 80.

In particular elements 82.sub.00 to 82.sub.15,0 of a first column "0" of the array 80 are shown having two data inputs. A first input to each element is from an adjacent element in its corresponding row on that element's right or the succeeding element, and the second is, for element 82.sub.15,0 from symbol line IS00, and for preceding elements 82.sub.0,0 to 82.sub.14,0, the second input is from the preceding one of the elements 82.sub.1,0 to 82.sub.15,0 in the same column. This permits symbols from line IS00 and for the remaining elements 82 of symbol lines IS01 to IS09 to be shifted down and to the left during a symbol to data word conversion. Correspondingly, elements 82.sub.0,0 to 82.sub.0,09 have two inputs one is lines IS0 to IS9, and the other inputs are the output of the succeeding one of said elements 82.sub.0,01 to 82.sub.0,09 for elements 82.sub.0,00 to 82.sub.0,08. For elements 82.sub.0,09 its second input in the data line WI'15. This arrangement permits left shifting during symbol to data word and data word to symbol conversions. The remaining array elements 82.sub.ij are connected in a corresponding manner, as shown for exemplary ones of said array elements 82. Here, for conversion between 16 bit data words and 10 bit symbols, the array contains 220 elements. That is the array 80 is 16 array elements.times.16 array elements, with a section of 6 array elements.times.6 array elements omitted. This arrangement is less costly and saves space.

It is noted that elements 82.sub.0,9 to 82.sub.9,9 and elements 82.sub.9,0 to 82.sub.9,9 are elements having a three input MUX. The third input of these elements is from WI<15:0> and bits 0 to 9 of WI<15:0>.

In operation, the formatter receives data either from a memory bank 41 or as symbol data from the ECC 22. As an example, if symbol data is fed to the array 80 the array 80 under control of the logic circuit 72 reformats the data as words to be stored in memory. In particular, here 16, 10 bit symbols are loaded in the array by storing the first data symbol in elements 82.sub.15,0 to 82.sub.15,09. This symbol is then shifted down to the next row of ten elements i.e. 82.sub.14,0 to 82.sub.14,09, while the next symbol is loaded into the elements 82.sub.15,0 to 82.sub.15,09. This proceeds until the 16 symbols have been loaded. When all 16 symbols have been loaded, 10, 16 bit data words are shifted out along lines WO00 to WO15 by shifting left the data stored in the appropriate array elements 82. That is the stored data in the array elements 82 mentioned above are now shifted left by columns to a preceding one of the columns. As the data words are shifted out of the array 80, a new set of symbols can be loaded into the array along lines IS'00 to IS'09 and will in turn be read out along lines WO'00 to WO'15, during a subsequent formatter phase. The address counter 73 is incremented each time a symbol is loaded into the array 80 and thus during writing of that portion of the array the counter 73 keeps track of the number of symbols and addresses the logic circuit to provide the appropriate inputs to the circuit which forms the correct MUXEN signals as outputs to the array. This sets up the input path to said MUX for the next data shift sequence on the array. During read out the counter keeps track of the number of words read from the array 80.

Operation of the formatter 70 for converting from data words to symbol data is analogous. Memory words are loaded along lines WI00 to WI15, shifted down for 10 cycles and then shifted left and read out along lines SO00 to SO09 during a second phase while data after six periods are loaded into the array 80 during a second phase on lines WI'00 to WI'15. This data is read out on lines SO00 to SO09 while data again is written after six periods into the array via, lines WI00 to WI15.

For memory configured with 1-bit or 4bit wide DRAM's the above arrangement can be used. They are pictorially illustrated in FIGS. 15A and 15B. As shown the term "phase" represents the operation cycle being performed on the array 80. In FIG. 15A block "A SYMBOLS" are written into the array 80 at ".phi..sub.1 BLOCK A SYMBOLS IN" during phase 1, while data words from a previous block "B WORDS" written during a previous phase 2 write cycle are read out as data words at ".phi..sub.2 BLOCK B WORDS OUT". Block "B SYMBOLS" are written during phase 2 at ".phi..sub.2 BLOCK B SYMBOLS IN" while data words written from a previous block "A WORDS" written during a previous phase 1 write cycle are read out at ".phi..sub.1 BLOCK A WORDS OUT".

Similarly, as shown in FIG. 15B, block "A WORDS" are written in during phase 1 at ".phi..sub.1 BLOCK A WORDS IN" are read out as BLOCK A SYMBOLS during phase 2 at ".phi..sub.2 BLOCK A SYMBOLS OUT. BLOCK B WORDS are written in during phase 2 and are read out as BLOCK B SYMBOLS during the next phase 1 cycle at ".phi..sub.1 BLOCK B SYMBOLS OUT".

For memory systems configured with by 8-bit DRAM's, the storage and reading from the array 80 is different. It takes 10 clock intervals to load the array from memory with a burst of 16 symbols while reading data from memory FIG. 15D. It takes however 16 clock periods to unload the symbols from the array 80. As shown in FIGS. 15C and 15D, a block 88 of 3.times.8 additional array elements are added to the array 80. The sixteen symbols are stored in two sections 91, 92. The symbol outputs of these sections are alternately selected to provide eight symbols for EDC 23. Because eight clock intervals are required to empty 91, the contents of 92 need to be held for three clock intervals before being sent out of the EDC23. The holding register 88 coupled to the array provides this delay. During writes to memory, symbols are loaded in via symbol lines IS00-IS09 (FIG. 8). This loading requires 8 clock intervals. The symbols in the array are then shifted left by columns. The symbol data is shifted 3 clock intervals left and then read out from the array 80 to the memory, as data words during five (5) clock cycles. Data words appear on lines (not referenced) corresponding to the location of WD1 Out and WD2 Out. That is the words are taken at the end of the extended bank of array elements and at column 01 of the original array. Thus additional external connections are needed for array elements 82.sub.15,1 through 82.sub.6,1. The array is also configured to permit symbols to be loaded in a second phase along lines IS'00 to IS'09 and read out along phase 1 WD1 and phase 1 WD2. Provision is thus made for external connection for array elements 82.sub.5,8 to 82.sub.5,15 for .phi..sub.1 WD1. Existing outputs WD08 to WD15 provide outputs for WD2.

A similar arrangement is used for convening from data words to symbols. Data words are fed in along elements 82.sub.6,8 82.sub.6,15 and also 82.sub.11,8 to 82.sub.11,15. Symbols are taken from the array along array elements 82.sub.6,8 to 82.sub.15,8. A similar arrangement is provide for the second phase. Words are read in along array elements 82.sub.15,4 to 82.sub.8,4 and 82.sub.15,9 to 82.sub.8,9, and taken out along array elements 82.sub.-03,07 (where the index" -3" indicates the index of the 3.sup.rd column of the extended array bank 88) to 82.sub.06,07.

With this formatter array 80, when used to handle 8 bit wide DRAM's there is an area of overlap 89. This overlap area 89 is compensated for by providing 4 additional array elements 82.sub.8,9 '; 82.sub.9,10 '; 82.sub.10,9 '; and 82.sub.10,10 ' which are used for one of buffer spaces 91 or 92. Thus with minor modifications the array 80 can also be used to format data from eight bit wide memory devices. These modifications include providing external connection for the additional array elements from which data or symbols are written or read, using 3--input mux's at those additional elements which are connected to an external input, and providing the additional array elements for the delay block 88 and the overlap block 89. Because the memory transfer requires only ten clock intervals out of the sixteen required to transfer the symbol data, six clock intervals are available for the refresh time slot and address multiplexing required to use DRAM components as storage for the memory. Preferably, data are fed out of the array 80 synchronously. Thus, the data (shown as formatter data ) are stored in a register (shown as array data) before it is presented to the memory or the ECC circuit (FIG. 12).

While the invention has been described with reference to a specific embodiment, the description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiment, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments which fall within the true scope of the invention.