Vibration Type Motor Device

1. Field of the Invention

The present invention relates to a control circuit for a vibration type driving device (vibration wave motor).

2. Related Background Art

In a known vibration type driving device (vibration wave motor control circuit), a circuit for changing the width of a pulse to be input to a switching element for applying a driving voltage to a motor is constituted by an analog circuit, as disclosed in Japanese Laid-Open Patent Application No. 64-8873.

In the above-mentioned prior art, the circuit for changing the pulse width suffers from the following drawbacks associated with the use of an analog circuit:

(i) A signal is easily disturbed by noise.

(ii) Since D/A conversion is necessary when the circuit is controlled by a computer, a large number of D/A converters are required, resulting in high cost.

(iii) The control circuit is not suitable for an IC structure; and when a digital arrangement is to be adopted, if the resolution is increased, then the number of logic elements is increased, thus considerably increasing manufacturing costs.

In one aspect, the present invention provides a control circuit capable of arbitrarily setting a driving pulse width for driving a vibration type driving device.

In another aspect, the present invention provides a control circuit for driving a vibration type driving device by forming a driving voltage for an electro-mechanical energy conversion element according to ON/OFF states of first and second switching elements, wherein the driving pulse widths for turning on the first and second switching elements can be independently set for the first and second switching elements.

In yet another aspect, the present invention provides a control circuit, which can independently set pulse signal widths for forming frequency signals having different phases upon application of the frequency signals to an electro-mechanical energy conversion element.

Other objects aspects of the present invention will become apparent from the following description of the illustrated embodiments taken in conjunction with the accompanying drawings.

FIG. 1 is a circuit diagram showing a vibration wave motor control circuit according to a first embodiment of the present invention;

FIG. 2 is a table showing the relationship between the pulse width and the pulse width setting command code in the arrangement shown in FIG. 1;

FIG. 3 is a table showing the relationship among the output from a counter 19, the pulse width, and signals A and B in the arrangement shown in FIG. 1;

FIG. 4 is a circuit diagram showing an arrangement of a vibration wave motor control circuit according to a second embodiment of the present invention;

FIG. 5 is a table showing the relationship between the pulse width and the command code in the arrangement shown in FIG. 4;

FIG. 6 is a table showing the relationship among the pulse width, the command code, and signals A and B in the arrangement shown in FIG. 4; and

FIG. 7 is a table showing the relationship between the command code and the pulse width.

FIG. 1 is a circuit diagram showing a vibration wave motor control circuit according to a first embodiment of the present invention. The circuit shown in FIG. 1 includes a piezoelectric element 1, FETs 2 and 3, a transformer 4, AND gates 5, 6, and 9 to 18, OR gates 7 and 8, and a counter 19.

The operation of this embodiment will be described below with reference to FIGS. 2 and 3.

Command codes G.sub.2, G.sub.1, and G.sub.0 (G.sub.0 =L.S.B) are used for setting the pulse widths of signals A and B, and form a 3-bit gray code indicating one of pulse widths "1" to "8", as shown in FIG. 2. The pulse waveforms of the signals A and B will be described below with reference to FIG. 3. Q represents outputs Q.sub.c, Q.sub.b, and Q.sub.a (Q.sub.a =L.S.B) from the counter 19 in hexadecimal notation. In FIG. 3, A and B represent high-level states of the signals A and B. For example, in the case of the pulse width "5" (G.sub.2, G.sub.1, G.sub.0 =1, 1, 0), the signal B goes to high level when Q="0" to "2", and the signal A goes to high level when Q="4" and "5". A signal S is a signal for connecting/disconnecting the signals A and B to/from the FETs 2 and 3, and a signal CK is a clock signal having a frequency eight times that of a driving signal.

More specifically, in the case of the pulse width "5" (G.sub.2, G.sub.1, G.sub.0 =1, 1, 0), of the AND gates 14 to 18, only the AND gates 16 and 17 are enabled. The AND gate 17 outputs a high (H)-level signal when the count value Q of the counter 19 is "0" and "1", and the AND gate 16 outputs an H-level signal when the count value Q is "2". Therefore, as shown in the row of the pulse width "5" in FIG. 3, an output B from the OR gate 8 goes to H level while the count value of the counter falls within a range from "0" to "2".

On the other hand, in the case of the pulse width "5", of the AND gates 9 to 13, only the AND gate 10 is enabled. The AND gate 10 outputs an H-level signal when the count value Q of the counter 19 is "4" and "5". Therefore, as shown in the row of the pulse width "5" in FIG. 3, an output A from the OR gate 7 goes to H level while the count value is "4" and "5".

If the signal S indicates H level, since the output A is supplied to the FET 2 as a switching element via the AND gate 5, the FET 2 is turned on while the count value is "4" and "5" when the counter 19 repeats count operations from "0" to "7". On the other hand, the output B is supplied to the FET 3 while the counter 19 indicates "0" to "2". During this interval, the FET 3 is turned on. Therefore, when the count value="0" to "2", "4", and "5", a reverse current flows through the transformer 4, and a secondary output generated in the transformer 4 is applied to the piezoelectric element 1.

In the above description, the case of the pulse width "5" has been illustrated by example. When the command codes G.sub.2, G.sub.1, and G.sub.0 are set to have different values, as shown in FIG. 2, the outputs B and A change in correspondence with the count value (FIG. 3) of the counter 19 in accordance with the set pulse width, thereby adjusting the secondary output state to be applied to the piezoelectric element 1.

According to the arrangement of this embodiment, a pulse width with a double resolution can be obtained without increasing the number of bits of the counter, and since the pulse width is commanded using gray codes, the number of inputs to the OR gate 7 can be decreased.

In FIG. 2, the pulse width is set in eight steps. Alternatively, codes may be used up to a middle code or may be used from the middle code, or codes which change bit by bit may be used, as shown in FIG. 7. A method of determining the pulse width of each pulse in the case of the pulse width "5" described above will be explained below. If the pulse width commands "1" to "8" are respectively represented by P.sub.0 to P.sub.7, the pulse width "5" is represented by P.sub.k (k=4).

Since there are two phases of output pulses A and B, if the number of phases is represented by r, then r=2.

When the pulse width of each phase is represented by S.sub.m (m=0, 1, . . . , (l-1)), the pulse widths of A and B phases are respectively represented by S.sub.0 and S.sub.1, a pulse width W.sub.ma which can be actually designated is expressed in five steps, i.e., W.sub.00 to W.sub.04 and W.sub.10 to W.sub.14 including a pulse width="0", and an arbitrary offset value b is set to be 1, S.sub.m is given by:

The conditions for S.sub.0 are m=0, k=4, b=1, and r=2, and the conditions for S.sub.1 are m=1, k=4, b=1, and r=2.

Therefore, S.sub.0 and S.sub.1 are respectively given by: ##EQU1## When fractions below the decimal point are rounded off, the pulse width of the A phase is S.sub.0 =W.sub.02 =2, and the pulse width of the B phase is S.sub.1 =W.sub.13 =3.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention. The circuit shown in FIG. 4 further includes a piezoelectric element 20, FETs 21 and 22, a transformer 23, choke coils 24 and 25 for smoothing a driving waveform, AND gates 26 and 27, a pulse width setting circuit 28, a counter 29, and a conventional up/down counter 30. This embodiment illustrates a case wherein driving voltages of two phases have a 90.degree. phase difference therebetween. The operation of this embodiment will be described below with reference to FIGS. 5 and 6.

FIG. 5 shows gray codes corresponding to pulse width commands. A sign attached to each relevant pulse width value represents the advance or delay between the two phases of the driving voltages, and a code G.sub.4 indicates this sign. The code G.sub.4 is connected to an UP/DOWN terminal of the up/down counter 30. When G.sub.4 =1, the pulse width setting circuit 28 outputs pulses in the order of A.fwdarw.C.fwdarw.B.fwdarw.D based on the count values of the counters 29 and 30 when the counter 29 counts clocks CK. On the other hand, when G.sub.4 =0, the circuit 28 outputs pulses in the order of A.fwdarw.D.fwdarw.B.fwdarw.C.

FIG. 6 shows signals A, B, C, and D output from the setting circuit 28 in response to the pulse width commands shown in FIG. 5, and Q represents outputs Q.sub.d, Q.sub.c, Q.sub.b, and Q.sub.a (Q.sub.a =L.S.B) from the counter 29 and the up/down counter 30 in hexadecimal notation. In FIG. 6, A, B, C, and D indicate high-level states of the signals A, B, C, and D in correspondence with the counter value Q. In this manner, since 16 steps of pulse widths can be set based on four steps of pulse widths per phase, i.e., for each of A, B, C, and D phases, a high-resolution pulse width can be set by a small-scale circuit. The pulse widths of A, B, C, and D phases will be calculated as in the first embodiment. Assume that pulse width commands "1" to "15" are represented by P.sub.0 to P.sub.14, and the command P.sub.9 will be illustrated. When the number of phases r=4, the pulse widths of the A, B, C, and D phases are respectively represented by S.sub.3, S.sub.1, S.sub.2, and S.sub.0, an arbitrary offset value b is set to 2, and pulse widths which can be respectively designated for the pulse widths S.sub.0, S.sub.1, S.sub.2, and S.sub.3 are expressed in five steps, i.e., W.sub.00 to W.sub.04, W.sub.10 to W.sub.14, W.sub.20 to W.sub.24, and W.sub.30 to W.sub.34, S.sub.0, S.sub.1, S.sub.2, and S.sub.3 are respectively given by: ##EQU2## If fractions below the decimal point are rounded off, the pulse width of the A phase is W.sub.33 ; the B phase, W.sub.13 ; the C phase, W.sub.23 ; and the D phase, W.sub.02.

With the above-mentioned arrangement, the signals A and B are output according to the pulse widths set at a timing of the count value Q shown in FIG. 6, and AND gates 5 and 6 output H-level signals to drive a transformer 4 with the pulse widths of the signals A and B, thus applying a driving voltage to a first-phase piezoelectric element 1. Similarly, the outputs from the AND gates 26 and 27 go to H level with the pulse widths of the outputs C and D (respectively having a 90.degree. phase difference from the outputs A and B) to drive the transformer 23 with the pulse widths of the outputs C and D, thereby applying a driving voltage to the second-phase piezoelectric element 20. In this case, as described above, since the pulses widths of the pulses (A, B) for the first phase and the pulses (C, D) for the second phase can be independently set, arbitrary driving voltages can be applied to the first and second phases.

In the above embodiment, as described in, e.g., U.S. Pat. No. 4,833,358, the piezoelectric element is arranged on a vibrating member, and forms a travelling vibration wave to obtain a driving force for driving an object. In place of the piezoelectric element, other electro-mechanical conversion elements such as an electrostrictive element may be used.