Computer-Controlled Circuit Breaker Arrangement With Circuit Breaker Having Identification Circuit

The present invention relates generally to circuit breaker tripping systems, and, more particularly, to microcomputer-based circuit breaker energy management systems in which the circuit breakers open and close in response to a control signal from a computer.

Circuit breaker energy management systems are designed to control circuit breakers in a circuit breaker panelboard by commanding the circuit breakers to turn "on" and "off," so as to "close" and "open" the current path for efficient energy use. Typically, a microcomputer is programmed to generate such commands.

It is advantageous for such systems to be user-programmable and user-maintainable so that circuit breakers in the panelboard can be replaced and additional circuit breakers can be added to the system. In a newly installed system having all two-pole breakers, for example, the microcomputer would be programmed to control only two-pole circuit breakers at designated circuit breaker positions, or slots, in the panelboard. If the panelboard subsequently required, after initial installation, a three-pole circuit breaker, the program for the microcomputer would have to be replaced so that the microcomputer can communicate with, and properly control the newly added circuit breaker.

This type of adaptability is not only burdensome and expensive for the user, it is unacceptable in many applications in which accessibility is difficult or prohibited. Accordingly, a microcomputer-based circuit breaker energy management system is needed which overcomes these deficiencies of the prior art.

The present invention provides an energy management loadpanel arrangement including a loadpanel enclosure having a plurality of circuit breakers, at least one of which includes a digital circuit indicating the type of circuit breaker (for example, one, two or three pole) and which opens and closes in response to a control signal generated by a microcomputer.

In a particular embodiment, an energy management loadpanel arrangement includes a loadpanel enclosure and a plurality of circuit breakers secured in the enclosure. At least one of the circuit breakers is digitally-coded and capable of opening and closing in response to a control signal so as to interrupt an associated current path. A microcomputer responds to the digital signal by determining the type of circuit breaker represented by said digital signal and then generates the control signal to control the circuit breaker and its associated current path. Thus, the digital signal is used by the microcomputer to determine the identity, or type, of circuit breaker disposed at one or more of the circuit breaker positions in the loadpanel.

The circuit breaker that is digitally-coded includes an interface circuit that provides the data to the microcomputer serially, using only two lines. One of the lines is used to select (or activate) the interface circuit, and the other line is used to generate a clock pulse in one direction and to read the digital signal in the other direction. In an application requiring a multitude of circuit breakers each having a respective identification circuit, this two-line communication scheme is used in an array to provide access to the respective interface circuits of all the circuit breakers.

Other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings, in which:

FIG. 1a is a perspective view of a load center arrangement, according to the present invention;

FIG. 1b is another perspective view of the load center arrangement of FIG. 1a;

FIG. 2 is a block diagram of the control module and interface module shown in FIGS. 1a and 1b;

FIG. 2a is a timing diagram showing a useful communication channel for certain of the circuits shown in FIG. 2;

FIG. 3 is an expanded block diagram of a portion of the interface module of FIG. 2, illustrating a manner in which a microcomputer of the interface module can efficiently communicate with the circuit breakers through an interface circuit;

FIG. 4 is a schematic diagram of one of several motor driver circuits illustrated in FIG. 3;

FIG. 5 is a schematic diagram of one of several circuit breaker select driver circuits illustrated in FIG. 3;

FIG. 6 is a schematic diagram of the electrical portion of a circuit breaker illustrated in FIG. 1a;

FIG. 7 illustrates a circuit breaker, according to the present invention, which may be used as part of the arrangement shown in FIGS. 1a and 1b; and

FIG. 8 is a state diagram depicting the power driver, data transmit and data receive operations of the gate array illustrated in FIG. 3.

While the invention is susceptible to various modifications and alternative forms, a specific embodiment thereof has been shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that it is not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

The present invention has direct application for managing energy by monitoring and interrupting current paths passing through a panelboard (or circuit breaker box), according to specifications that may be programmed by the user. For example, it may be desirous to program the panelboard so that certain types of circuit breakers open and close at specified times of the day. In this way, the energy provided through the panelboard can be efficiently used.

The panelboard arrangement of FIGS. 1a and 1b provides an extremely adaptable and user-friendly panelboard, in which a panelboard or load-center enclosure 10 distributes, from a plurality of input power lines 12, power to various loads (not shown) via lines 14 which exit the enclosure 10. Bus boards 16 and 18, which may be implemented on the same board, are disposed in parallel on each side of the load-center for mounting remotely controlled circuit breakers 20, each having a plug-in socket which is coupled to one of a plurality of connectors 22 on the bus boards 16 and 18. The connectors 22 are used with the bus boards 16 and 18 to carry motor control and contact-status signals, via an interface module 24, to and from the circuit breakers 20. The interface module 24 interprets messages from a controller (or control module) 32 so as to facilitate electrical control and monitoring functions from both local and remote locations.

As illustrated in the block diagram of FIG. 2, the circuit breakers 20 are controlled by a microcomputer 102, which is part of the interface module (24 of FIG. 1) depicted below the dashed lines. Between the circuit breakers 20 and the microcomputer 102 there resides an interface circuit 104 which preferably includes an optical isolation circuit (not shown) to isolate the circuit breakers 20 from the remainder of the interface module.

Various types of circuits can be used to implement the interface circuit 104. For example, the I/O bits from the microcomputer 102 can be used so as to directly drive the inputs of the optical isolators. Alternatively, a modified version of the gate array circuit disclosed in "ELECTRICAL DISTRIBUTION SYSTEM WITH IMPROVED CIRCUIT FORMULTIPLE CIRCUIT BREAKER CONTROL", U.S. patent application Ser. No. 07/723,362, filed on Jun. 28, 1991, abandoned Jun. 20, 1993, can be used to implement the interface circuit 104. Such a gate array is described in connection with FIGS. 3 et seq.

The microcomputer 102 commands the circuit breakers to their respective "open" and "closed" positions according to respective 2-wire or 3-wire switch inputs provided at a dry contact interface 106. The connections for, and control over, the signals at the switch inputs can be implemented as set forth in the last-referenced application, or using conventional methods, such as the implementation in Square D Company's "PowerLink" product, or as described in U.S. patent application Ser. No. 07/620,237, filed on Nov. 29, 1990 and entitled "Power Management and Automation System, now U.S. Pat. No. 5,323,307." Alternatively, the circuit breakers 20 are controlled via a program stored by the microcomputer 120.

The microcomputer 102 uses conventional memory circuits, for example ROM 108 and EEPROM 110, for storage of its object code and other data requiring permanent or semi-permanent preservation.

As an option, the interface module can also include a serial interface circuit 112 to permit the microcomputer 102 to communicate with similarly situated panelboard arrangements, such as the one shown in FIGS. 1a and 1b.

The control module (32 of FIG. 1b and shown above dashed lines in FIG. 2) incorporates a microcomputer 120, and conventional memory circuits including ROM 122, EEPROM 124 and RAM 126, to provide the overall control for the panelboard arrangement. This control includes overall initialization, communication between the microcomputers 120 and 102, monitoring and control of the keyboard and display 130, and I/O communication via a serial interface 132 or a network interface 134. A multiplexer 136 is used to establish which interface 132 or 134 communicates with the microcomputer 120.

The keyboard and display 130 can be implemented using conventional LCD type driver and key read circuitry. For example, a 44 character by 8 line display and a 24 button push key circuit can be used to provide status-reading and function-programming capabilities to a user.

The ability to control the circuit breakers 20 according to the time of the day is established by a program entered via the keyboard and display 130. The microcomputer 120 employs a conventional real time clock (RTC) 138, such as the DS1283S available from Dallas Semiconductor, to maintain the time.

The entire panelboard arrangement of FIG. 2 is provided power via a conventional power supply 140, including a regulated Vcc (+5 Volts and associated common), a separately regulated +5 Volt Isolated ("VISO" and associated VISO common), and separately regulated -24 Volt and -5 Volt outputs sharing a common ground.

The power supply 140 is preferably sourced by a 240 volt AC or 480 volt AC line and, therefore, is susceptible to long-term interruptions. These long-term power interruptions, for example, are frequently encountered with electric company overloads, blackouts and other events requiring manual service or repair by the electric company. Thus, during these interruptions a secondary power supply is needed to maintain the integrity of important data which is used frequently and is not stored in the non-volatile EEPROM.

The secondary power supply is provided using an electrical double-layer capacitor (EDLC or SUPERCAP) 144, which supplies secondary power to the RTC 138 and RAM 126 via a power arbitration circuit 146. The arbitration circuit 146 ensures that a +5 Volt source supplies power to the RTC 138 and RAM 126 either from the power supply 140 or from a stored capacitive charge on the EDLC 144. Thus, in the event that the power supply 140 shuts down, each of the circuits shown in FIG. 2 powers down except for the RTC 138 and RAM 126 (and unshown logic support circuits), which stay powered up as long as there is sufficient charge on the EDLC 144. An FS or FE type SUPERCAP available from NEC Corporation, which may be used for this application, provides several weeks of standby power for the implementation shown in the figures.

A reset switch 148 is used to reset the entire circuit of FIG. 2 via its connection to both the microcomputer 120 and the arbitration circuit 146.

Other aspects of the EDLC 144 and the RTC 138 are discussed in copending U.S. patent application Ser. No. 901,058, now U.S. Pat. No. 5,315,499, entitled "COMPUTER CONTROLLED ENERGY MANAGEMENT ARRANGEMENT HAVING RELIABLE MEMORY AND CLOCK," filed concurrently herewith and assigned to the instant assignee. This application is also incorporated herein by reference.

Communication between the microcomputers 102 and 120 can be provided using any of a number of asynchronous or synchronous serial communication schemes. For example, synchronous communication can be provided using three lines which directly interconnect the microcomputers and establish the control microcomputer 120 as the master and the interface microcomputer 102 as the slave. Using Intel's 80C31B type microcomputers, for example, the P1.0 port for the master 120 and P1.4 port for the slave can be used as the data in/out line ("DATA"), the P1.1 port as an input for the master 120 and P1.5 port as an output for the slave can be used as the handshake line for the interface microcomputer 102 ("I.HS"), and the P1.2 port as an output for the master 120 and the INT1 port as an input for the slave can be used as the handshake line for the interface microcomputer 102 ("C.HS"). In such an implementation, the command/response format would be initiated by the master, by sending an OP-CODE type command followed by the number of data bytes to be sent, and followed by the data bytes and a checksum word. The response would be a response number, followed by the number of data bytes to be returned, and followed by the data bytes and a checksum word.

Error checking between the master and slave is also provided using a software watchdog timer in each microcomputer.

FIG. 2a, illustrates the timing of the communications between the microcomputers 102 and 120. In an exemplary communication scheme, the illustrated timing of FIG. 2a between the microcomputer 120, acting as the "Controller", and the microcomputer 102, acting as the "Interface", uses ten protocol steps as follows:

1. Controller initiates communications by putting up first bit of data and pulling C.sub.-- HS low to indicate data is available.

2. Interface receives EXT.sub.-- INT from C.sub.-- HS, reads first bit, shifts it into receive byte, and then pulls I.sub.-- HS low to acknowledge data received.

3. When seeing D.sub.-- ACK, Controller removes D.sub.-- AVL and waits for D.sub.-- ACK to return high.

4. Simultaneously, the Interface waits for D.sub.-- AVL to return high and will set D.sub.-- ACK high when it happens.

5. When D.sub.-- CK is high, Controller gets the next bit and repeats the cycle.

6. When Interface gets 8 bits, they are transferred to the communications buffer. On receipt of byte 2 (# of bytes), the byte counter is loaded.

7. When the number of bytes received equals the number of bytes in the counter +2 (for the checksum) Interface computes and compares th checksums.

8. The control module should be waiting for a response when all bytes are sent. The roles reverse, with Interface now sending data.

9. The process repeats until the cycle is complete.

10. The frame bit is set internally be each microprocessor to indicate the amount of time spent in the communications routine. This is used by the communications watchdog to stop the process and re-initialize if required.

FIG. 3 illustrates the interface circuit 104 providing the control, and reading, of the circuit breakers 20 under control of the microcomputer 102 of FIG. 2. From the microcomputer, data is transmitted to and received from a gate array 206 serially, via an optical isolator 210. The gate array 210, which can be implemented using a semi-custom part available from ACTEL, Inc. of Sunnyvale, Calif., is provided a clock signal by a conventional oscillation circuit 216 operating, for example, at 455 kHz. The optical isolator 210 can be implemented using two NEC2501-1 type parts with respective resistors (R=1 k Ohm) providing the appropriate bias at the inputs and outputs of the optical isolator 210.

The serial communication between the microcomputer and the gate array 206 is performed using a sixteen bit word, the bits of which are as follows (beginning with least significant bit):

first nine bits: six address bits followed by three command bits;

tenth and eleventh bits: fixed bits at 0 and 1, respectively, for error detection;

next four bits: check bits using a hamming code;

last bit: fixed stop bit at 1.

There are five commands implemented in the three command bits. They are: 001--open, 101--close, 010--read motor status, 110--read contact status, 100--read ID circuit, and 000--NO OP. The NO OP command is used to read the transmit buffer in the gate array without communicating with the circuit breakers. The transmit buffer in the gate array is automatically read whenever one of the other commands is sent to the gate array.

The gate array 206 feeds six circuit breaker row drivers 212 and seven circuit breaker column drivers 214, which are configured seven down and six across, respectively, for controlling the motors "M" and identification circuits "ID" of up to forty-two circuit breakers. Each of the circuit breaker row drivers 212 and circuit breaker column drivers 214 acts as an amplifier to the corresponding signal from the gate array 206.

Each row driver 212 is used to select (or enable) the circuits of six circuit breakers, while each column driver 214 is used to actuate the circuit breaker motor and identification circuit pair which is selected by the intersecting row driver 212.

A status filter 220 is connected to the circuit breakers in each row in order to receive a status signal from a particular circuit breaker. The status signal is used to report whether the contacts of the circuit breaker are open or closed. The status signal from a circuit breaker is operative, and readable via the gate array 206, when two conditions are present: the corresponding column driver 214 is selecting the column of circuit breakers in which the status filter 220 is associated; and the gate array 206 is actuating a triac circuit (e.g., a Siemens IL420) 218 to provide, simultaneously, a momentary common path (LED COMM on the bus boards 16 and 18 of FIG. 1a) for the input ports of the optical isolators 230 (FIG. 6) of all forty-two of the circuit breakers. The gate array 206 then reads all six statuses and determines which of these statuses are to be sent to the controller 32. The circuit breaker contacts are preferably monitored using a lead 231 (FIG. 6) connected to the load terminal of the circuit breaker 20.

A varistor 222, such as a GE-V30DLA2, is coupled across the output ports of the triac circuit 218 to provide circuit protection against voltage and current transients.

In FIG. 4, the column (or motor) driver 214 is shown as being controlled by the gate array 206 using CDa, CDb and MSTAT leads so as to drive the motor on the selected circuit breaker 20. The diodes 232 through which the motor drive signal passes are located on the bus board 16 or 18 to allow a current path through only one circuit breaker 20. The CDa and CDb signals from the gate array 206 are controlled in a polarized manner between -5 Volts and common so that if either signal is absent, the designated circuit breaker 20 cannot be commanded to open or close its contacts.

The MSTAT signal is used to indicate whether or not a motor is present. This type of status check operates in substantially the same manner as the statuses from the associated circuit breaker load, as described above. The MSTAT signal is operative when the corresponding column driver 214 selects the column of circuit breakers associated with the circuit breaker under test. The gate array 206 then reads all six MSTAT signals and determines which of these signals are to be sent to the controller 32. A diode 235 is connected between -24 Volts and "OPEN" to prevent the signal level on "OPEN" from falling below this point, a pull-down resistor 236 is connected between -5 Volts and "CLOSE" to maintain the signal at -5 Volts when it is not being driven by the designated circuit breaker.

In FIG. 5, the row (or select) driver 212 is shown as being controlled by the gate array 206 using RDa and RDb leads so as to select the appropriate row of circuit breakers 20. The diodes 238 and 239 are used to mitigate the effect of transient signals received from the bus boards 16 and 18.

FIG. 6, which illustrates the electrical control portion of the preferred remote control circuit breaker 20, depicts six leads carried by each plug-in connector (22 of FIG. 1a) of the bus boards 16 and 18. The first four of these include: the select lead 246, status lead 248, motor drive lead 250 and an isolator enable lead 252. The signals of each of these leads are carried on the bus boards 16 and 18 (FIG. 1a) using the six-by-seven array configuration of FIG. 3 to limit the number of conductors required to communicate with the circuit breakers.

A parallel resistor/diode arrangement 254/256 serves two functions. The diode 254 may be used to provide current flow in a unilateral direction, while the resistor 256 is used to control the power provided from lead 258 to the motor of the circuit breaker 20. The value of the resistor 256 is selected according to the necessary current specified to operate the motor. In the event that the lead 258 is used to control a plurality of poles, e.g., for controlling two or three circuit breaker poles, the resistance required will vary. For single pole operation by a FK130S-10300 Mabuchi motor, the value of the resistor 256 is preferably 12 Ohms.

The remaining two leads carried by each plug-in connector, data/clock 262 and -5 Volts 264, are used in combination with select 246 to control and access the identification portion of the circuit in the circuit breaker. This configuration allows the transmission of encoded digital information from the gate array to as many as forty-two conductors using a limited number of conductors, using conventional parts and using no internal clock.

Each of nine status bits, which are manually settable at JMP1-JMP9 positions, are converted to serial data at lead 272 using a 74HC165 shift register 273 so as to permit up to 256 digital signals to be read by the gate array. These signals can be used to indicate how many poles the circuit breaker includes, the current rating of the circuit breaker, and other information that is associated with the circuit breaker or with the circuit breaker position. For example, the controller can determine if there exists a circuit breaker in a particular circuit breaker position by using all "0"s to indicate that no circuit breaker is present, and another code to identify the type and/or status of a device in that position that is not a circuit breaker, for example, a plug-in surge protector. Other possibilities exist as well.

The identification circuit remains inactive while power is off and presents a high impedance to any circuitry connected to the clock/data lead under these conditions. When select 246 is either open circuited or taken to the same voltage potential as -5 Volts 264, transistors 266-268 are inactive and data/clock 262 appears as a high impedance input to external circuitry. A 1000 Ohm resistor 269 bleeds off any charge from between Vcc and -5 Volts, and a diode 270 discharges capacitor 271 in preparation for when power is next applied to select 246.

Power is applied between select 246 and -5 Volts 264 by setting select 246 to 0 Volts. When this occurs, capacitor 271 will be discharged and will hold SH.sub.-- LD input of the shift register 273 low for a short time causing the data present at SER and A-H inputs to be parallel loaded into the shift register 273. Also during this initialization phase, transistors 266-268 will be enabled and the voltage at data/clock 262 (set to "high" at initialization) will appear at the collectors of transistors 266 and 267. After stabilization of the initialization phase, the CLK input of the shift register 273 will be high and its SH.sub.-- LD input will also be high allowing the shift register 273 to enter its shift mode of operation. At this point, the data present at the H input will be present at QH output of the shift register 273. A 100 kOhm resistor 280 acts to hold the power on the shift register down until select 246 reaches 0 Volts.

To transmit data from the shift register 273, a specific sequence of events is used. To read the first bit present at QH, all that is required is to tri-state data/clock 262. If the data present at QH is a "1", QH will hold the line high through a 1000 Ohm resistor 274. If the data present at QH is a "0", data/clock 262 will be pulled low through the resistor 274. In either case, the data present in the shift register 273 will not be shifted because its clock requires a low-to-high transition to shift the data.

To shift the next data bit to the QH output, the first step is to take data/clock 262 from tri-state to low. This action has no effect on the clock input of the shift register 273. If QH is low, it will remain low; if it is high, it will be pulled low because data/clock 262 will over-drive the QH output through the resistor 274. In either case, the shift register will not have been clocked yet.

The next step is to drive data/clock high. This will drive the clock input high and cause a data shift regardless of the state of QH. The data is then read by tri-stating the data/clock and reading the data present at QH via the resistor 274 and the transistors 266-267. If QH is high, data/clock 262 will simply remain high; if it is low, data/clock 262 will go low. In either case the data in the shift register will not be inadvertently shifted.

The SER input to the shift register 273 is set for odd or even parity to provide error detection.

Accordingly, each of the data bits at JMP1-JMP9 is shifted and read by tri-stating the data/clock, reading the data present at QH and then taking data/clock 262 from tri-state to low for the next data bit.

For further details concerning the configuration of the gate array of FIG. 3, a two-sheet schematic, representing the detailed electrical configuration of the gate array of FIG. 3, is attached hereto as a fuse-file list (used to program the gate array) in Appendix A. Also, a one-sheet pin-out list identifying the pinout/interface circuitry configuration for the gate array of FIG. 3 is attached hereto as appendix B. The pinout/pin-name list for the gate array is listed in appendix C.

An implementation for the circuit breaker 20 is shown in expanded form in FIG. 7. The arrangement includes an insulative body or housing 310, a line terminal 314 and a load terminal 316 for completing the circuit between the source and load (not shown). More specifically, the circuit path beginning at line terminal 314 carries current through stationary and movable contacts 318 and 320 and through a flexible copper conductor 322, which is soldered between a carrier 324 and a bimetal 328. A rigid conductive plate 329 carries current from the bimetal 328 to the load terminal 316.

Remote control is provided using a motor 350 having a shaft 352 which rotates in one direction to pull the carrier 324 and break the current path and which rotates in the opposite direction to allow the carrier 324 to be pulled by spring 334 to re-establish the current path. This is accomplished with a shaft spring 354 which is mounted around the shaft 352, and a gear 356 which rotates about a pin 357 to control a hook-shaped drive rod assembly 358 which includes an end which bends into a hole 325 in the contact carrier 324 for pulling the carrier 324. The shaft spring 354 is secured at one end 360 to the shaft 352, using a torsional-type pressure fitting, so that the shaft spring 354 rotates with the motor shaft 352. The gear 356 includes teeth 362 which interlock with the windings of the spring 354 to establish a linear relationship between the rotation of the shaft 352 and the rotation of the gear 356 about pin 357. For example, clockwise rotation of the shaft 352 may correspond to a counterclockwise rotation of the gear 356 about pin 357.

A coupling pin 364, which is secured to and protrudes out of the gear 356, responds to the rotation of the gear 356 to control the position of the contact carrier 324. As the gear teeth 362 move with the shaft spring 354, the side of the gear 356 opposite the teeth 362 rotates to the same degree, thereby forcing the coupling pin 364 to rotate about pin 357. The movement of the coupling pin 364 in the counterclockwise direction pulls the drive rod assembly 358 a, b to the right in order to pull the contact carrier 324 away from the stationary contact 318. The drive rod assembly 358 a, b is sufficiently long to provide a gap on the right side of the coupling pin 364 when the gear 356 is fully rotated clockwise so that the contact carrier 324 does not prevent the contacts 318 and 320 from closing.

In response to the motor operating in the opposite direction, the coupling pin 364 rotates in the clockwise direction and allows the biasing spring 334 to return the contact carrier 324 to the contacts-closed position.

The circuit of FIG. 6 can be implemented on the printed circuit board 412, or the upper and lower halves of the circuit of FIG. 6 can be mounted on separate printed circuit boards and "piggy-backed" together. A conventional six-pin connector 410 is used to mate the circuit breaker with the bus board 16 or 18 of FIG. 1a.

For additional information concerning the operation and structure of this circuit breaker, reference may be made to U.S. patent application Ser. No. 07/722,050, filed Jun. 28, 1991, now U.S. Pat. No. 5,180,051, entitled "REMOTE CONTROL CIRCUIT BREAKER, and assigned to the instant assignee.

FIG. 8 illustrates, in state diagram form, the power driver, data transmit and data receive operations of the gate array of FIG. 3. The diagram includes eight states, depicted A-H. Beginning at state A, the gate array waits for a command from the controller. The command may be any one of the commands previously discussed: a close contacts command which instructs a particular circuit breaker to close its contacts, depicted by the sequence of states A-B-D-E-A; an open contacts command which instructs a particular circuit breaker to open its contacts, depicted by the sequence of states A-C-D-E-A; a read contacts command to determine if a particular circuit breaker's contacts are closed or open, depicted by the sequence of states A-E-A; a read motor command to determine if the motor is present, depicted by the sequence of states A-F-A; a read ID circuit command to read the digital code in the circuit breaker, depicted by the sequence of states A-G-A; and a NO OP, depicted by the sequence of states A-H-A. The state delay associated with state D is to allow the contacts sufficient time to settle before reading the status of the contacts at state E. The state delays associated with states B and C are to allow the contacts sufficient time to react before commencing the settling-time delay of state D. The state delays associated with states E and F are to provide the gate array with the appropriate timing response before reporting to the controller with the requested status.

While the invention has been particularly shown and described with reference to a few particular embodiments, it will be recognized by those skilled in the art that modifications and changes may be made to the present invention described above without departing from the spirit and scope thereof. For example, in view of their similarities, many of the components or blocks disclosed herein may be substituted and/or combined with the arrangement disclosed in the application entitled, "ELECTRICAL DISTRIBUTION SYSTEM HAVING MAPPABLE CONTROL INPUTS," supra. ##SPC1##