Circuit Device Utilizing a Plurality of Transistor Pairs

1. Field of the Invention

The present invention relates to a circuit device.

2. Description of the Related Art

Several types of D-A converters utilizing current sources have heretofore been known, such as a type in which the value of each binary-weighted current source is added to the value of the next one by using transistors and a type which employs equal current sources and R-2R ladder resistors.

However, such a conventional type of D-A converter has a number of problems. For example, in the case of the binary-weighted current source type of D-A converter, since linearity error, which is the most important performance index, is determined by the relative accuracy between transistors which constitute each current source, it is necessary to form transistors having emitter area ratios of up to 1:32, for example, in a 6-bit D-A converter. As a result, an area to be occupied by such a D-A converter on a semiconductor circuit device becomes extremely large and an increase in cost is incurred. If a quantizing bit number is increased, the above-described problem becomes serious. In the D-A converter of the type which employs equal current sources and R-2R ladder resistors, if the relative accuracy between R-2R ladder resistors is increased up to a generally necessary value, an extremely large area is needed. This still leads to a further increase in cost.

It is, therefore, an object of the present invention to solve the above-described problems.

Another object of the present invention is to provide a circuit device which can be reduced in area to be occupied, which can be miniaturized and which can be reduced in cost.

To achieve the above objects, in accordance with one aspect of the present invention, there is provided a circuit device which comprises a plurality of transistor pairs, the number of which corresponds to a quantizing bit number, each of the plurality of transistor pairs being a pair of transistors having respective control electrodes connected to each other and respective first primary electrodes connected to each other, and a connecting line arranged to connect in series a second primary electrode of one transistor of one transistor pair among the plurality of transistor pairs to first primary electrodes of another transistor pair among the plurality of transistor pairs so as to constitute a binary-weighted current source.

The above and other objects, features and advantages of the present invention will become apparent from the following detailed description of preferred embodiments of the present invention, taken in conjunction with the accompanying drawings.

FIG. 1 is a diagram showing the circuit arrangement of a D-A converter which constitutes a first embodiment of a circuit device according to the present invention; and

FIG. 2 is a diagram showing the circuit arrangement of a D-A converter which constitutes a second embodiment of the circuit device according to the present invention.

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing one example of a D-A converter which constitutes a first embodiment of a circuit according to the present invention. The D-A converter which constitutes the first embodiment of the present invention is a 6-bit current output type of D-A converter.

In FIG. 1, reference numeral 1 denotes a D-A converter having a power source voltage IN. The arrangement shown in FIG. 1 includes a power source voltage 1, switches SW.sub.1 to SW.sub.6 which are arranged to be individually switched according to the digital input of the D-A converter, and NPN transistors Q.sub.19 and Q.sub.20 which are disposed to form a current mirror arrangement. The emitter size of the NPN transistor Q.sub.19 is selected so that its collector current becomes I/2 (I is an arbitrary amount of current), while the emitter size of the NPN transistor Q.sub.20 is selected so that its collector current becomes 4.times.I. The shown arrangement also includes NPN emitter-coupled transistors (which form a pair of NPN transistors) Q.sub.1 and Q.sub.2, Q.sub.3 and Q.sub.4, Q.sub.5 and Q.sub.6, Q.sub.10 and Q.sub.11, Q.sub.12 and Q.sub.13, and Q.sub.14 and Q.sub.15. Each of the NPN transistor pairs is arranged in such a manner that the base and emitter of one NPN transistor are respectively connected to the base and emitter of the other NPN transistor. The shown arrangement further includes bias voltage sources V.sub.1 to V.sub.3 which are respectively set to appropriate voltage values so that the associated ones of the NPN transistors Q.sub.1 to Q.sub.6 and Q.sub.10 to Q.sub.15 as well as NPN transistors Q.sub.7, Q.sub.8, Q.sub.9, Q.sub.16, Q.sub.17 and Q.sub.18 can be set to their active states. The base of each of the transistors Q.sub.8 and Q.sub.17 and the base of each of the transistors Q.sub.9 and Q.sub.18 are connected to the base voltage sources V.sub.3 and V.sub.2, respectively.

As described above, the emitter size of the NPN transistor Q.sub.20 is adjusted by an appropriate constant current circuit so that its collector current becomes 4.times.I. The NPN transistors Q.sub.14 and Q.sub.15, the emitter of each of which is connected to the collector of the NPN transistor Q.sub.20, are connected by their bases and biased by the voltage of the bias voltage source V.sub.1. Since the collector potential of each of the NPN transistors Q.sub.14 and Q.sub.15 becomes a potential which is 1V.sub.BE lower than the potential of the bias voltage source V.sub.2, the NPN transistors Q.sub.14 and Q.sub.15 are biased approximately equivalently. Accordingly, the collector currents of the NPN transistors Q.sub.14 and Q.sub.15 become equal, so that if their base currents are neglected, the collector current of each of the NPN transistors Q.sub.14 and Q.sub.15 becomes 2.times.I which is half the collector current of the NPN transistor Q.sub.20.

Similar operations respectively occur among the NPN transistors Q.sub.12, Q.sub.13 and Q.sub.14, among the NPN transistors Q.sub.10, Q.sub.11 and Q.sub.12, among the NPN transistors Q.sub.5, Q.sub.6 and Q.sub.19, among the NPN transistors Q.sub.3, Q.sub.4 and Q.sub.5, and among the NPN transistors Q.sub.1, Q.sub.2 and Q.sub.3. Accordingly, the collector current of each of the NPN transistors Q.sub.1 and Q.sub.2 becomes 1/16, the collector current of each of the NPN transistors Q.sub.3 and Q.sub.4 becomes I/8, the collector current of each of the NPN transistors Q.sub.5 and Q.sub.6 becomes I/4, the collector current of each of the NPN transistors Q.sub.10 and Q.sub.11 becomes I/2, and the collector current of each of the NPN transistors Q.sub.12 and Q.sub.13 becomes I. Thus, the binary-weighted current sources of from I/16 to 2.times.I are obtained.

By selectively switching the current sources by the switches SW.sub.1 to SW.sub.6, the collector current of a current summary PNP transistor Q.sub.21 is outputted as an analog current which is obtained by digital-to-analog conversion according to a digital input which controls the on/off operations of the individual switches SW.sub.1 to SW.sub.6. The output current of the PNP transistor Q.sub.21 is provided at the collector of a PNP transistor Q.sub.22 which is connected to the PNP transistor Q.sub.21 to form an current mirror arrangement.

Of the NPN transistors Q.sub.1 to Q.sub.20, the NPN transistors Q.sub.7 to Q.sub.9 and the NPN transistors Q.sub.16 to Q.sub.18 are inserted for the purpose of making equal the collector potentials of the associated emitter-coupled transistor pairs and highly accurately adjusting the collector currents to a uniform level for each of the emitter-coupled transistor pairs.

It is to be noted that it is, of course, possible to adopt an arrangement in which the NPN transistors Q.sub.1 to Q.sub.20 are replaced with PNP transistors, whereas the PNP transistors Q.sub.21 and Q.sub.22 are replaced with NPN transistors.

In the description of the first embodiment shown in FIG. 1, reference has been made to one example of a 6-bit D-A converter. However, the number of bits can be increased or decreased by increasing or decreasing the number of connection stages of emitter-coupled transistor pairs. FIG. 2 is a circuit diagram of a second embodiment and shows one example of a 3-bit D-A converter whose transistors are of opposite polarity to the transistors used in the embodiment shown in FIG. 1. In the shown arrangement, PNP transistors Q.sub.10 ' and Q.sub.11 ' are provided for supplying a current I to PNP transistors Q.sub.1 ' and Q.sub.2 '. The output current of this arrangement is provided at the collector of an NPN transistor Q.sub.13 ' which is connected to an NPN transistor Q.sub.12 ' to form a current mirror arrangement.

It is also possible to adopt an arrangement in which the aforesaid emitter-coupled NPN transistors are replaced with N type field effect transistors which are connected together gate to gate and source to source. In the arrangement shown in FIG. 2, the emitter-coupled PNP transistors may also be replaced with P type field effect transistors. With either of the arrangements, it is possible to achieve similar advantages.

As is apparent from the foregoing description, according to either of the first and second embodiments, it is possible to construct a D-A converter made up of transistor pairs while taking account of only the relative accuracy between two transistors which constitute each of the transistor pairs. Accordingly, an area to be occupied by a D-A converter on a semiconductor circuit device can be made small compared to conventional examples. Similarly, it is possible to form a D-A converter of high bit accuracy while taking account of the characteristics of two transistors which are paired at an emitter area ratio of 1:1. Accordingly, in the formation of such a D-A converter, the extent of increase of an area to be occupied by the D-A converter on a chip can be made extremely small compared to the conventional examples, so that no cost increase is incurred.