US 5,453,711 AGrant
Weighted Summing Circuit
Issue Date:1995-09-26
•7 Claims
•2 Drawing Sheets
Abstract
A weighted summing circuit performing a weighted summation using small scale circuitry with a degree of accuracy and that is easily adapted to operate with various kinds of processing systems. Weighted summing circuit includes parallel inductances L.sub.1, L.sub.2 and L.sub.3 having voltages V.sub.1, V.sub.2 and V.sub.3 at a common output V.sub.out.
Metadata
Assignees
- Yozan Inc.
- Sharp Corporation
Inventor
- Makoto Yamamoto
Application Information
Application Number:US 1473115
Filing Date:1993-11-05
Priority Date:1992-11-06
Art Unit:254
Classifications
IPC:
H03K 522
Field of Search:
328307327104;158529;242355;361;407
Patent Drawings (2 sheets)
Description
Field of the Invention
The present invention relates to a weighted summing circuit, including a plurality of parallel connected inductances having an equilibrium voltage as a common output;
Background of the Invention
Digital weighted summing circuit are known. However, digital weighted summing circuits are large scale circuits. Analog weighted summing circuit are also known, but such circuits have in its calculation low accuracy.
Summary of the Invention
This invention solves the conventional problems and provides a weighted summing circuit that performs a weighted summation using a small scale circuit having high accuracy and that is easily available for a various kinds of calculation devices.
A weighted summing circuit according to the present invention has a summing voltage as a common output in a parallel inductance circuit.
Brief Description of the Drawings
FIG. 1 is a circuit diagram showing an embodiment of a weighted summing circuit according to the present invention;
FIG. 2 is a diagram showing the relationship between changes of V.sub.1, V.sub.2 and V.sub.3 and V.sub.OUT ;
FIG. 3 is a diagram showing currents i.sub.1, i.sub.2 and i.sub.3 corresponding to FIG. 2(a) and 2(b); and
FIG. 4 is a circuit diagram showing another embodiment of the present invention.
Preferred Embodiment of the Present Invention
Hereinafter an embodiment of a weighted summing circuit according to the present invention is described with referance to the attached drawings.
FIG. 1 shows a weighted summing circuit A that has a plural number of parallel connected inductances L.sub.1, L.sub.2 and L.sub.3 connected to a common output. Other terminals of L.sub.1, L.sub.2 and L 3 are connected to input voltages V.sub.1, V.sub.2 and V.sub.3. The output of the weighted summing circuit is connected to a circuit (Figure is omitted) through a capacitance C.
Here, currents flowing in L.sub.1, L.sub.2 and L.sub.3 are defined as current i.sub.1, i.sub.2 and i.sub.3. Also, change rates of each current for time t are defined as di.sub.1 /dt, di.sub.2 /dt and di.sub.3 /dt. The following formulas are obtained approximately.
If both sides of these Formulas 1 to 3 are integrated, then Formulas from 4 to 6 are obtained. Their integration constants are I.sub.1 (O), I.sub.2 (O) and I.sub.3 (O). ##EQU1##
Formula 7 is obtained by Kirchoff's law, then Formula 8 is obtained by substituting Formulas 4, 5 and 6 for Formula 7. ##EQU2##
Formula 8 is changed to Formula 9 through differentiating by t. ##EQU3##
If the admittances corresponding to L.sub.1 and L.sub.2 and L.sub.3 are defined as a.sub.1, a.sub.2 and a.sub.3, then Formula 10 is obtained.
Formula 9 can be changed into Formula 11 by expressing it in terms of V.sub.OUT and substituting the admittances of Formula 10
This Formula is equal to a weighted sum of V.sub.1, V.sub.2 and V.sub.3.
As an example of input signals, if
then Formula 15 is obtained.
Driving the circuit in FIG. 1 by an analog simulator in a condition of L1=L2=L3 is shown by FIG. 2(a) and FIG. 2(b). As a result of this experiment, where V.sub.1, V.sub.2 and V.sub.3 are provided as shown in FIG. 2(b), it was established that V.sub.OUT and the logical value of Formula 11 substantially coincide. In addition, V.sub.OUT corresponds to a weighted summation of V.sub.1, V.sub.2, and V.sub.3. In addition, increasing the frequency reduces the consumed current.
FIG. 4 is a circuit including resistances R.sub.1, R.sub.2 and R.sub.3 connected to each inductance L.sub.1, L.sub.2 and L.sub.3 in series and a voltage follower circuit VF, instead of capacitance C. As a result, inductances L.sub.1, L.sub.2 and L.sub.3 are protected from breakdown due to Joule's heat by resistances R.sub.1, R.sub.2 and R.sub.3, and the input impedance for the voltage follower circuit VF is large. Values of these resistances R.sub.1, R.sub.2 and R.sub.3 are relatively small and can be ignored when inductances L.sub.1, L.sub.2 and L.sub.3 are high with increasing frequency of currents i.sub.1, i.sub.2 and i.sub.3.
Formula 11 is converted into a general formula for an arbitrary number of inductances, and Formula 16 is obtained. ##EQU4##
As mentioned above, a weighted summing circuit according to the present invention has a summing voltage as a common output to a plurality of parallel connected inductances and is capable of performing a weighted summation using small scale and circuit at a high accuracy and is easily available for a various kinds of calculation devices.
Claims
What is claimed is:
1. A weighted summing circuit comprising: i) a plurality of inductances, each of said inductances having a first terminal and a second terminal, each said second terminal being connected together; ii) a plurality of voltage sources, wherein a separate voltage source is operatively connected to said first terminal of each inductance, each of said voltage sources producing an input voltage that varies independently of said each input voltage of others of said voltage sources and having an amplitude that is continuously variable over a range of finite slopes and over a range of voltage levels; and iii) a common output operatively connected to said second terminal of each said inductance for conducting an output of said plurality of inductances corresponding to a weighted sum of said input voltages provided by said plurality of voltage sources.
2. A weighted summing circuit as defined in claim 1, wherein said common output is operatively connected to a circuit through a capacitance.
3. A weighted summing circuit as defined in claim 1, wherein said common output is connected to a gate of a field-effect transistor.
4. A weighted summing circuit as defined in claim 1, further comprising at least one resistance connected in series with each of said inductances.
5. A method of determining a weight sum of a plurality of input voltages comprising: providing each input voltage in said plurality of input voltages to a first terminal of each of a plurality of inductances, each of said inductances having a second terminal, connected together, each input voltage in said plurality of said input voltages varying independently of other input voltages in said plurality of input voltages, and each input voltage in said plurality of input voltages having an amplitude that is continuously variable over a range of finite slopes and over a range of voltage levels; and monitoring an output from said second terminals of said inductances, said output corresponding to a weighted sum of said input voltages of said voltage sources.
6. A method as defined in claim 5, further comprising connecting said output to a circuit through a capacitance.
7. A method as defined in claim 5, further comprising connecting said output to a gate of a field-effect transistor.
Patent Citations (6)
Non-Patent Literature (3)
- Sedra and Smith, Microelectronic Circuits, 1991, FIG. 5.10(a).
- Nilsson, Electric Circuits, 1983, p. 401.
- McPherson, An Introduction to Electrical Machines and Transformers, 1981, p. 257.