Global Communication Interrupt Control System for Communication Between Real and Virtual Machine Systems Using Global Communication Functions of a Shared Memory

The present invention generally relates to global communication interrupt control systems, and more particularly to a global communication interrupt control system which is used when making a communication between a real machine system and a virtual machine system using a global communication function of a shared memory.

In this specification, the global communication function will hereinafter also be referred to as a global signal processor (GSIGP).

A large computer system made up of a plurality of computer systems has various applications. In one example of such applications, a system storage unit which is provided as an external storage is shared by a real machine of one computer system and a guest virtual machine (guest VM) which is a virtual machine of another computer system. In this case, effective utilization of a central processing unit (CPU) by the virtual machine can be realized, while realizing a high-speed hot stand-by and a high-speed process by the plurality of computer systems.

When realizing a communication between the real machine and the virtual machine of different computer systems using the global signal processor (GSIGP), hardware is provided to hold a communication interrupt request at the virtual end and to cancel the interrupt hold when the interrupt is reflected to the virtual machine. The interrupt hold state can constantly be monitored by hardware of the real machine which is the source of the interrupt request. If the interrupt hold of the interrupt request is cancelled, it is determined that the interrupt is reflected or sent to the virtual machine and the operation continues to a next process.

If the communication interrupt is issued from the real machine of one computer system to the virtual machine of another computer system, a guest VM which is provided as the virtual machine is put into an operable state by a control program (CP) which is known as a virtual machine (VM) monitor program. The interrupt is first reflected to the control program (CP), and is thereafter reflected to the guest VM. However, the interrupt hold is cancelled at the stage when the interrupt is reflected to the control program (CP). For this reason, although the interrupt is actually not yet reflected to the guest VM, it appears to the source of the interrupt request as if the interrupt has been reflected to the guest VM, and it is desirable to improve the system in this respect.

On the other hand, if the global signal processor (GSIGP) function were used by the real machine system to realize an initial program load (IPL) function of a virtual machine system, the IPL would be made to the control program (CP) and not to the guest VM. As a result, it would be impossible in this case to carry out an accurate process with respect to the guest VM. Moreover, there is a problem in that the real machine system cannot be aware of the actual state of the virtual machine system.

Accordingly, it is a general object of the present invention to provide a novel and useful global communication interrupt control system in which the problems described above are eliminated.

Another and more specific object of the present invention is to provide a global communication interrupt control system comprising a real machine system including one or a plurality of real machines, a virtual machine system including one or a plurality of virtual machines which are realized by an operating system and a control program which makes the virtual machines operable, and a shared memory which is shared by the real machine system and the virtual machine system: The shared memory includes global communication means for making or establishing communication between an arbitrary real machine of the real machine system and an arbitrary virtual machine of the virtual machine system. The real machine includes means for issuing an interrupt of a communication request with respect to a specific virtual machine using the global communication means, and the virtual machine system includes hold means for holding the interrupt from the real machine and reflecting the interrupt to the control program, and cancel means for cancelling the holding of the interrupt by the hold means at a time when the control program reflects the interrupt to the specific virtual machine, so that the hold means maintains a held state of the interrupt until the interrupt is actually reflected to the specific virtual machine. According to the global communication interrupt control system of the present invention, it is possible to accurately confirm, from the real machine system, whether or not the interrupt is actually reflected to the specific virtual machine of the virtual machine system. As a result, it is possible to realize a global communication between the real machine and the virtual machine using the global communication means, in the same manner as the communication between the real machines. Therefore, the operation efficiency and the system reliability of a composite computer system which shares the shared memory between the real machine system and the virtual machine system are considerably improved by the present invention.

Still another object of the present invention is to provide an interrupt control system comprising a real machine system including one or a plurality of real machines, a virtual machine system including one or a plurality of virtual machines which are realized by an operating system and a control program which makes the virtual machines operable, and a shared memory which is shared by the real machine system and the virtual machine system. In this system, the shared memory includes global communication means for making a communication between an arbitrary real machine of the real machine system and an arbitrary virtual machine of the virtual machine system; the real machine includes means for issuing an interrupt of a request with respect to a specific virtual machine using the global communication means; and the virtual machine system includes hold means for holding the interrupt from the real machine and reflecting the interrupt to the control program, and cancel means for cancelling the holding of the interrupt by the hold means at a time when the control program reflects the interrupt to the specific virtual machine, so that the hold means maintains a held state of the interrupt until the interrupt is actually reflected to the specific virtual machine. According to the interrupt control system of the present invention, it is possible to accurately confirm from the FIG. 1 machine system whether or not the interrupt is actually reflected to the specific virtual machine of the virtual machine system.

Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.

FIG.1 is a system block diagram for explaining an example of a conventional global communication between real machine systems;

FIG. 2 is a diagram for explaining a conventional communication procedure between the real machine systems in FIG. 1;

FIG. 3 is a diagram for explaining a conceivable communication procedure between a real machine system and a virtual machine system;

FIG. 4 is a flow chart for explaining a conceivable communication process between the real machine system and the virtual machine system in FIG. 3;

FIG. 5 is a flow chart for explaining a conceivable initial program load (IPL) function of the virtual machine system using a GSIGP interrupt;

FIG. 6 is a system block diagram for explaining the operating principle of the present invention;

FIG. 7 is a system block diagram showing a composite computer system which is applied with an embodiment of a global communication interrupt control system according to the present invention;

FIG. 8 is a diagram for explaining an interrupt request hold and an interrupt to a control program in the embodiment;

FIG. 9 is a diagram for explaining a determination of a guest VM and an interrupt hold by the control program, and an interrupt to the guest VM in the embodiment;

FIG. 10 is a diagram for explaining a cancellation of the interrupt hold in the embodiment;

FIG. 11 is a flow chart for explaining a communication process between the real machine and the virtual machine in the embodiment; and

FIG. 12 is a flow chart for explaining an initial program load (IPL) function of the virtual machine in the embodiment.

First, a description will be given of the problem encountered in the conventional system.

An example of a conventional global communication between real machine systems will be described with reference to FIG. 1. A composite computer system shown in FIG. 1 includes a plurality of real machine systems 12-1 and 12-2 which use a system storage unit 20 as a shared memory 20. In FIG. 1, only two real machine systems are shown for the sake of convenience. A global communication between the real machine systems 12-1 and 12-2 is realized by a global signal processor (GSIG P) 22 provided in the shared memory 20, and it is possible to accurately be aware of the held and reflected states of an interrupt.

FIG. 2 is a diagram for explaining an example of a conventional communication procedure between the Peal machine systems 12-1 and 12-2. In FIG. 2, an interrupt of a communication request, which is issued from a real machine 10-1 of the real machine system 12-1, is held within hardware which is provided in the receiving real machine system 12-2. This held state of the interrupt can be monitored from the source of the interrupt, that is, by the real machine 10-1. More particularly, a process is carried out according to the following procedures [1] through [3] in FIG. 2.

[1] The real machine 10-1 of the real machine system 12-1 issues the interrupt of the communication request so as to communicate with a real machine 10-2 of the real machine 12-2.

[2] The real machine system 12-2 which receives the interrupt from the real machine 10-1 holds the interrupt by a hardware thereof if the interrupt cannot be reflected to the real machine 10-2. In this state, the held state of the interrupt can be confirmed from the real machine 10-1 which is the source of the interrupt.

[3] When it becomes possible to reflect the interrupt to the real machine 10-2, the hardware of the real machine system 12-2 reflects the interrupt to the real machine 10-2. Since the held state of the interrupt is cancelled at the time when the interrupt is reflected to the real machine 10-2, it is possible to confirm, from the real machine 10-1, that the interrupt has been reflected to the real machine 10-2.

However, if the second computer system, which shares the shared memory with the first computer system, is not a real machine and is a guest VM which functions as a virtual machine operable in an operating system (OS) by a control program (CP) which is known as a VM monitor program, a problem occurs when the interrupt of the communication request is issued from the real machine to the guest VM using the global signal processor (GSIGP) similarly as in the case where the first and second computer systems as both real machines. In other words, the interrupt is first reflected to the control program (CP) which makes the guest VM operable in the receiving virtual machine system, and the interrupt is thereafter reflected to the guest VM from the control program (CP). For this reason, the hardware of the virtual machine system which holds the interrupt cancels the held state of the interrupt at the time when the interrupt is reflected to the control program (CP), and the real machine system which is the source cannot accurately judge the held and reflected states of the interrupt in the virtual machine system.

FIG. 3 is a diagram for explaining a conceivable communication procedure between a real machine system and a virtual machine system. A process is carried out according to the following procedures [1] through [4] in FIG. 3.

[1] A real machine 10 of a real computer system 12 is issued an interrupt of a communication request so as to communicate with a guest VM 14 of a virtual machine system 18.

[2] The virtual machine system 18 which receives the interrupt from the real machine 10 holds the interrupt by a hardware thereof if the interrupt cannot be reflected to a control program (CP) 16 of the virtual machine system 18. In this state, the held state of the interrupt can be confirmed from the real machine 10 which is the source of the interrupt.

[3] The hardware of the virtual machine system 18 reflects the interrupt to the control program (CP) 16 when it becomes possible, and the held state of the interrupt is cancelled at the same time. Hence, from the real machine 10 which is the source of the interrupt, it appears as if the interrupt has been reflected to the guest VM 14. However, at this point in time, the interrupt is not yet reflected to the guest VM 14.

[4] Based on the contents of the interrupt which is generated, the control program (CP) 16 reflects the interrupt to the guest VM 14 when it becomes possible.

FIG. 4 is a flow chart for explaining the conceivable communication process between the real machine system 12 and the virtual machine system 18 in FIG. 3.

In FIG. 4, the software of the real machine 10 issues a GSIGP interrupt in a step S1. The hardware of the real machine system 12 modifies a main storage control unit (MCU) of the other hardware in a step S2.

Then, the hardware of the virtual machine system 18 turns ON a GSIGP interrupt bit of the MCU in a step S3. In addition, the hardware of the virtual machine system 18 generates the GSIGP interrupt with respect to the control program (CP) 16, and simultaneously cancels the held state of the GSIGP interrupt, in a step S4.

On the other hand, the software of the virtual machine system 18 reflects the GSIGP interrupt from the hardware to the control program (CP) 16 in a step S5, and holds the GSIGP interrupt in the guest VM 14 in a step S6. Further, the control is handed over to the guest VM 14 in a step S7, and the reflection of the GSIGP interrupt is detected in a step S8. If the reflection of the GSIGP interrupt to the guest VM 14 is detected in the step S8, the held state of the GSIGP interrupt in the control program (CP) 16 is cancelled in a step S9.

Hence, the hardware of the virtual machine system 18 turns OFF the GSIGP interrupt bit in a step S10 in response to the cancellation of the held state in the step S9.

On the other hand, the held and reflected states of the GSIGP interrupt can be monitored from the source of the GSIGP interrupt, that is, the software of the real machine 10. More particularly, the software of the real machine 10 investigates the state of the virtual machine system 18 in a step S11, and the cancellation of the held state of the GSIGP interrupt is detected in a step S12.

But as may be seen from the step S4, the held state is cancelled simultaneously as the generation of the GSIGP interrupt with respect to the control program (CP) 16. As a result, it appears to the real machine 10 as if the GSIGP interrupt has been reflected to the guest VM 14 at the time when the GSIGP interrupt is actually only reflected to the control program (CP) 16. For this reason, even though the GSIGP interrupt may actually still be in the held state with respect to the guest VM 14, it appears to the real machine 10 as if the GSIGP interrupt has successfully been reflected to the guest VM 14.

Therefore, there is a problem in that the real machine 10, which is the source of the GSIGP interrupt, cannot accurately judge the held and reflected states of the GSIGP interrupt with respect to the intended guest VM 14. Consequently, an incorrect judgement as to the held and reflected states of the GSIGP interrupt in the real machine 10 may trigger erroneous operations within the complex computer system.

On the other hand, if the global signal processor (GSIGP) function were used by the real machine system 12 to realize an initial program load (IPL) function of the virtual machine system 18, the IPL would be made to the control program (CP) 16 and not to the guest VM 14. As a result, it would be impossible in this case to carry out an accurate process with respect to the guest VM 14, and there is a problem in that the real machine system 12 cannot be aware of the actual state of the virtual machine system 18.

FIG. 5 is a flow chart for explaining this conceivable initial program load (IPL) function of the virtual machine system 18 using the GSIGP interrupt. In FIG. 5, those steps which are essentially the same as those corresponding steps in FIG. 4 are designated by the same reference numerals, and a description thereof will be omitted.

In FIG. 5, the software of the real machine 10 issues a GSIGP interrupt of an IPL request in a step S1 so as to realize the IPL function of the virtual machine system 18. The hardware of the real machine system 12 modifies a main storage control unit (MCU) of the other hardware in a step S2.

Then, the hardware of the virtual machine system 18 stores IPL information of the MCU and makes an IPL to the control program (CP) 16 in a step S22.

Hence, even though an IPL was intended to be made to the guest VM 14 which is controlled by the control program (CP) 16, no IPL is made to the guest VM 14 because the IPL is made to the control program (CP) 16.

The object of the present invention is to eliminate the above described problems of the conceivable system.

A description will now be given of the operating principle of the present invention, by referring to FIG. 6.

In FIG. 6, a real machine system 12 is provided with one or a plurality of real machines 10. A virtual machine system 18 is provided with one or a plurality of virtual machines (guest VMs) 14 which are realized by an operating system (OS), and a control program (VM monitor program) 16 which makes the virtual machine 14 operable. A shared memory 20 is shared by the real machine system 12 and the virtual machine system 18. This shared memory 20 is provided with a global signal processor (GSIGP) 22 which carries out a communication between the real machine system 12 and the virtual machine system 18. The present invention relates to the global communication interrupt control system which is applicable when a communication request is issued from the real machine 10 to the virtual machine 14 and a communication interrupt control is made in the virtual machine 14.

In the present invention, if an interrupt of a communication request is issued from the real machine 10 of the real machine system 12 to the guest VM 14 of the virtual machine system 18, this interrupt is held in the virtual machine system 18 and is reflected to the control program (CP) 16 by a hold means 24. This hold means 24 maintains the held state of the interrupt until the control program (CP) 16 further reflects the interrupt to the guest VM 14. Hence, from the real machine 10 which is the source of the interrupt, the held state of the interrupt is maintained in the hold means 24 until the interrupt is actually reflected to the guest VM 14. In addition, a hold cancel means 26 of the virtual machine system 18 cancels the held state of the interrupt in the hold means 24 at the time when the control program (CP) 16 reflects the interrupt to the guest VM 14.

Accordingly, the held state of the interrupt is maintained in the hold means 24 until the interrupt is actually reflected to the guest VM 14. As a result, the interrupt to the guest VM 14 can be correctly recognized by the real machine 10 which is the source of the interrupt.

Next, a description will be given of an embodiment of a global communication interrupt control system according to the present invention. FIG. 7 shows a composite computer system which includes this embodiment of the global communication interrupt control system according to the present invention.

In FIG. 7, computer systems 30-1, 30-2, ..., 30-n are coupled via a system bus 46 and share a system storage unit (SSU) 20 which is used as a shared memory. The computer systems 30-1, 30-2, ..., 30-n respectively have the same construction, and a description will only be given with respect to the construction of the computer system 30-1. In addition, only the constructions of the computer systems 30-1 and 30-2 are shown in FIG.7.

In this embodiment, the computer system 30-1 includes two central processing units (CPUs) 32-1 and 32-2, and a main storage unit (MSU) 36 is provided with respect to these CPUs 32-1 and 32-2 via a main storage control unit (MCU) 34. In addition, a system bus 40 for the subsystem is coupled to the MSU 36 via a channel processor (CHP) 38, so as to connect an external unit via the system bus 40.

The system bus 40 in this embodiment is coupled to magnetic disk units 44 via a device interface 42. The magnetic disk units 44 are used as direct access storage devices (DASDs). Further, the system bus 40 may be coupled to a communication line via another device interface 46, or to an appropriate terminal via the device interface 46 and a local area network (LAN), for example.

The SSU 20 is provided with a global signal processor (GSIGP) function 22 which enables communications among the computer systems 30-1 through 30-n. On the other hand, hardware and software necessary to make the global communication using the GSIGP function 22 are provided within the MCU 34 of each of the computer systems 30-1 through 30-n, in correspondence with the GSIGP function 22 of the SSU 20.

For example, the CPU 32-1 within the computer system 30-1 executes an operating system (OS) of the MSU 36 as a real machine. On the other hand, the CPU 32-2 executes an OS of the MSU 36 as a guest VM of a virtual machine, and in order to make the guest VM operable, the CPU 32-2 simultaneously executes a control program (CP) of the MSU 36 known as a VM monitor program. Normally, the OS which is executed by the CPU 32-2 executes a plurality of guest VMs, and one control program (CP) controls the plurality of guest VMs.

Accordingly, the CPU 32-1 of the computer system 30-1 shown in FIG. 7 functions as the real machine 10 shown in FIG. 6, and the CPU 32-2 of the computer system 30-1 shown in FIG. 7 operates as the control program (CP) 16 and the guest VM 14 within the virtual machine system 18 shown in FIG. 6. Furthermore, the interrupt hold means 24 and the hold cancel means 26 of the virtual machine system 18 shown in FIG. 6 is provided in the MCU 34 of the computer system 30-1 shown in FIG. 7. In this embodiment, the interrupt hold means 24 and the hold cancel means 26 are realized by hardware of the MCU 34.

Similarly, a CPU 32-3 of the other computer system 30-2 realizes a real machine, and a CPU 32-4 of this other computer system 30-2 realizes a control program (CP) and a guest VM.

A global communication is made between the computer systems 30-1 and 30-2. In other words, the global communication is made from a real machine which is realized by the CPU 32-1 of the computer system 30-1 to a specific guest VM out of the plurality of guest VMs realized by the CPU 32-4 of the other computer system 30-2, using the GSIGP function 22 of the SSU 20.

The communication interrupt control in the composite computer system shown in FIG. 7 will now be described with reference to FIGS. 8, 9 and 10.

FIGS. 8, 9 and 10 shows the operation of this embodiment in phases (1) through (5) when the communication is made from the real machine 10 which is realized by the CPU 32-1 of the computer system 30-1 shown in FIG. 7 to a specified guest VM 14-1 out of the plurality of guest VMs 14-1 and 14-2 which are realized by the CPU 32-4 of the other computer system 30-2 shown in FIG. 7, using the GSIGP function 22 of the SSU 20 which is used as the shared memory.

As shown in FIG. 8, the computer system 30-1 is provided with a hardware 48 which executes a communication procedure in conformance with the GSIGP function 22 of the SSU 20. On the other hand, an interrupt hold device 24 which is realized by hardware, and a control program (CP) 16, which is realized by the OS of the CPU 32-4, are provided in the virtual machine system which is realized by the computer system 30-2. In addition, as shown in FIG. 9, two guest VMs 14-1 and 14-2 which are realized by the OS executed by the CPU 32-4 are also provided in the virtual machine system which is realized by the computer system 30-2. The phases (1) through (5) are carried out as follows.

Phase (1):

In order to communicate to the computer system 30-2 shown in FIG. 8, the real machine 10 of the computer system 30-1 issues an interrupt of a communication request using the GSIGP function 22 of the SSU 20.

Phase (2):

The interrupt hold device 24 of the computer system 30-2 which receives the interrupt of the communication request from the computer system 30-1, holds the interrupt by hardware. In this state, the real machine 10 which is the source of the issued interrupt can confirm that this interrupt is in the held state at the virtual machine system which is realized by the computer system 30-2.

The interrupt hold device 24 generates the interrupt when it becomes possible to reflect the interrupt to the control program (CP) 16 of the virtual machine system. According to the conceivable system described above, the held state of the interrupt is cancelled when the interrupt is generated with respect to the control program (CP) 16. However, in this embodiment, the interrupt hold device 24 maintains the held state of the interrupt even after the interrupt is generated. Accordingly, even if the interrupt is generated with respect to the control program (CP) 16, the real machine 10 which is the source of the interrupt continues to confirm that the interrupt is in the held state at the virtual machine system.

Phase (3):

As shown in FIG. 9, the control program (CP) 16 of the virtual machine system determines the guest VM which is to reflect the interrupt, based on the interrupt which is generated from the interrupt hold device 24. In this case, the control program (CP) 16 holds the interrupt with respect to the guest VM 14-1.

Phase (4):

The control program (CP) 16 generates the interrupt to the guest VM 14-1 at the time when it becomes possible to reflect the interrupt to the guest VM 14-1. The interrupt hold device 24 still maintains the held state of the interrupt even at the time when the control program (CP) 16 generates the interrupt to the guest VM 14-1. Accordingly, the real machine 10 which is the source of the interrupt continues to confirm that the interrupt is in the held state at the virtual machine system.

Phase (5):

Next, as shown in FIG. 10, the control program (CP) 16 controls a cancel device 26 to cancel the held state of the interrupt in the interrupt hold device 24 after confirming that the interrupt generated from the control program (CP) 16 is reflected to the guest VM 14-1. As a result, the real machine 10 which is the source of the issued interrupt can accurately confirm that the interrupt of the communication request has been reflected to the intended guest VM 14-1. In other words, the real machine 10 can correctly judge that the global communication request was successfully made, and continue to a next process.

FIG. 11 is a flow chart for explaining the communication process between the real machine system and the virtual machine system in this embodiment. In FIG. 11, those steps which are essentially the same as those corresponding steps in FIG. 4 are designated by the same reference numerals.

In FIG. 11, the software of the real machine 10 issues a GSIGP interrupt in a step S1. The hardware of the real machine system (computer system 30-1) modifies the MCU of the other hardware in a step S2.

Then, the hardware of the virtual machine system (computer system 30-2) turns ON a GSIGP interrupt bit of the MCU in a step S3. In addition, the hardware of the virtual machine system generates the GSIGP interrupt with respect to the control program (CP) 16, but maintains the held state of the GSIGP interrupt, in a step S31.

On the other hand, the software of the virtual machine system reflects the GSIGP interrupt from the hardware to the control program (CP) 16 in a step S5, and holds the GSIGP interrupt in the guest VM 14-1 in a step S6. Further, the control is handed over to the guest VM 14-1 in a step S7, and the reflection of the GSIGP interrupt is detected in a step S8. If the reflection of the GSIGP interrupt to the guest VM 14-1 is detected in the step S8, the held state of the GSIGP interrupt in the control program (CP) 16 is cancelled in a step S9.

Hence, the hardware of the virtual machine system turns OFF the GSIGP interrupt bit in a step S10 in response to the cancellation of the held state in the step S9.

On the other hand, the held and reflected states of the GSIGP interrupt can be monitored from the source of the GSIGP interrupt, that is, the software of the real machine 10. More particularly, the software of the real machine 10 investigates the state of the virtual machine system in a step Sll, and the cancellation of the held state of the GSIGP interrupt is detected in a step S12.

However, as may be seen from FIG. 11, the held state is cancelled simultaneously as the generation of the GSIGP interrupt with respect to the control program (CP) 16. As a result, the real machine 10 can confirm that the GSIGP interrupt has been reflected to the guest VM 14-1 at the time when the GSIGP interrupt is actually reflected to the guest VM 14.

Next, a description will be given of an initial program load (IPL) function of the virtual machine system using the GSIGP function 22.

FIG. 12 is a flow chart for explaining this IPL function of the virtual machine system. In FIG. 12, those steps which are essentially the same as those corresponding steps in FIG. 5 are designated by the same reference numerals.

In FIG. 12, the software of the real machine 10 issues a GSIGP interrupt of an IPL request in a step S1 so as to realize the IPL function of the virtual machine system. The hardware of the real machine system modifies the MCU of the other hardware in a step S2.

Then, the hardware of the virtual machine system stores IPL information of the MCU, turns ON the GSIGP interrupt bit of the MCU, and holds the interrupt in a step S41.

A service processor (SVP) 66, which is independent of the hardware and software of the virtual machine system (30-2) in FIG. 12, is coupled to the SU 36 as indicated by a dotted line in FIG. 7. This service processor 66 carries out service processes such as supervision. The service processor 66 starts a time supervision in a step S42 when the GSIGP interrupt is held in the step S41.

At the same time, the software of the virtual machine system investigates the IPL information in a step S45, and a decision is made in a step S46 as to whether or not the GSIGP interrupt is held. If the decision result in the step S46 is YES, the control program (CP) 16 makes the IPL to the VM 14 in a step S47, and the held state of the GSIGP interrupt is cancelled in a step S48.

If the IPL of the intended VM 14 is not completed within a time out period and a decision result in a step S44 is NO, the control program (CP) 16 is stopped because it is judged in this case that an abnormality has occurred. On the other hand, if the decision result in the step S44 is YES, the GSIGP interrupt bit of the MCU is turned OFF in a step S10.

Accordingly, the real machine 10 which is the source of the interrupt of the IPL request can investigate the state of the virtual machine system in the step Sll and decide in the step S12 whether or not the held state of the interrupt has been cancelled, so as to determine whether or not the IPL to the intended VM 14 has been completed.

In the embodiment described above, it was described for the sake of convenience that the communication is made from the CPU 32-1 of the computer system 30-1 shown in FIG. 7 to the guest VM which is realized by the CPU 32-4 of the other computer system 30-2. However, a communication can be made exactly in the same manner between the CPU of an arbitrary one of the computer systems 30-1 through 30-n and a guest VM which is realized by the CPU of another one of the computer systems 30-1 through 30-n.

Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.