Timing Generator

This invention relates to the generation of timing signals for electronic systems.

Timing signals which make periodic transitions between low and high voltage levels are used in digital electronic systems to control system operation. The signal transitions (or edges) define successive instants at which activities or operations can occur in a digital system.

The timing signals in a digital system are typically produced with the assistance of an oscillator, such as a crystal oscillator, that supplies clock pulses. The power consumption of a system that uses an oscillator to produce clock pulses increases with the oscillation frequency. Although crystal oscillators can reach frequencies of several hundred megahertz, a clock oscillator operating at such a frequency normally cannot be utilized with most state-of-the-art integrated circuits because the circuit power consumption would be too great. Excessive heat would be generated. In addition, a high-frequency oscillator introduces significant electromagnetic interference which is difficult to deal with and reduces system reliability.

Delay lines that delay signal transitions to create desired time intervals are also used to produce timing signals. Unfortunately, precision delay lines typically include inductors which cannot readily be incorporated into integrated circuits. It would be quite desirable to have a low-power technique for generating finely controllable timing signals having sharp transitions.

Hoffman, U.S. Pat. No. 5,073,730, disclose a circuit for controlling peak transition current in data buses of VLSI chips. Hoffman's circuit includes a ring oscillator formed with multiple high speed inverters arranged in a loop to produce a set of control signals with short time delay between them. The control signals are directly used to sequence the switching of the bus drivers so that the transients are spread over a time interval which is relatively short compared to the bus transfer cycle but allows time for some driver transients to end before others begin. In his circuit, Hoffman utilizes the control signals in producing further signals. However, each of the further signals is generated from only one of the control signals and therefore does not have rising and/or falling edges that correspond to transitions of two or more of the control signals.

The present invention furnishes a timing generator capable of producing finely controlled timing signals having sharp edges. The characteristics of the timing signals are typically indicative of an oscillator that runs faster than any oscillator which is used in the timing generator or whose oscillation signal is supplied as a clock input to the timing generator. For example, if a reference clock at 25-30 MHz is supplied to the timing generator of the invention, the generator can generate timing signals indicative of a 200-MHz oscillator even though none of generator's components actually run at more than 25-30 MHz. The timing generator also produces its timing signals at considerably reduced power dissipation compared to what would arise from using an oscillator whose oscillation frequency equals the frequency seemingly indicated by the characteristics of the timing signals.

Specifically, the present timing generator contains an oscillator section and a timing-signal generating section. The oscillator section is formed with a plural number of oscillator stages for respectively producing a like number of corresponding stage signals that sequentially move between signal levels at a basic oscillator frequency. The oscillator section is typically implemented as a ring oscillator. Each oscillator stage is then an inverting stage. In response to the stage signals, the generating section generates at least one timing signal having at least two transitions corresponding to transitions of two or more of the stage signals. For example, in a simple case, such a timing signal could consist of a periodic series of high-level pulses where the rising and falling edges of each pulse respectively correspond to rising edges of two different stage signals.

The timing generator typically includes a control section, preferably arranged in a phase-locked loop, for causing the oscillator frequency to have a substantially fixed relationship to a reference frequency. The reference frequency is defined by a reference signal supplied to the timing generator.

Consider the case in which the oscillator frequency substantially equals the reference frequency. Let N be the number of stages in the oscillator section. Although each stage runs at the oscillator frequency and thus substantially at the reference frequency, the time between a transition of the stage signal of one stage and the resulting transition of the stage signal of the next stage is approximately one Nth the time between consecutive transitions of the reference signal. As a group, the stage signals appear to make transitions at a frequency equal to N times the reference frequency.

At least two (and typically the great majority) of the transitions of each timing signal produced by the present timing generator correspond, as mentioned above, to transitions of at least two of the stage signals. Consequently, the locations of the transitions in each timing signal correspond to a frequency equal to N times the reference frequency even though the reference frequency is the highest frequency in the timing generator. The invention thereby achieves the benefit of an oscillator that runs at very high frequency, such as 200 MHz, without incurring the increased power usage and other problems that would arise if such an oscillator were actually used in or with the present timing generator.

FIG. 1 is a block diagram of a timing generator in accordance with the invention.

FIG. 2 is a simplified graph of stage signals as a function of time for the ring oscillator in the timing generator of FIG. 1.

FIG. 3 is a block diagram of a preferred embodiment of the timing generator of FIG. 1.

FIG. 4 is a circuit diagram of an inverting stage in the ring oscillator of the timing generator of FIG. 3.

FIG. 5 is a block diagram of the timing generator of FIG. 3 with the components of the timing-signal generating logic broken out in special detail.

FIG. 6 is a simplified graph of stage and pulse signals as a function of time for the timing generator of FIGS. 3 and 5.

FIG. 7 is a simplified graph of counting and sequencing signals as a function of time for the timing generator of FIGS. 3 and 5.

FIGS. 8a and 8b are circuit diagrams of exemplary portions of the random decode logic and output timing latches in the timing generator of FIGS. 3 and 5.

FIGS. 9a and 9b are graphs for the time variation of certain signals in the circuit portions of FIGS. 8a and 8b.

FIGS. 10a and 10b are block diagrams of alternative timing generators in accordance with the invention.

The low and high levels of the voltages illustrated in FIGS. 6, 7, 9a, and 9b are, for simplicity, respectively illustrated as "0" and "1". Like reference symbols are employed in the drawings and in the description of the preferred embodiments to represent the same or very similar item or items.

Referring to the drawings, FIG. 1 illustrates a timing generator in accordance with the teachings of the invention. This timing generator produces M timing signals V.sub.T1, V.sub.T2, ... V.sub.TM (collectively "V.sub.T ") for controlling the operation of circuitry (not shown) such as dynamic random-access memories, pulse-width modulators, one-shot multivibrators, and other such digital devices that require fine timing. The timing generator consists of an oscillator section 10, a control section 12, and timing-signal generating logic 14.

Oscillator section 10 is a ring oscillator formed with an odd number N of substantially identical inverting stages S.sub.1, S.sub.2, ... S.sub.N arranged in a loop. Each inverting stage S.sub.i, where i is an integer running from 1 to N, has a stage input (terminal) and a stage output (terminal). The stage input of each inverting stage S.sub.i, except for stage S.sub.1, is connected to the stage output of previous stage S.sub.i-1. The S.sub.1 stage input is connected to the S.sub.N stage output to complete the oscillator loop.

Inverting stages S.sub.1 - S.sub.N respectively produce N corresponding stage signals V.sub.S1, VS.sub.2, ... V.sub.SN (collectively "V.sub.S ") that repeatedly switch between a low voltage level V.sub.SL and a high voltage level V.sub.SH at a basic oscillator frequency f.sub.O. Each inverting stage S.sub.i, except for stage S.sub.1, generates its stage signal V.sub.Si by inverting stage signal V.sub.Si-1 from previous stage S.sub.i-1. Stage S.sub.1 generates stage signal V.sub.S1 by inverting stage signal V.sub.N from stage S.sub.N. Each time that a stage voltage V.sub.Si moves from low level V.sub.SL to high level V.sub.SH or vice versa constitutes a signal transition or edge. As discussed further below, at least one of timing signals V.sub.T contains pulses whose rising and falling edges correspond to transitions of at least two different stage signals V.sub.S.

Ring oscillator 10 and control section 12 are configured in a phase-locked loop that forces oscillator frequency f.sub.O to be substantially equal to a reference clock frequency f.sub.R. Control 12 consists of a phase/frequency comparator 16 and a low-pass analog filter 18.

Phase/frequency comparator 16 receives two input signals: (a) a reference clock voltage signal V.sub.R at frequency f.sub.R and (b) an arbitrary one of signals V.sub.S at frequency f.sub.O. Reference voltage V.sub.R is supplied from a reference oscillator (not shown). FIG. 1 illustrates the case in which the particular V.sub.S input signal supplied to comparator 16 is stage signal V.sub.S1. Comparator 16 compares frequency f.sub.O of signal V.sub.S1 to frequency f.sub.R of signal V.sub.R and generates a comparison voltage signal V.sub.B whose value depends on whether f.sub.O is greater than f.sub.R or less than f.sub.R. Internally, comparator 16 operates by comparing the V.sub.S1 phase to the V.sub.R phase.

Filter 18, which typically includes a grounded capacitor, filters comparison signal V.sub.B to produce a control voltage V.sub.C that is largely a DC signal. DC voltage V.sub.C is approximately proportional to frequency f.sub.O at steady-state.

Each inverting stage S.sub.i has a control input (terminal) that receives control voltage V.sub.C. Stages S.sub.1 -S.sub.N are configured in such a way that frequency f.sub.O varies with voltage V.sub.C. When f.sub.O is less than f.sub.R, voltage V.sub.C is provided at such a value as to cause f.sub.O to increase. The opposite occurs when f.sub.O is greater than f.sub.R. Accordingly, the phase-locked loop causes f.sub.O to be substantially equal to f.sub.R -i.e., the phase-locked loop locks onto f.sub.R.

The stage-signal transmission delay through each inverting stage S.sub.i (from the S.sub.i stage input to the S.sub.i stage output) is substantially the same for all of stages S.sub.1 - S.sub.N because they are substantially identical. Let .tau. represent the stage-signal transmission delay through each stage S.sub.i. Each stage signal V.sub.si, except for signal V.sub.S1, thus makes a transition in one direction approximately .tau. after previous stage signal V.sub.si-1 makes a transition in the other direction. Signal V.sub.S1 makes a transition in one direction approximately .tau. after signal V.sub.SN makes a transition in the other direction. Since the number of stages S.sub.1 - S.sub.N is N, each stage signal V.sub.si also makes a transition in one direction approximately N.tau. after making a transition in the other direction.

The repetition period of ring oscillator 10 is the amount of time between the instants that one of the V.sub.S signals makes consecutive transitions in the same direction. Letting T.sub.O represent the oscillator repetition period, T.sub.O equals 2N.tau.. T.sub.O also equals 1/f.sub.O and therefore approximately equals 1/f.sub.R.

Turning to FIG. 2, it depicts two sets of slanted lines that represent the voltage transitions of stage signals V.sub.S. The upper set of slanted lines illustrates the transitions of signal V.sub.S1 during a time slightly greater than T.sub.O and thus illustrates the oscillator repetition cycle. The lower set of slanted lines illustrates the transitions of all the V.sub.S signals (including the V.sub.S1 signal) during a time slightly greater than T.sub.O.

During each period T.sub.O, each stage signal V.sub.si (including V.sub.S1) makes a low-to-high transition and a high-to-low transition. Hence, the V.sub.S signals together make 2N equally spaced transitions during each period T.sub.O. That is, as a group, the V.sub.S signals make N times as many timewise-distinct transitions as signal V.sub.S1 by itself. Although oscillator 10 operates at frequency f.sub.O, the V.sub.S signals as a group have an effective frequency f.sub.E equal to Nf.sub.O which, in turn, approximately equals Nf.sub.R.

The spacing .tau. between the midpoints of consecutive voltage transitions of the V.sub.S signals is approximately one Nth the spacing between the midpoints of consecutive voltage transitions of reference signal V.sub.R. Likewise, if only transitions in one direction are considered (e.g., only low-to-high transitions), the resultant spacing 2.tau. between the midpoints of consecutive V.sub.S transitions in one direction is approximately one Nth the spacing between the midpoints of consecutive V.sub.R transitions in that direction. The net effect of using ring oscillator 10 and control section 12 is to generate stage signals whose edge spacing is approximately one Nth the edge spacing of voltage V.sub.R supplied by the reference oscillator.

Timing-signal generating logic 14 produces timing signals V.sub.T in response to stage signals V.sub.S. The V.sub.T signals vary between a low voltage level V.sub.TL and a high voltage level V.sub.TH. Each time that each timing signal V.sub.Tj, where j is an integer running from 1 to M, moves from V.sub.TL to V.sub.TH or vice versa constitutes a signal transition or edge.

Timing-signal generating logic 14 is configured in such a way that at least one of timing signals V.sub.T has at least two transitions which correspond to transitions of at least two of stage signals V.sub.S. For instance, one such timing signal V.sub.T typically contains a group of high-level pulses that repeat at a given frequency where the rising and falling edges of each pulse are respectively defined by rising (or falling) edges of two different V.sub.S signals. Typically, most (usually the vast majority) of the V.sub.T signals have at least two edges which correspond to edges of two or more of the V.sub.S signals. Since the time spacing between consecutive transitions of the V.sub.S signals as a group is approximately one Nth the time spacing between the transitions of reference voltage V.sub.R, the characteristics of the V.sub.T signals can accordingly be set in time increments that are N times finer than that available from directly using voltage V.sub.R.

FIG. 3 illustrates a preferred embodiment of the timing generator in FIG. 1 for which the number N of inverting stages S.sub.1 - S.sub.N in oscillator 10 is seven. The number M of signals V.sub.T is three.

Phase/frequency comparator 16 in control section 12 of FIG. 3 consists of a phase comparator 20 and a charge pump 22. Phase comparator 20 compares the phase of stage signal V.sub.S1 to the phase of reference signal V.sub.R and produces a plurality of adjustment signals V.sub.A indicative of the phase difference. Adjustment signals V.sub.A typically consist of (a) a signal and its complement for indicating that the V.sub.S1 phase is ahead of the V.sub.R phase and (b) a further signal and its complement for indicating that the V.sub.S1 phase is behind the V.sub.R phase.

Charge pump 22 generates comparison signal V.sub.B in response to adjustment signals V.sub.A. If the V.sub.S1 phase is behind the V.sub.R phase, comparator 20 provides signals V.sub.A at such values as to cause charge pump 22 to pump up the voltage of signal V.sub.B. Control voltage V.sub.O thereby increases. The reverse occurs if the V.sub.S1 phase is ahead of the V.sub.R phase.

In addition to components 18-22, control section 12 in the timing generator of FIG. 3 contains a voltage complementer 24 that receives control voltage V.sub.C provided from filter 18 in response to comparison signal V.sub.B. Voltage complementer 24 generates a further control voltage signal V.sub.c substantially complementary to control voltage V.sub.C. Each inverting stage S.sub.i has a further control input (terminal) that receives voltage V.sub.c.

FIG. 4 depicts the internal configuration for each inverting stage S.sub.i in the timing generator of FIG. 3. Stage S.sub.i here consists of five (an odd number) of substantially identical individual inverters I.sub.1, I.sub.2, ... I.sub.5 arranged in series. Inverters I.sub.1 - I.sub.5 are connected between a source of a high supply voltage V.sub.HH and a source of a low supply voltage V.sub.LL. Voltage difference V.sub.HH - V.sub.LL is the power-supply voltage for all of inverting stages S.sub.1 - S.sub.7.

Each individual inverter I.sub.k, where k is an integer running from 1 to 5, has a main input, a pair of control inputs, and an output. Control signals V.sub.C and V.sub.C are supplied to the control inputs of each inverter I.sub.k. Inverters I.sub.1 - I.sub.5 respectively produce five output voltage signals V.sub.I1, V.sub.I2, ... V.sub.I5 at their main outputs by respectively inverting signals V.sub.si-1 and V.sub.I1 - V.sub.I4 provided at their main inputs, where signal V.sub.si-1 is output signal of previous stage S.sub.i-1. Output signal V.sub.I5 is the S.sub.i stage output Vsi supplied to next stage S.sub.i+1. Each output signal V.sub.Ik varies between a low voltage level V.sub.SL and a high voltage V.sub.SH. The values of voltage levels V.sub.SL and V.sub.SH depend on fabrication process parameters, temperature, power-supply voltage V.sub.HH - V.sub.LL, frequency f.sub.O, and the total number of inverters I.sub.k in the oscillation loop. Voltages V.sub.SL and V.sub.SH respectively tend to exponentially approach supply voltages V.sub.LL and V.sub.HH.

Each individual inverter I.sub.k consists of a main N-channel field-effect transistor ("FET") Q1N, a main P-channel FET Q1P, a control N-channel FET Q2N, and a control P-channel FET Q2P. FETs Q1N, Q1P, Q2N, and Q2P are all enhancement-mode insulated-gate devices. Their channels are connected in series between the V.sub.LL and V.sub.HH supplies.

More particularly, the gate electrodes of complementary FETs Q1N and Q1P in each inverter I.sub.k are connected together to form the main I.sub.k input. The Q1N and Q1P drains are connected together to form the I.sub.k output. The drain and source of FET Q2N are respectively connected to the Q1N source and the V.sub.LL supply. The drain and source of FET Q2P are likewise respectively connected to the Q1P source and the V.sub.HH supply. The Q2N and Q2P gate electrodes form the control inputs that respectively receive control signals V.sub.C and V.sub.C.

Complementary FETs Q1N and Q1P in each individual inverter I.sub.k of each stage S.sub.i in FIG. 4 basically constitute a CMOS inverter. The interconnected channels of FETs Q1N and Q1P form a main current path through which a main inverter current I.sub.M flows. Main current I.sub.M is specifically illustrated in inverter 12 of FIG. 4.

The value of main current I.sub.M in each individual inverter I.sub.k depends on the conductive levels of its control FETs Q2N and Q2P. Increasing the conductive levels of FETS Q2N and Q2P by raising control voltage V.sub.C and simultaneously reducing control voltage V.sub.C enables current I.sub.M to reach a greater magnitude. This increases the rate at which output voltage V.sub.Ik changes during a rising or falling transition between levels V.sub.SL and V.sub.SH and, as a result, decreases the V.sub.Ik rise and fall times. Similarly, decreasing the conductive levels of FETs Q2N and Q2P by reducing voltage V.sub.C and simultaneously raising voltage V.sub.C reduces the magnitude that current I.sub.M can reach. The rate at which output voltage V.sub.Ik changes during rising and falling transitions decreases so as to increase the V.sub.Ik rise and fall times.

With the foregoing in mind, the phase-locked loop in the timing generator of FIG. 3 controls oscillator frequency f.sub.O in the following way. If f.sub.O is less than f.sub.R as determined by phase comparator 20, control section 12 increases control voltage V.sub.C and simultaneously decreases control voltage V.sub.C. The rise and fall times of voltages V.sub.I1 - V.sub.I5 in each inverting stage S.sub.i thereby decrease. This causes f.sub.O to increase towards f.sub.R. The opposite occurs if f.sub.O is greater than f.sub.R. The result is that f.sub.O becomes substantially equal to f.sub.R.

The oscillator power-supply voltage V.sub.HH - V.sub.LL preferably is 5 volts. As a result, oscillator frequency f.sub.O can be varied from approximately 15 MHz to approximately 35 MHz. In the preferred embodiment, reference frequency f.sub.R is approximately 28 MHz and thus falls within the f.sub.O variation range. Since effective frequency f.sub.E is approximately Nf.sub.R, f.sub.E is in the vicinity of 200 MHz, a value that would be difficult to attain with a conventional crystal oscillator without incurring significant power-dissipation problems.

Each inverting stage S.sub.i in FIG. 4 could be formed with an odd number of serially connected inverters different from five. Consider the general case in which each stage S.sub.i consists of an odd number P of individual inverters connected in series in the manner shown in FIG. 4. The total number of inverters in the oscillator loop is then NP.

The average rise time t.sub.RAVG Of the individual inverters normally differs from the average fall time t.sub.FAVG Of the inverters. This introduces a timing error into the timing generator. The timing error approximately equals (t.sub.FAVG - t.sub.RAVG)/NP, where t.sub.RAVG and t.sub.FAVG are measured from the 10% to 90% voltage switching points. In comparison to the case where each inverting stage S.sub.i consists of a single individual inverter, the use of P individual inverters in each stage S.sub.i thereby reduces the rise/fall timing error by a factor of N. In the preferred embodiment, the rise/fall timing error is 1/5 of that which would arise if each stage S.sub.i were formed with one inverter.

FIG. 5 illustrates the internal construction of timing-signal generating logic 14 in FIG. 3. Logic 14 here consists of a pulse generator 26, a bulk counter 28, a counter decode 30, an edge shifter 32, random decode logic 34, and three output timing latches T.sub.1, T.sub.2, and T.sub.3. As noted above, M is three in the preferred embodiment.

Pulse generator 26 is formed with logic gates that convert stage signals V.sub.S into seven pulse voltage signals V.sub.P1, V.sub.P2, ... V.sub.P7 (collectively "V.sub.P "). Pulse signals V.sub.P vary between a low voltage level, typically about 0.2 volt above V.sub.LL, and a high voltage level, typically about 0.2 volt below V.sub.HH. Pulse signals V.sub.P are at their high voltage levels for considerably shorter times than stage signals V.sub.S.

The signal conversion performed by pulse generator 26 can be understood with the assistance of the simplified voltage curves shown in FIG. 6. The upper seven curves in FIG. 6 illustrate the V.sub.S signals starting with V.sub.S1 at the top and ending with V.sub.S7 at the bottom. The middle seven curves present a rearranged version of the V.sub.S signals in which they are ordered so that transitions in the same direction progressively occur at later times in going from the top curve to the bottom curve. Signals V.sub.S1, V.sub.S3, V.sub.S5, V.sub.S7, V.sub.S2, V.sub.S4, and V.sub.S6 have been respectively relabeled as signals V.sub.01, V.sub.02, ... V.sub.07 (collectively "V.sub.O ") in FIG. 6.

The bottom seven curves in FIG. 6 illustrate pulse signals V.sub.P. Using the relabeled version of the V.sub.S signals, each pulse signal V.sub.Pi, except for signal V.sub.P7, the logical AND of signals V.sub.oi and V.sub.oi+1, where V.sub.oi is the inverse (or complement) of V.sub.oi. Signal V.sub.P7 is the logical AND of signals V.sub.o7 and V.sub.o1. As shown in FIG. 6, each pulse signal V.sub.Pi consists of a train of high-level pulses having a pulse width of 2.tau. and a period of T.sub.O.

The timing generator of FIGS. 3 and 5 is characterized by an overall repetition period T.sub.T greater than oscillator period T.sub.O. Bulk counter 28, counter decode 30, and edge shifter 32 form a sequencing circuit that generates a group of sequencing signals which (a) subdivide overall period T.sub.T into overlapping time segments and (b) repeat every new T.sub.T period. FIG. 7, discussed further below, illustrates simplified voltage curves for components 28-32 in the preferred embodiment for a time slightly greater than one T.sub.T.

Bulk counter 28 counts the (high-level) pulses of one of pulse signals V.sub.P and produces a group of counting signals V.sub.Q indicative of the count. When a selected maximum count K is reached, counter 28 resets to zero and starts counting again. This occurs automatically--i.e., without the need to use special reset logic for generating a reset signal--when, as in the preferred case, counter 28 is a power-of-2 counter, and selected maximum count K equals that power of 2. Overall period T.sub.T is the maximum count period--i.e., the time that counter 28 takes to reach maximum count K.

The timing generator of FIGS. 3 and 5 typically provides timing signals V.sub.T to circuitry that is switched among a group of different timing modes. For example, the circuitry controlled by the timing generator could be a dynamic random-access memory selectively operable in a one-write/four-read mode, in a one-write/one-read mode, in a refresh mode, and possibly in one or more other such modes. The duration of overall (or maximum count) period T.sub.T is preferably chosen to be sufficiently long that each of the timing modes can be started and completed during period T.sub.T. Thus, each of the timing modes can be utilized without having to take any special action to adjust the T.sub.T duration.

Counter decode 30 consists of logic gates which decode counting signals V.sub.Q to produce a first set of sequencing signals V.sub.D that establish time segments (or subdivisions) of overall period T.sub.T. The number of sequencing signals V.sub.D equals K (the maximum count). The V.sub.D signals vary between two voltage levels, typically close to V.sub.LL and V.sub.HH. Each sequencing signal V.sub.D is high for a time equal to T.sub.O during a different count of counter 28 and is low at other times. When one sequencing signal V.sub.D goes high, another goes low such that only one signal V.sub.D is high at a time. Consequently, the V.sub.D signals go in sequence from their low level to their high level and return to the low level in the same sequence. The high portions of the V.sub.D signals cover the entire period T.sub.T.

During each oscillator period T.sub.O, each pulse signal V.sub.Pi makes precisely one low-to-high transition and one high-to-low transition. Since the high portions of sequencing signals V.sub.D cover overall period T.sub.T and each sequencing signal V.sub.D is high for a time equal to oscillator period T.sub.O, any V.sub.S transition during overall period T.sub.T, except for V.sub.S transitions that correspond (identically) to V.sub.D transitions, can be uniquely identified by a selected one of the V.sub.D signals and a selected one of the V.sub.P signals.

In order to be able to uniquely identify each V.sub.S transition that corresponds to a V.sub.D transition, a second group of K sequencing signals V.sub.E are supplied from edge shifter 32. Sequencing signals V.sub.E have the same characteristics as the V.sub.D signals except that the transitions in the V.sub.E signals are respectively delayed from the transitions in the V.sub.D signals by an amount that typically lies between zero and oscillator period T.sub.O and, in any case, is not an integer multiple of T.sub.O, Consequently, the time segment during which each sequencing signal V.sub.D is at its high level is overlapped by two of sequencing signals V.sub.E, one during part of the high V.sub.D segment and the other during the remainder of the high V.sub.D segment.

As a composite group, the V.sub.D and V.sub.E signals go in sequence from a low voltage level to a high voltage level and back to the low level in the same sequence. Any V.sub.S transitions during overall period T.sub.T are uniquely selected by choosing an appropriate one of the V.sub.P signals and an appropriate one of either the V.sub.D signals or the V.sub.E signals. One of the V.sub.E signals is used if the desired V.sub.S transition corresponds to a V.sub.D transition, and vice versa.

Edge shifter 32 typically consists of a group of D-type flip-flops (not shown) whose clock inputs all receive one V.sub.P signal other than the V.sub.P signal supplied to counter 28. The data input of each flip-flop receives a different one of the V.sub.D signals. When the V.sub.P signal supplied to the clock input goes high, the already-high values of the V.sub.D signals are clocked into the flip-flops to produce the V.sub.E signals.

Maximum count K is 8 in the preferred embodiment. Accordingly, three V.sub.Q signals V.sub.Q1, V.sub.Q2, and V.sub.Q3 are sufficient to indicate when K is reached. There are eight V.sub.D signals V.sub.D1, V.sub.D2 ... V.sub.D8 and another eight V.sub.E signals V.sub.E1, V.sub.E2, ... V.sub.E8 for a total of sixteen sequencing signals. Counter 28 counts the pulses of signal V.sub.P1, while pulse signal V.sub.P3 is supplied to the clock inputs of the (resulting) eight D-type flip-flops in shifter 32. Consequently, the delay between the V.sub.D and V.sub.E signals is approximately 2T.sub.O /7 or 4.tau..

FIG. 7 illustrates simplified versions of the V.sub.Q, V.sub.D, and V.sub.E signals in the preferred embodiment. The upper three curves in FIG. 7 represent the V.sub.Q signals. V.sub.Q1 is the least significant bit. V.sub.Q3 is the most significant bit. The next eight curves are the V.sub.D signals, each of which is high for a different time segment equal to T.sub.O. The last eight curves are the V.sub.E signals, each of which is similarly high for a different time segment equal to T.sub.O.

Random decode logic 34 combines certain of the V.sub.P signals with certain of the V.sub.D and V.sub.E signals to produce three rising-edge selection signals V.sub.G1, V.sub.G2, and V.sub.G3 (collectively "V.sub.G ") and three falling-edge selection signals V.sub.H1, V.sub.H2, and V.sub.H3 (collectively "V.sub.H "). Selection signals V.sub.G and V.sub.H vary between two voltage levels, again typically close to V.sub.LL and V.sub.HH. Each selection signal V.sub.Gj has a rising transition corresponding to a desired rising edge of timing signal V.sub.Tj. Each selection signal V.sub.Hj has a rising transition corresponding to a desired falling edge of signal V.sub.Tj.

Each output timing latch T.sub.j has a set input that receives selection signal V.sub.Gj, a reset input that receives selection signal V.sub.Hj, and an output that provides timing signal V.sub.Tj. The V.sub.T signals vary between two voltage levels, again typically close to V.sub.LL and V.sub.HH. When selection signal V.sub.Gj makes a low-to-high transition, latch T.sub.j sets timing signal V.sub.Tj at the high voltage level. When selection signal V.sub.Hj later makes a low-to-high transition, latch T.sub.j resets signal V.sub.Tj to the low level. Latches T.sub.1 - T.sub.3 also have master reset inputs for receiving a master reset signal V.sub.MR to simultaneously reset all the V.sub.T signals to the low level.

FIGS. 8a and 8b illustrate examples of how portions of decode logic 34 are internally configured for providing selection signals V.sub.Gj and V.sub.Hj to typical output timing latch T.sub.j. FIGS. 9a and 9b present simplified voltage curves illustrating how timing signal V.sub.Tj is produced in these two examples starting from the V.sub.P, V.sub.D, and V.sub.E signals. In order to make it easier to graphically see the relationship among the various signals, the signal transition delays through the various gates that form latch T.sub.j and the portions of logic 34 in FIGS. 8a and 8b are not incorporated into the voltage curves of FIGS. 9a and 9b. When the gate delays are taken into consideration, the results are qualitatively the same as discussed below even though certain of the transitions occur at later times (further to the right) than shown in FIGS. 9a and 9b.

In the examples shown in both of FIGS. 8a and 8b, latch T.sub.j contains a pair of cross-connected NOR gates 36 and 38 to which signals V.sub.Gj and V.sub.Hj are supplied. Master reset signal V.sub.MR is also provided to gate 38. Gate 36 furnishes its output signal to an inverter 40 whose inverted output signal is timing signal V.sub.Tj.

In the example of FIG. 8a, each of selection signals V.sub.Gj and V.sub.Hj is generated simply by logically ANDing one of the V.sub.P signals and one of the V.sub.D or V.sub.E signals. Specifically, decode logic 34 contains AND gates 42 and 44. Gate 42 ANDs signals V.sub.D2 and V.sub.P6 to produce signal V.sub.Gj. Gate 44 ANDs signals V.sub.E3 and V.sub.P1 to produce signal

FIG. 9a depicts signals V.sub.D2, V.sub.P6, V.sub.Gj, V.sub.E3, V.sub.P1, and V.sub.Hj for the example of FIG. 8a. Because signals V.sub.Gj and V.sub.Hj are produced from the V.sub.P, V.sub.D, and V.sub.E signals simply by performing AND operations in this example, timing signal V.sub.Tj has a single high-level pulse during each overall period T.sub.T as shown in FIG. 9a. This pulse occurs at a fixed location in period T.sub.T.

The example of FIG. 8b illustrates a more complex case in which timing signal V.sub.Tj has multiple high-level pulses during each overall period T.sub.T and in which the locations of these pulses within period T.sub.T can be controllably varied from one T.sub.T period to the next T.sub.T period so as to allow a group of timing modes to be implemented. In this example, decode logic 34 contains AND gates 46, 48, 50, and 52, OR gates 54 and 56, AND gates 58, 60, 62, and 64, and OR gates 66 and 68.

Mode-select signals V.sub.W1, V.sub.W2, V.sub.W3, and V.sub.W4 are respectively supplied to gates 46-52. Each of gates 46 -52 also receives one of the V.sub.D and V.sub.E signals. If any of mode-select signals V.sub.W1 - V.sub.W4 is high at the same time that the associated one of the V.sub.D and V.sub.E signals is high, the corresponding one of gates 46-52 provides its output signal at a high value. Gate 54 provides its output signal V.sub.F1 at a high value whenever the output signal from gate 46 or 48 is high. Gate 56 similarly provides its output signal V.sub.F2 at a high value whenever the output signal from gate 50 or 52 is high.

Gate 58 ANDs signals V.sub.D2, V.sub.P6, and possibly one or more other signals (not shown) to produce a signal V.sub.F3. Gate 60 similarly AND signals V.sub.F1, V.sub.P3, and possibly one or more other signals (also not shown) to produce a signal V.sub.F4. Gate 66 provides selection signal V.sub.Gj at a high value whenever signal V.sub.F3, signal V.sub.F4, or any of the one or more other (unshown) input signals to gate 66 is high. Each of these inputs to gate 66 defines a rising edge for a different high-level pulse in timing signal V.sub.Tj provided that gate 68 defines suitable falling edges for the V.sub.Tj pulses.

Gate 62 ANDs signals V.sub.F2, V.sub.P4, and possibly one or more other signals (not shown) to produce a signal V.sub.F5. Gate 64 ANDs signals V.sub.E3, V.sub.P1, and possibly one or more other signals (also not shown) to produce a signal V.sub.F6. Gate 68 furnishes selection signal V.sub.Hj at a high value whenever signal V.sub.F5, signal V.sub.F6, or any of the one or more other (unshown) input signals to gate 68 is high. Each of these input signals to gate 68 defines a falling edge for a different high-level V.sub.Tj pulse provided that gate 66 defines suitable rising edges for the V.sub.Tj pulses.

FIG. 9b depicts signals V.sub.F1 - V.sub.F6, V.sub.P3, V.sub.P4, V.sub.Gj, and V.sub.Hj for the example of FIG. 8b. Signal V.sub.F1 is shown for the case in which mode-select signal V.sub.W1 is high during the V.sub.D5 high-level pulse while mode-select signal V.sub.W2 is low during the V.sub.D4 high-level pulse. Signal V.sub.F2 is shown for the case in which mode-select signal V.sub.W4 is high during the V.sub.D7 high-level pulse while mode-select signal V.sub.W3 is low during the V.sub.D6 high-level pulse. In addition, FIG. 9b illustrates timing signal V.sub.Tj for the situation in which only the preceding signals produce V.sub.Tj pulses. As shown in FIG. 9b, these signals cause timing signal V.sub.Tj to have two pulses during each overall period T.sub.T, The positions of the falling edge of the first V.sub.Tj pulse and the rising edge of the second V.sub.Tj pulse during each T.sub.T period are controlled by mode-select signals V.sub.W1 - V.sub.W4

The timing generator of FIG. 1 could be modified so that the phase-locked loop locks onto an integer multiple or a fraction of reference frequency f.sub.R. Specifically, a divide-by-X counter 70, where X is an integer, could be inserted between the V.sub.S1 line and control section 12 as shown in FIG. 10a. Oscillator frequency f.sub.O then becomes substantially equal to Xf.sub.R. Similarly, a divide-by-Y counter 72, where Y is also an integer, could be inserted between the V.sub.R line and control 12 as depicted in FIG. 10b. As a result, frequency f.sub.O becomes substantially equal to f.sub.R /Y.

Counters 70 and 72 could both be used in the present timing generator. In this case, frequency f.sub.O becomes substantially equal to Xf.sub.R /Y. The phase-locked loop locks onto a fractional integer multiple of reference frequency f.sub.R.

While the invention has been described with reference to particular embodiments, this description is solely for the purpose of illustration and is not to be construed as limiting the scope of the invention claimed below. Oscillator section 10 could be implemented with a non-inverting multi-stage oscillating delay chain instead of a ring oscillator. In this case, suitable initiation logic would be employed to cause the delay chain to oscillate. Also, oscillation section 10 could be implemented as a combination of inverting and non-inverting stages. The signal-transmission delays could differ from stage to stage dependent upon design objectives.

Pulse generator 26 could be deleted. Components 28 -32 could be replaced with a timing chain consisting of a number of identical timing stages arranged in a loop for producing sequencing signals analogous to the V.sub.D and V.sub.E signals. The signal polarities could be reversed so that the V.sub.T timing signals consist of low-level pulses rather than high-level pulses.

The inverter or inverters (e.g., I.sub.1 - I.sub.5) that form each inverting stage S.sub.i could be implemented partially or totally with bipolar transistors. In fact, the inverters in stages S.sub.1 - S.sub.N could be created according to, or in combination with, technologies beside semiconductor technology. Various modifications and applications may thus be made by those skilled in the art without departing from the true scope and spirit of the invention as defined in the appended claims.