PTAT Current Source

1. Field of the Invention

This invention relates to improvements in current source circuits, and more particularly to improvements in current source circuits that provide a current that is proportional to absolute temperature (PTAT). 2. Relevant Background Information

Current source circuits that provide a current that is proportional to absolute temperature have many uses. In the past, such circuits suffered numerous deficiencies. Cascode current mirrors having a high output impedance, were necessary to force equal currents in two bipolar transistors of different emitter areas, thereby increasing the minimum operating supply. Also, reliable start-up was not enjoyed under all conditions. When start-up circuitry was present, it had to be disconnected from the circuit not to affect the output current value when an equilibrium was reached. Sensing of that equilibrium was also difficult to implement in a reliable way. Other shortcomings of the classical solutions were the use of operational amplifiers, or transistor current gain dependent output.

A typical PTAT current source 10, in accordance with the prior art, is shown in FIG. 1. The prior art circuit for generating a PTAT current has two complementary current mirrors, as shown in FIG. 1. The current source 10 includes a first current mirror that is provided by NPN bipolar transistors 11 and 12 and a current mirror provided by a P-channel MOS transistors 17 and 18. The two NPN transistors 11 and 12 connected as shown to provide respective current paths from a V.sub.CC rail 15 to ground 16 through respective MOS transistors 17 and 18. The bases of the NPN transistors 11 and 12 are interconnected to each other and to the collector of the NPN transistor 12. The emitters of the NPN transistors 11 and 12 are sized such that the emitter of the NPN transistor 11 is n-times larger than the emitter of the NPN transistor 12. A resistor 20, of value R, is connected between the emitter of the NPN transistor 11 and the ground rail 16. A current source 22 that provides a current of magnitude Istart is connected between the gates of the MOS transistors 17 and 18 and the ground rail 16. The gates of the MOS transistors 17 and 18 are interconnected with each other and to the drain of the MOS transistor 17. An output MOS mirror transistor 23 is connected to provide a current path from the V.sub.CC rail to an output terminal 24 from which the output current Iout is derived. The gate of the MOS transistor 23 is connected to the gates of the MOS transistors 17 and 18, whereby the output current Iout that is delivered to terminal 24 mirrors the current that flows through the MOS transistor 18 and NPN bipolar transistor 12.

If the mirrors are ideal, the collector currents of NPN transistors 11 and 12, I.sub.c11 and I.sub.c12, are equal. Thus: ##EQU1## or, taking the logs:

Therefore, the voltage drop across the resistor 20, of value R, which has the value V.sub.be12 -V.sub.be11, equals:

With ideal mirrors, one should then obtain for the output current: ##EQU2##

Practical implementations of the circuit described, however, suffer from the non-ideal state-of-the-art current mirrors that result mainly from the Early effect on their outputs. Reducing this effect requires cascoding the mirrors, which then will not operate under low supply voltages. With respect to the lower mirror that includes the bipolar transistors 11 and 12, base current effects also need to be eliminated. The sources of error contribute to make the collector currents in the transistors 11 and 12, I.sub.c11 and I.sub.c12, different, and then the ideal PTAT relationship for Iout becomes inexact.

Another problem is the condition where the circuit 10 reaches its second equilibrium state at the moment of startup, corresponding to zero value collector currents in the transistors 11 and 12, i.e., I.sub.c11 =I.sub.c12 =0. Since this equilibrium is also stable, it is generally avoided by adding the startup current source, Istart, 22 into the input of one of the mirrors to initiate current growth in the transistors at power up. Since this current source also affects the current output value when the equilibrium is reached, it needs to be disconnected from the mirrors at that time by an adequate detection circuitry that senses when the output has become stable. Such a detection circuit needs to disconnect the current source 22 precisely after the critical threshold of ##EQU3## has been crossed, not to abort the current growth in the mirrors before that point. It therefore requires a current source similar to the PTAT current we are considering, and would also make this circuit prone to oscillation, since the current in the mirrors also tends to recess and to drop back below the threshold when the current from the current source 22 is disabled too quickly.

In general, PTAT current sources suffer from either poor accuracy or uncertain startup behavior. If startup circuitry is proposed, it often affects the value of the output current, especially for large startup current values. Other circuits require the use of operational amplifiers, which are more costly in silicon area.

In light of the above, it is, therefore, an object of the invention to provide an improved current source circuit.

It is still another object of the invention to provide a current source circuit of the type described that produces an output current that is proportional to absolute temperature.

It is still another object of the invention to provide an improved current source circuit of the type described in which the outputs are essentially independent of the beta of the transistors used, resulting in very linear high temperature capabilities.

It is yet another object of the invention to provide a current source circuit of the type described that can be implemented without operational amplifiers, thus saving total circuit area.

It is yet another object of the invention to provide an improved current source circuit of the type described that is self-starting, and in which the output current is independent of the start-up current value, and from which the start-up current source does not have to be disconnected after current build-up, while still providing a beta-independent, multiple output.

These and other objects, features and advantages of the invention will be apparent to those skilled in the art from the following detailed description of the invention, when read in conjunction with the accompanying drawings and appended claims.

In accordance with a broad aspect of the invention, a PTAT current source is presented that has a first current mirror formed of bipolar transistors and a second current mirror formed of MOS transistors connected to the first current mirror. A resistor is connected between the bipolar transistors to produce a PTAT current in the first current mirror. A pair of bipolar mirror output transistors are connected between the first and second current mirrors, and a startup current source is connected to provide regenerative current growth in the mirrors. An output current MOS transistor is connected to mirror a current in one of the bipolar mirror output transistors. The bipolar transistors of the first current mirror can be NPN transistors, and the MOS transistors of the second current mirror can be PMOS devices. If desired, at least an additional output mirror circuit can be provided to produce at least an additional output PTAT current source. Also, a base current compensation circuit may be connected to the first current mirror to provide a bias that makes the PTAT current fully independent of a startup current from the startup current source.

In accordance with another broad aspect of the invention, a PTAT current source is presented. The PTAT current source has a first current mirror having first and second current flow paths, and including first and second bipolar transistors. A resistor is connected between the bases of the first and second bipolar transistors. A second current mirror has current flow paths connected in series with the respective first and second current flow paths of the first current mirror, the second current mirror having first and second MOS transistors. Third and fourth bipolar transistors are connected respectively in the first and second current flow paths, and a startup current source is connected between a reference potential and the gates of the first and second MOS transistors. Third, fourth and fifth MOS transistors are connected between a supply voltage and the reference potential, the third MOS transistor having a gate connected to the gates of the first and second MOS transistors, the fourth MOS transistor having a gate connected to the base of the first bipolar transistor, and the fifth transistor having a gate connected between the second and fourth bipolar transistors, the fifth MOS transistor being connected between the base of the first transistor and the reference potential. An MOS transistor is connected to mirror a current in the second current flow path.

In a preferred embodiment, the bipolar transistors are NPN transistors, with the first transistor having an emitter that is about n times as large as the emitter of the second transistor. The first, second, and third MOS transistors are PMOS devices, and the fourth and fifth MOS transistors and the output current MOS transistor are NMOS devices.

If desired, at least an additional output mirror circuit comprising an output MOS transistor may be connected between an output terminal and the reference potential, the at least an additional output mirror circuit connected to mirror a current is the fifth MOS transistor. The fifth MOS transistor is about twice as large as the output current MOS transistor.

In another preferred embodiment, a base current compensation circuit is provided. The base current compensating circuit has a sixth MOS transistor and a fifth bipolar transistor connected in series between the supply voltage and the reference potential. A seventh MOS transistor is connected between the supply voltage and the base of the second bipolar transistor. An eighth MOS transistor is connected between the supply voltage and a base of the fifth bipolar transistor, the sixth MOS transistor having a gate connected to the gate of the third MOS transistor, and the seventh and eighth MOS transistors each having a gate connected to the fifth bipolar transistor, wherein the output current is fully independent of the startup current.

The invention is illustrated in the accompanying drawings, in which:

FIG. 1 is an electrical schematic diagram of a PTAT current source, in accordance with the prior art.

FIG. 2 is an electrical schematic diagram of a PTAT current source, in accordance with a preferred embodiment of the invention.

And FIG. 3 is an electrical schematic diagram of a PTAT current source, in accordance with another preferred embodiment of the invention.

A PTAT current source 30, in accordance with the invention, is shown in FIG. 2. The PTAT current source 30 has two bipolar NPN transistors 31 and 32 having emitters connected to a ground rail 33. A resistor 34, of value R, is connected between the bases of the transistors 31 and 32. The emitter of the NPN transistor 31 is sized to be n times larger than the emitter of the NPN transistor 32.

A second set of NPN bipolar transistors 35 and 36 are provided in the respective current flow paths of NPN transistors 31 and 32. The base and collector of each of the NPN transistors 35 and 36 are interconnected. A pair of P-channel MOS (PMOS) transistors 37 and 38 are additionally provided in the respective current flow paths of the NPN transistors 31 and 32, connected at their respective drain terminals to the V.sub.CC rail 40.

A PMOS transistor 42 is connected between the V.sub.CC rail 40 and an N-channel MOS (NMOS) transistor 43 to provide a current flow path between the V.sub.CC rail 40 and the base of the NPN transistor 31. The gate of the PMOS transistor 42 is connected to the respective gates of PMOS transistors 37 and 38, as well as to its own drain. Additionally, a current source 44 is connected between the gate connections of the PMOS transistors 37, 38, and 42 and the ground rail 33. The NMOS transistor 43, on the other hand, has its gate connected to the base of the NPN transistor 35.

Finally, an additional NMOS mirror transistor 45 is connected between a current output terminal 46 and the base of the NPN transistor 32. The gate of the NMOS transistor 45 is connected to the base of the NPN transistor 36. Thus, a current output, Iout, is provided at the current output terminal 46 to the circuit.

An additional mirror circuit includes an NMOS transistor 48 connected between the base of the NPN transistor 31 and the ground rail 33. The NMOS transistor 48 is twice the size of the NMOS output mirror transistor 45. Any number of additional NMOS transistors 49, 49', . . . may be provided between respective output terminals 50, 50', . . . and the ground rail 33, as shown

The gates of the NMOS transistors 48, 49, 49', . . . are interconnected to each other and to the emitter of the NPN transistor 36. Thus, each of the output mirror NMOS transistors 49, 49', . . . provides an output current, Iout, from its respective output terminals 50 50', . . .

In the operation of the circuit 30, the current source 44 provides a non-critical amount of startup current into the PMOS mirror input at the gate of the PMOS transistor 42. This current is duplicated by the PMOS transistors 37 and 38 into the NPN transistors 31 and 32, forcing current into their collectors. At the same time, the NMOS transistor 48 provides current to the sources of the NMOS transistor 43 by mirroring the current in the isolated NMOS transistor 45.

since the NMOS transistor 45 has an isolated bulk (i.e., no body effect), and the same current is flowing through the NPN transistors 32 and 36. Since NMOS transistor 48 is twice the size of the NMOS transistor 45, the output current is half the value of the current that flows through the NMOS transistor 48, and is equal to the current that flows through the NMOS transistor 45.

The current through the NMOS transistor 43 is I.sub.48 -Iout=Iout, because Iout is the current flowing through the resistor 34, which feeds into the PMOS transistor 42, therefore providing regenerative current growth in the PMOS mirror. Even for a small value of Istart that may be provided by the current source 44, a small amount of current will be created in the NMOS transistor 48, which will be fed back into PMOS transistor 42. This makes the initial current, current through PMOS transistor 42 grow until equilibrium has been reached. At that point, I.sub.c31 =I.sub.c32 (the collector currents of the NPN transistors 31 and 32). The difference between the Vbe's of the transistors 31 and 32 is converted by the resistor 34 into the desired PTAT current, and ##EQU4##

Early effects in the PMOS mirror have been eliminated since the PMOS transistors 37 and 38 have equal drain to source voltages, namely, V.sub.DD -V.sub.be31 -V.sub.GS43, if the NMOS transistors 43 and 45 have equal sizes, and if the NMOS transistor 43 is also isolated. The NMOS transistor 43 is sized such that its V.sub.GS is the same as the V.sub.GS of NMOS transistor 45, if it is not isolated. The Early effects between transistors 31 and 32 have also been eliminated for the same reason, without cascoding.

It is noted that the circuit provides a high impedance output from the drain of the NMOS transistor 45 and enables a connection for multiple outputs at the gate of the NMOS transistor 48. The value of Istart provided by the current source 44 only affects the output current through the base current of the NPN transistor 32, and is therefore divided by the current gain of the NPN transistors 31 and 32.

Another embodiment of the PTAT current source of the invention, denoted by the reference numeral 60, is shown in FIG. 3. The PTAT current source 60 includes two NPN transistors 61 and 62. The base of the NPN transistor 63 is connected to its collector. The base of the NPN transistor 63 is also connected to the gate of the NMOS transistor 78. The NPN transistor 61 is connected in a current path that includes a second NPN transistor 63 and an MOS transistor 64, between the V.sub.CC rail 65 and a ground rail 68. Likewise, the NPN transistor 62 is connected in a current path that includes a second NPN transistor 70 and a PMOS transistor 71 connected between the V.sub.CC rail 65 and the ground rail 68. The bases of the NPN transistors 61 and 62 are connected by a resistor 73, having a value R. Likewise, the gates of the PMOS transistors 64 and 71 are interconnected. The base of the NPN transistor 70 is connected to its collector and to the gate of the NMOS mirror transistor 91.

The current source 75 is connected between the gates of the PMOS transistors 64 and 71 and the ground rail 68 to provide a start current to the circuit 60. A PMOS transistor 77 and an NMOS transistor 78 are connected between the V.sub.CC rail 65 and the base of the NPN transistor 61. The gate of the PMOS transistor 77 is connected to the gates of the PMOS transistors 64 and 71, and the gate of the NMOS transistor 78 is connected to the base of the NPN transistor 63. The gate of the PMOS transistor 77 is also connected to its drain.

In the circuit embodiment 60 shown in FIG. 3, an additional circuit is provided that includes an additional NPN transistor 80 and an additional PMOS transistor 81 connected between the V.sub.CC rail 65 and the ground rail 68. An NMOS transistor 83 is connected between the V.sub.CC rail 65 and the base of the NPN transistor 80, and an additional NMOS transistor 84 is connected between the V.sub.CC rail 65 and the base of the active NPN transistor 62. The gates of the NMOS transistors 83 and 84 are connected to each other and to the collector of the NPN transistor 80. Additionally, the gate of the PMOS transistor 81 is connected to the gate of the PMOS transistor 77. Thus, the current that flows in the flow path that includes the PMOS transistor 81 and NPN transistor 80 mirrors the current that flows in the current path that includes transistors 71 and 62.

The output current, Iout, from the circuit 60 is provided at a current output terminal 90 that is connected to an NMOS mirror transistor 91 to provide a current flow path from the terminal 90 to the base of the active NPN transistor 62.

In a manner similar to that described above with respect to the circuit embodiment 30 of FIG. 2, additional current outputs can be provided from the circuit embodiment 60 shown in FIG. 3. To ensure regenerative startup, an output NMOS transistor 95 is provided that is twice the size of the NMOS mirror transistor 91. To provide additional current outputs, output NMOS mirror transistors 96, 96', . . . are provided, wherein the output currents Iout are provided at output terminals 97, 97', . . . in a current flow path between the respective terminals 97, 97', . . . and the ground rail 68.

The NMOS transistor 95 is connected to provide a current flow path between the base of the NPN transistor 61 and the ground rail 68. Additionally, the gates of the three NMOS transistors 95, 96, 96', . . . are connected to each other and to the emitter of the NPN transistor 70.

The operation of the circuit 60 shown in FIG. 3 is essentially the same as that described above with reference to the circuit 30 shown in FIG. 2, however, with base current compensation at the base of the NPN transistor 62 that makes the output current Iout fully independent of the value Istart of the current provided by the current source 75. Thus, the PTAT current provided is nearly ideal at the drain of the NMOS transistor 91, and there is essentially no base current error.

Although the invention has been described and illustrated with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the combination and arrangement of parts can be resorted to by those skilled in the art without departing from the spirit and scope of the invention, as hereinafter claimed.