Auto-Calibrated Current-Mode Digital-to-Analog Converter and Method Therefor

This invention relates generally to digital-to-analog converters, and more particularly, to an auto-calibrated current-mode digital-to-analog converter.

In present telecommunications and digital audio systems, digital-to-analog converters (DACs) having higher resolution, as well as requiring less surface area on an integrated circuit are needed. Linearity errors that reduce resolution and accuracy in an analog output signal may be caused by processing variations and component value mismatching. To achieve higher resolution, relatively large surface area, and/or special equipment, such as laser trimmers, may be required. In addition, various calibration techniques have been used to improve linearity of the analog output signal. One calibration technique used with current-mode DACs is disclosed in "A Self-Calibration Technique For Monolithic High-Resolution D/A Converters", by Groeneveld et al., IEEE Journal of Solid-State Circuits, Vol. 24, No. 6, December 1989, pp. 1517-22, and involves calibrating each current source element in the converter independently. A current-mode DAC uses current instead of voltage to represent an analog signal. The DAC is implemented using 2.sup.K +1 current source elements, where K represents the number of bits received by the DAC. During every clock cycle, 2.sup.K of the elements are switched to the output or to ground depending on the DAC input code. The one remaining current source element is calibrated relative to a reference current source. During each clock cycle, a different current source element is calibrated until eventually all of the elements have been calibrated. The calibration cycle then repeats.

A problem with the calibrated current source implementation is that it may require a very large number of current source elements to implement a high resolution DAC. For example, a 12-bit DAC requires 2.sup.12, or 4096 elements. To reduce the number of current source elements in a DAC, one common technique is to use two smaller DACs together with a divide-by-2.sup.N attenuator. N represents the number of bits in each of the two DACs. In this manner, a high resolution DAC can be implemented using two low resolution DACs. For example, a 12-bit DAC can be implemented using two 6-bit DACs. Each 6-bit DAC requires 2.sup.6, or 64 current source elements. Thus, a 12-bit DAC can be simplified from 4096 elements to 128 elements. However, the divide-by-2.sup.N attenuator should be accurate in order in order to maintain high-linearity in the DAC. A typical divide-by-2.sup.N attenuator is implemented using a current divider in a current-mode DAC, however, the accuracy of the current divider can be degraded by device mismatch. This can be a significant problem in high resolution DACs requiring high linearity.

Accordingly, there is provided, in one form, a current-mode digital-to-analog converter, a first sub-DAC, a second sub-DAC, an attenuator, a gain adjust sample and hold circuit, and a summing element. The first sub-DAC has a plurality of current sample and hold circuits. The first sub-DAC receives a reference current and a plurality of least-significant-bits of a K-bit digital signal, where K is an integer. In response, the first sub-DAC provides a first analog signal corresponding to the plurality of least-significant-bits. The second sub-DAC has a plurality of current sample and hold circuits. The second sub-DAC for receives the reference current and a plurality of most-significant-bits of the K-bit digital signal. In response, the second sub-DAC provides a second analog signal corresponding to the plurality of most-significant-bits. The attenuator is coupled to the first sub-DAC, and attenuates the first analog signal in order to provide an attenuated first analog signal. The gain adjust sample and hold circuit adjusts the attenuated first analog signal with a constant scale factor to compensate for device mismatch errors in the attenuator, and provides an adjusted attenuated first analog signal. The summing element receives the adjusted attenuated first analog signal and the second analog signal, and in response, provides an output analog signal.

In another embodiment, a method for removing device mismatch effects in the attenuator which cause nonlinearity errors in the current-mode digital-to-analog converter is provided. These and other features and advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

FIG. 1 illustrates in block diagram form, a current-mode DAC in accordance with the present invention.

FIG. 2 illustrates in schematic diagram form, the 4-phase gain adjust sample and hold circuit of FIG. 1.

FIG. 3 illustrates in schematic diagram form, a current-mode DAC in accordance with another embodiment of the present invention.

Generally, the present invention provides an auto-calibrated current-mode digital-to-analog converter. A division ratio of a current dividing attenuator of the current-mode digital-to-analog converter is calibrated in order to remove linearity errors caused by device mismatch effects in the current dividing attenuator. This is accomplished by providing two sub-DACs. One sub-DAC receives the least-significant-bits (LSB) of a K-bit digital input signal, and a second sub-DAC receives the most-significant-bits (MSB) of the K-bit digital input signal, where K is an integer. An output of the LSB sub-DAC is attenuated, and the attenuated signal is summed with an output of the MSB sub-DAC to form an analog output signal corresponding to the K-bit digital input signal. A 4-phase gain adjust sample and hold circuit is used to calibrate the current-dividing attenuator. The 4-phase gain adjust circuit samples the current from the attenuator, replicates the current, and scales it with a constant scale factor. The constant scale factor is provided by a calibrated sample and hold current element, and removes the device mismatch effects which cause linearity errors in the DAC.

The present invention can be more fully described with reference to FIG. 1-FIG. 3. FIG. 1 illustrates in block diagram form, current-mode DAC 20 in accordance with the present invention. Current-mode DAC 20 includes current source 21, sub-DAC 22, sub-DAC 36, current sample and hold circuit 34, switch 35, calibrated attenuator 48, and summing element 51. Sub-DAC 22 includes switches 23, 26, and 30, current sample and hold circuits 24, 27, and 31, switches 25, 28, and 32, and summing elements 29 and 33. Sub-DAC 36 includes switches 37, 40, and 44, current sample and hold circuits 38, 41, and 45, switches 39, 42, and 46, and summing elements 43 and 47. Calibrated attenuator 48 includes 4-phase gain adjust sample and hold circuit 49 and attenuator 50.

Current source 21 has a first terminal connected to a power supply voltage terminal labeled V.sub.DD, and a second terminal for providing a reference current labeled "I.sub.REF ". In sub-DAC 22, switches 23, 26, and 30 each have a first terminal connected to the second terminal of current source 21 for receiving reference current I.sub.REF, and a second terminal. Current sample and hold circuit 24 has a first terminal connected to the second terminal of switch 23, and a second terminal. Current sample and hold circuit 27 has a first terminal connected to the second terminal of switch 26, and a second terminal. Current sample and hold circuit 31 has a first terminal connected to the second terminal of switch 30, and a second terminal. Switch 25 has a first terminal connected to the second terminal of current sample and hold circuit 24, a second terminal connected to a first input terminal of summing element 29, and a third terminal connected to a power supply voltage terminal labeled "V.sub.SS ". Switch 28 has a first terminal connected to the second terminal of current sample and hold circuit 27, a second terminal connected to a second input terminal of summing element 29, and a third terminal connected to V.sub.SS. Switch 32 has a first terminal connected to the second terminal of current sample and hold circuit 31, a second terminal connected to a first input terminal of summing element 33, and a third terminal connected to V.sub.SS. An output terminal of summing element 29 is connected to a second input terminal of the next summing element in line, as indicated by the series of dots at the output terminal of summing element 29.

In sub-DAC 36, switches 37, 40, and 44 each have a first terminal connected to the second terminal of current source 21 for receiving reference current I.sub.REF, and a second terminal. Current sample and hold circuit 38 has a first terminal connected to the second terminal of switch 37, and a second terminal. Current sample and hold circuit 41 has a first terminal connected to the second terminal of switch 40, and a second terminal. Current sample and hold circuit 45 has a first terminal connected to the second terminal of switch 44, and a second terminal. Switch 39 has a first terminal connected to the second terminal of current sample and hold circuit 38, a second terminal connected to a first input terminal of summing element 43, and a third terminal connected to V.sub.SS. Switch 42 has a first terminal connected to the second terminal of current sample and hold circuit 41, a second terminal connected to a second input terminal of summing element 43, and a third terminal connected to V.sub.SS. Switch 46 has a first terminal connected to the second terminal of current sample and hold circuit 45, a second terminal connected to a first input terminal of summing element 47, and a third terminal connected to V.sub.SS. An output terminal of summing element 43 is connected to a second input terminal of the next summing element in line, as indicated by the series of dots at the output terminal of summing element 43.

Current sample and hold circuit 34 has a first terminal connected to the second terminal of current source 21, and a second terminal. Switch 35 has a first terminal connected to the second terminal of current sample and hold circuit 34, a second terminal connected to V.sub.SS, and a third terminal. In calibrated attenuator 48, attenuator 50 has an input terminal connected to the output terminal of summing element 33, and an output terminal. 4-phase gain adjust sample and hold circuit 49 has an input terminal connected to the output terminal of attenuator 50, and an output terminal. Summing element 51 has a first input terminal connected to the output terminal of 4-phase gain adjust sample and hold circuit 49, a second input terminal connected to the output terminal of summing element 47, and an output terminal for providing an analog output signal labeled "I.sub.OUT ".

Current-mode DAC 20 converts a digital signal comprising K-bits, to a corresponding analog signal. Sub-DAC 22 receives N-bits of the decoded digital signal and sub-DAC 36 receives M-bits of the decoded digital signal. There can be more than two sub-DACs, as illustrated in FIG. 3. In current-mode DAC 20, the N-bits represent the least-significant-bits and the M-bits represent the most-significant-bits of the K-bit digital signal. M does not have to be equal to N. Sub-DAC 22 has 2.sup.N +1 current sample and hold circuits. Sub-DAC 36 has 2.sup.M +1 current sample and hold circuits. Current sample and hold circuits 24, 27, 31, 34, 38, 41, and 45 are each conventional current-mode sample and hold circuits. Switches 25, 28, 32, 39, 42, and 46 receive digital signals from the decoder (not shown), where the digital signals from the decoder correspond to the K-bit digital input signal. Switches 25, 28, and 32 represent the switches used by sub-DAC 22. Switch 25 responds to decoded signal L.sub.0, switch 28 responds to decoded signal L.sub.1, and switch 32 responds to decoded signal L.sub.2.sup.N. Switches 39, 42, and 46 represent the switches used by sub-DAC 36. Switch 39 responds to decoded signal M.sub.0, switch 42 responds to decoded signal M.sub.1, and switch 46 responds to decoded signal M.sub.2.sup.M.

Note that there is one additional current sample and hold circuit in each of sub-DACs 22 and 36 than is required for receiving a decoded analog signal. The additional current sample and hold circuit is needed to allow one of the current sample and hold circuits to be calibrated while the other current sample and hold circuits are outputting data. Current-mode DAC 20 has two phases. During a first phase of operation, switch 23 of sub-DAC 22 is closed, coupling current sample and hold circuit 24 to current source 21 for calibrating current sample and hold circuit 24. The remaining switches 26 and 30 are open, while current sample and hold circuits 27 and 31 are outputting their respective values depending on the position of switches 28 and 32. For example, if decoded signal L.sub.1 represents a logic "zero", switch 28 will be positioned to couple current sample and hold circuit 27 to V.sub.SS. If decoded signal L.sub.1 represents a logic "one", switch 28 will be positioned to couple current sample and hold circuit 27 to the first input terminal of summing element 29. During a second phase of operation, switch 26 of sub-DAC 22 is closed, coupling current sample and hold circuit 27 to current source 21 for calibrating current sample and hold circuit 27. The remaining switches 23 and 30 are open, while current sample and hold circuits 24 and 31 are outputting their respective values depending on the position of switches 25 and 32. Sub-DAC 36 operates in the same manner, except the sub-DAC follows the operation of sub-DAC 22 by two phases of operation. Therefore, the operation of current-mode DAC 20 can be described as being "pipelined". Note that logic and decoding circuits used for controlling the switches of current-mode DAC 20 are unimportant for purposes of describing the invention, and are therefore not shown.

The outputs of each of the current sample and hold circuits of sub-DAC 22 are summed together, resulting in an analog current labeled "I.sub.SUM " being provided to attenuator 50. Attenuator 50 is a conventional current divider circuit that divides current I.sub.SUM by a scale factor of 1/2.sup.N plus a device mismatch error, if any, to provide an attenuated analog current labeled "I.sub.SIG " to 4-phase gain adjust sample and hold circuit 49. 4-phase gain adjust sample and hold circuit 49 has 4 phases, and removes the device mismatch error, and provides an adjusted attenuated analog current labeled "I.sub.ADJ " to summing element 51. Summing element 51 sums currents I.sub.ADJ and the analog current from summing element 47 to provide analog output signal I.sub.OUT corresponding to the K-bit digital input signal. Since 4-phase gain adjust sample and hold circuit 49 operates in 4 phases, it requires a clock frequency that is twice as high as that required for the 2 phases of current-mode DAC 20. The operation of 4-phase gain adjust sample and hold circuit 49 will be discussed in detail later.

FIG. 2 illustrates in schematic diagram form, 4-phase gain adjust sample and hold circuit 49 of FIG. 1. 4-phase gain adjust sample and hold circuit 49 includes P-channel transistors 60, 61, 64, 65, 75, and 76, N-channel transistors 62 and 66, current sources 63, 67, and 77, differential amplifiers 78 and 89, differential pair 72, and switching elements 68-71, 79 and 80, and 81-88. Differential pair 72 includes P-channel transistors 73 and 74.

P-channel transistor 60 has a source connected to V.sub.DD, a gate, and a drain. P-channel transistor 61 has a source connected to the drain of P-channel transistor 60, a gate for receiving bias voltage labeled "P.sub.BIAS ", and a drain. N-channel transistor 62 has a drain connected to the drain of P-channel transistor 61, a gate for receiving a bias voltage labeled "N.sub.BIAS ", and a source. Current source 63 has a first terminal connected to the source of N-channel transistor 62, and a second terminal connected to V.sub.SS. P-channel transistor 64 has a source connected to V.sub.DD, a gate connected to the gate of P-channel transistor 60, and a drain. P-channel transistor 65 has a source connected to the drain of P-channel transistor 64, a gate connected to the gate of P-channel transistor 61 for receiving bias voltage P.sub.BIAS, and a drain. N-channel transistor 66 has a drain connected to the drain of P-channel transistor 65, a gate connected to the gate of N-channel transistor 62 for receiving bias voltage N.sub.BIAS, and a source. Current source 67 has a first terminal connected to the source of N-channel transistor 66, and a second terminal connected to V.sub.SS. P-channel transistor 75 has a source connected to V.sub.DD, a gate, and a drain. P-channel transistor 73 has a source connected to the drain of P-channel transistor 75, a gate, and a drain. P-channel transistor 74 has a source connected to the source of P-channel transistor 73, a gate, and a drain. P-channel transistor 76 has a source connected to V.sub.DD, and a gate and a drain connected together. Current source 77 has a first terminal connected to the gate and drain of P-channel transistor 76, and a second terminal connected to V.sub.SS. Differential amplifier 78 has a non-inverting input terminal connected to the sources of differential pair 72, an inverting input terminal for receiving a common-mode reference voltage labeled "V.sub.CMREF ", and an output terminal connected to the gates of P-channel transistors 60 and 64.

Switch 70 has a first terminal connected to the drain of P-channel transistor 65, and a second terminal connected to the gate of P-channel transistor 73. Switch 71 has a first terminal connected to the drain of P-channel transistor 61, and a second terminal connected to the gate of P-channel transistor 74. Switch 68 has a first terminal connected to the drain of P-channel transistor 65, and a second terminal. Switch 69 has a first terminal connected to the drain of P-channel transistor 61, and a second terminal. Differential amplifier 89 has a non-inverting input terminal connected to the second terminal of switch 68, an inverting input terminal connected to the second terminal of switch 69, and an output terminal. Switch 79 has a first terminal connected to the output terminal of differential amplifier 89, and a second terminal connected to the gate of P-channel transistor 75. Switch 80 has a first terminal connected to the gate of P-channel transistor 75, and a second terminal connected to the gate and drain of P-channel transistor 76. Switch 85 has a first terminal for receiving a current labeled "I.sub.SIGN ", and a second terminal connected to the source of N-channel transistor 66. Switch 86 has a first terminal for receiving a current labeled "I.sub.SIGP ", and a second terminal connected to the source of N-channel transistor 62. Switch 87 has a first terminal for receiving a calibration current labeled "I.sub.CALN ", and a second terminal connected to the source of N-channel transistor 66. Switch 88 has a first terminal for receiving a calibration current labeled "I.sub.CALP ", and a second terminal connected to the source of N-channel transistor 62. Switch 81 has a first terminal connected to the drain of P-channel transistor 73, and a second terminal connected to the source of N-channel transistor 66. Switch 82 has a first terminal connected to the drain of P-channel transistor 73, and a second terminal for providing a current labeled "I.sub.ADJP ". Switch 83 has a first terminal connected to the drain of P-channel transistor 74, and a second terminal connected to the source of N-channel transistor 62. Switch 84 has a first terminal connected to the drain of P-channel transistor 74, and a second terminal for providing a current labeled "I.sub.ADJN ".

Each of the switches shown in FIG. 1 and FIG. 2 are conventional switching elements and comprise complementary metal-oxide semiconductor (CMOS) transmission gates or individual N-channel transistors. It should be apparent, however, that many different circuit elements can be used for the switching elements.

Calibrated attenuator 48 has 4 modes, or phases of operation: 1) sample attenuated differential current I.sub.SIGN /I.sub.SIGP for calibration; 2) calibrate the scale factor to adjust for attenuator error due to device mismatches; 3) sample attenuated differential current I.sub.SIGN /I.sub.SIGP ; and 4) hold to the output and scale to adjust for the attenuator linearity error. During phase 1, switches 85, 86, 70, 71, 80, 81, and 83 are closed, all of the other switches are open. In addition, all of the 2.sup.N +1 current sample and hold circuits, represented by current sample and hold circuits 24, 27, and 31, are summed and provided as a full scale differential current I.sub.SUM. Full scale differential current I.sub.SUM is received at the input terminal of attenuator 50 from summing element 33, and is 2.sup.N times larger than differential calibration current I.sub.CALN /I.sub.CALP from current sample and hold circuit 34. (Note: differential calibration current I.sub.CALN /I.sub.CALP will be applied during phase 2.) The current sample and hold circuits that generate differential calibration current I.sub.CALN /I.sub.CALP and differential current I.sub.SUM are independently calibrated to ensure accuracy. Differential current I.sub.SUM is attenuated by attenuator 50 to produce attenuated differential current I.sub.SIGN /I.sub.SIGP. Attenuator 50 comprises a conventional current dividing circuit. A differential current through N-channel transistors 62 and 66 is equal to the difference between attenuated differential current I.sub.SIGN /I.sub.SIGP and the differential drain current of P-channel transistors 73 and 74. The differential current through N-channel transistors 62 and 66 causes a large differential voltage at the drains of N-channel transistors 62 and 66, which in turn causes a change in the current through P-channel transistors 73 and 74. The current in P-channel transistors 73 and 74 adjusts until it is substantially equal to attenuated differential current I.sub.SIGN /I.sub.SIGP.

During phase 2, switches 68, 69, 79, 81, 83, 87, and 88 are closed, all other switches are open. The gate voltage of P-channel transistor 75 is adjusted by differential amplifier 89 to cause a change in the tail current and transconductance of P-channel transistors 73 and 74. The adjustment of the gate voltage of transistor 75 continues until the differential current in P-channel transistors 73 and 74 equals differential calibration current I.sub.CALN /I.sub.CALP. Since the current in P-channel transistors 73 and 74 was set by differential current I.sub.SUM during phase 1, which was 2.sup.N times larger than differential calibration current I.sub.CALN /I.sub.CALP, the calibrated current in P-channel transistors 73 and 74 should equal differential calibration current I.sub.CALN /I.sub.CALP.

During phase 3, switches 85, 86, 70, 71, 80, 81, and 83 are again closed, with all other switches open. 4-phase gain adjust sample and hold circuit 49 operates as in phase 1. The current in P-channel transistors 73 and 74 is adjusted until it equals attenuated differential current I.sub.SIGN /I.sub.SIGP.

During phase 4, switches 85, 86, 70, 71, 81, 83, and 80 are open and switches 82, 84, and 79 are closed.. Attenuated differential current I.sub.SIGN /I.sub.SIGP is coupled to the output terminals and scaled to adjust for attenuator mismatch error. The current in P-channel transistors 73 and 74 flows to the output terminals and is adjusted by a change in the tail current flowing from P-channel transistor 75 in differential pair 72. The change in tail current causes an adjustment in the transconductance of P-channel transistors 73 and 74 which in turn either amplifies or attenuates current attenuated differential current I.sub.SIGN /I.sub.SIGP to provide adjusted attenuated differential current I.sub.ADJP /I.sub.ADJN. This gain, or attenuation factor is adjusted during phase 2 to account for gain errors in attenuator 50. Thus, 4-phase gain adjust sample and hold circuit 49 effectively adjusts for gain errors in attenuator 50 by changing the transconductance of differential pair 72 in the time between phase 3 and phase 4. The result is that the attenuator scale factor, or mismatch error in attenuator 50, is multiplied by the gain adjust scale factor (from 4 -phase gain adjust sample and hold circuit 49), which provides an almost exact division by 2.sup.N.

Current sources 63 and 67 are voltage controlled current sources that are controlled by the voltage at the drains of N-channel transistors 62 and 66, respectively, during phase 4. This prevents the drains of N-channel transistors 62 and 66 from floating during phase 4 when switches 68, 69, 70, and 71 are open. Also, controlling current sources 63 and 67 with the drain voltage of N-channel transistors 62 and 66 removes offset errors in 4 -phase gain adjust sample and hold circuit 49 that are caused by device mismatches. In addition, the adjusted current values of current sources 63 and 67 that are established in phase 4 are maintained in phases 1-3.

FIG. 3 illustrates in schematic diagram form, three-stage current-mode DAC 90 in accordance with another embodiment of the present invention. Three-stage current-mode DAC 90 converts a K-bit digital signal to an analog signal, and includes J-bit sub-DAC 91, M-bit sub-DAC 92, N-bit sub-DAC 93, calibrated attenuators 94 and 96, and summing elements 95 and 97. Calibrated attenuators 94 and 96 are the same as calibrated attenuator 48 of FIG. 1.

Each sub-DAC has the same structure as sub-DACs 22 and 36 of FIG. 1. J-bit sub-DAC 91 has 2.sup.J +1 current sample and hold circuits, M-bit sub-DAC 92 has 2.sup.M +1 current sample and hold circuits, and N-bit sub-DAC 93 has 2.sup.N +1 current sample and hold circuits, where J+M+N equals K.

Three-stage current-mode DAC 90 illustrates that more than one calibrated attenuator can be used in a multi-stage DAC with multiple sub-DACs. The scale factor of calibrated attenuator 94 is 1/2.sup.N, and the scale factor of calibrated attenuator 96 is 1/2.sup.M. The accuracy of calibrated attenuators 94 and 96 becomes more important when used with more than two sub-DACs. For example, attenuator 94 needs a gain accuracy of only N bits since it is processing the N least-significant-bits of the DAC. However, attenuator 96 should have a gain accuracy of M+N bits. The advantage of using a large number of stages is that it reduces the total number of current elements in the DAC.

The total number of current elements for a K-bit DAC converter is equal to (K/N)(2.sup.N +1)-1, where N is the number of bits in each sub-DAC. The following table relates the total number of current elements required for a K-bit DAC and a 12-bit DAC.

From the table, it can be seen that a DAC having the smallest number of elements can be obtained by using sub-DACs having 2-bits each. High resolution digital-to-analog converters having multiple sub-DACs can be constructed using the calibrated attenuator of the present invention, without having the linearity errors of conventional attenuators that are affected by device mismatch.

While the invention has been described in the context of a preferred embodiment, it will be apparent to those skilled in the art that the present invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above. For example, it should be apparent to one skilled in the art that a single-ended DAC could be constructed for receiving a single-ended input signal and providing a single-ended output signal. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.