US 5,440,524 AGrant
Method and Apparatus for Simuilataneous Long Writes of Multiple Cells of a Row in a Static Ram
Issue Date:1995-08-08
•1 Claims
•4 Drawing Sheets
Abstract
A multiple column select circuit enables simultaneous selection of multiple columns of a static RAM to allow a "long write" test for leakage defects whereas a fewer number of columns are selected during normal operation of the static RAM. In one embodiment, a multiple column select circuit includes an inverter, the output lead of which is coupled to the pull-up circuits of each respective column of the static RAM. When a multiple column select input signal is asserted, a supply voltage supplied to each of the pull-up circuits by the output lead of the inverter switches from V.sub.DD to ground potential thereby simultaneously selecting multiple columns of the static RAM. In another embodiment, a multiple column select circuit drives each individual column select line of the memory. When a multiple column select input signal is asserted, each individual column select line is asserted, thereby selecting all columns. When the multiple column select input signal is not asserted, a column addressing circuit controls the voltages on the column select lines through the multiple column select circuit to select only one column.
Metadata
Assignee
- Integrated Device Technology, Inc.
Inventor
- William L. Devanney
Application Information
Application Number:US 1908065
Filing Date:1994-02-01
Priority Date:1994-02-01
Art Unit:251
Classifications
IPC:
G11C 800
Field of Search:
365230.06;201;203;189.11;189.09
Patent Drawings (4 sheets)
Description
Field of the Invention
This invention relates to semiconductor memory devices. More particularly, this invention relates to a static random access memory (SRAM) with simultaneous multiple column select circuitry and an associated method.
Background Information
Random access memories (RAMs) are now widely used in computers and other electronic devices. Today, the digital circuit designer has at his or her disposal a wide variety of RAMs of different types and sizes. Generally, the factors used to select a particular RAM for a particular application include price, power consumption, access speed, integrated circuit (IC) chip size and reliability.
For applications requiring a fairly large amount of memory at a minimal cost, dynamic complementary metal oxide semiconductor (CMOS) memory is typically a good compromise. Dynamic memory cells occupy minimal bit cell area, thereby minimizing IC cost, but require circuitry for continuously providing "refresh" cycles necessary to maintain the integrity of the memory content.
On the other hand, if access speed and data integrity are of primary concern, CMOS static RAM (SRAM) memory is a better choice. A static bit cell typically occupies a larger area than a dynamic bit cell on an IC, resulting in higher cost, but is generally easier to use because a static bit cell can maintain its memory content without being refreshed. Other advantages of SRAM memory include faster data access times and reduced power consumption in low frequency applications.
FIG. 1a shows the r.sup.th bit cell of the c.sup.th column of a prior art static memory IC having a total of C columns and R rows. FIG. 1b shows an example of a conventional row address decoder for an embodiment of the memory shown in FIG. 1a having sixteen rows of memory. Conventionally, "columns" and "rows" refer to the physical layout of the memory cell array. However, the memory is accessed logically as 8-bit, 16-bit or 32-bit words. For example, a 2K.times.8 memory has 16,384 memory cells typically arranged in an array of 128 columns and 128 rows, and is typically accessed eight bits at a time, so that a user has 2,048 words, each word being eight bits wide.
Referring again to FIG. 1a, the r.sup.th memory bit cell 100 of the c.sup.th column is shown in greater detail and has a bit output node 120 and a complementary bit output node 130. N-channel field effect transistors (FETs) Q3 and Q4 are coupled to their respective load resistors R1 and R2 which act as internal cell pull-up loads. The gate of FET Q3 is coupled to the drain of the opposing FET Q4 and vice versa. Together, the cross-coupled transistors Q3 and Q4 and load resistors R1 and R2 are responsible for maintaining the logic state of bit cell 100 and thereby retaining bit cell data against any leakage current.
In this configuration, one of FETs Q3 and Q4 is normally ON while the opposing FET is OFF. Bit cell 100 has two stable states, HIGH and LOW. Either state can be overridden by applying an appropriate sequence of external signals in a write cycle, described in greater detail below. These two stable states provide bit cell 100 with the desired characteristic of a static memory cell.
In the above described static RAM configuration, data is written into and read from each memory cell via a differential pair of bit lines BIT and BIT. In the storage mode, the voltages on a row select lead and node 110 and a column select lead and node 210 are normally LOW, thereby keeping bit transmission gates Q1, Q2 and column transmission gates 201, 202 OFF.
Pull-up N-channel FETs 301 and 302 of column pull-up circuit 300 are always ON, thereby keeping bit lines BIT and BIT normally HIGH when the bit lines are not coupled to a bit cell in column c. Pull-up FETs 301 and 302 are needed due to the low static pull-up current supplied by load resistors R1 and R2. The static pull-up currents supplied by load resistors R1 and R2 are in the range of 5 pA to 500 nA in a typical SRAM cell. If pull-up FETs 301 and 302 were not provided, a leakage current flowing through bit cell 100 due to a charge associated with the stray capacitance of one of bit lines BIT and BIT near ground potential may unintentionally flip the state of bit cell 100.
Prior to a read operation, due to the low pull-up current in static bit cell 100, column pull-up FETs 301 and 302 of column pull-up circuit 300 are needed to pull the voltages of both bit lines BIT and BIT towards V.sub.DD to prevent an excessive differential voltage from developing between bit lines BIT and BIT. Pull-up circuit 300 can be implemented using other schemes including but not limited to resistors, N-channel transistors, or P-channel transistors, while serving the function of providing a limited conductance connection between bit lines BIT, BIT and the V.sub.DD supply.
Hence, pull-up circuit 300 comprising FETs 301 and 302 functions in a manner similar to pull-up load resistors (i.e. FETS 301 and 302 are always on). In other words, when bit output node 120 and complementary bit output node 130 are coupled to bit lines BIT and BIT, respectively, one of the bit lines BIT or BIT will contend with one of FETS 301 and 302. During a read cycle, because FETS 301 and 302 form high impedance connections to V.sub.DD, one of bit output nodes 120 or 130 of bit cell 100 will pull (force) the source of either FET 301 or 302 to a low level. Similarly, when bit cell 100 is being written, the high writing current produced by one of data lines DATA and DATA will pull the source of either FET 301 or 302 to a low voltage level.
A read cycle of bit cell 100 is as follows. As described above, when there are no read or write operations in progress, bit lines BIT and BIT are normally HIGH due to pull-up circuit 300. If bit cell 100 is in the HIGH state (i.e., bit output node 120 is HIGH and complementary bit output node 130 is LOW) pulling row select lead and node 110 HIGH turns both bit transmission gates Q1 and Q2 ON, thereby coupling bit output node 120 and complementary bit output node 130 to bit lines BIT and BIT, respectively. In addition, increasing the voltage on column select lead and node 210 serves to turn both column transmission gates 201 and 202 ON, thereby coupling bit lines BIT and BIT to data bus lines DATA and DATA, respectively. As a result, the HIGH voltage level on bit output node 120, together with the complementary LOW level on complementary bit output node 130, are now transmitted onto data bus lines DATA and DATA, respectively.
A write HIGH cycle of bit cell 100 begins with asserting the desired logic level and its complement onto data bus lines DATA and DATA, respectively. Placing a logic level HIGH onto column select lead and node 210 turns both column transmission gates 201 and 202 ON. If DATA is HIGH and DATA is LOW, this has the effect of pulling bit line BIT LOW while leaving bit line BIT HIGH. Similarly, driving row select lead and node 110 HIGH turns both bit transmission gates Q1 and Q2 ON. When bit transmission gate Q1 turns ON, bit output node 120 of bit cell 100 (which is coupled to the gate of FET Q4) is pulled HIGH, thereby turning FET Q4 ON. Similarly, when bit transmission gate Q2 turns ON, complementary bit output node 130 of bit cell 100 (which is coupled to the gate of FET Q3) is pulled LOW, thereby turning FET Q3 OFF. Thus bit output node 120 is now set to a HIGH level and complementary bit output node 130 is set to a LOW level at the end of this write cycle when the voltage on the row select line 110 is returned to its normal LOW logic level.
A write LOW cycle of bit cell 1DO is very similar because the static RAM memory cell circuitry is substantially symmetrical. Bit output node 120 is set to a LOW logic level and complementary bit output node 130 is a HIGH logic level at the end of the write LOW cycle. This is done by placing LOW and HIGH logic level signals on DATA and DATA, respectively, at the start of the write LOW cycle. During write operations, due to higher current supplied via data bus lines DATA and DATA, bit line voltages typically go lower in voltage than they do in read operations or when the columns are not being addressed (i.e., in a "deselected" state).
If a manufacturing defect exists such that there is a leakage in bit transmission gates Q1 or Q2 from an internal node of bit cell 100 to bit lines BIT or BIT, then an extended write operation (write of a long duration) on the c.sup.th column to any one of the other rows (rows 1 to (r-1) and (r+1) to R) can cause the data of bit cell 100 to be corrupted or lost. This is because an extended write to any bit cell other than cell 100 of the c.sup.th column provides a current leakage path for an adequate length of time into cell 100 via bit lines BIT and BIT to affect the contents of cell 100. Note that this particular leakage problem does not occur when cell 100 is being read and when cell 100 is in the deselected state, because bit cell 100 is designed to be stable under these conditions.
Further, if one of transistors Q1 and Q2 is not just leaky but rather is completely shorted, then a write and subsequent read operation is sufficient to identify the complete short defect by detecting the inability of cell 100 to latch a logic state and then maintain that logic state during the read operation. Hence no special write is required to test for the complete short defect.
Referring again to FIG. 1a, to test for the above described leakage defect, a write operation is performed separately for each bit line for an adequately long duration, generally on the order of seconds, to guarantee that no such leakage defect exists. This is because leakage currents across FETs Q1 and Q2 can only be detected by "long write" operations in which bit lines BIT and BIT are written to for an extended period (i.e., long enough to allow a defective bit cell in the column to be discharged via leakage).
For example, if bit cell 100 has a capacitance C, and each of pull-up load resistors R1 and R2 has a resistance R, then the approximate duration of such a test is RC, assuming that, in the worst case, the defect indicates a leakage of the same magnitude as the pull-up load resistor current. In the case of a 256K SRAM organized as 256 rows.times.1024 columns, where columns of bit cells are accessed in groups of eight (i.e. eight columns for each word), 128 separate long write sequences are required to complete the test for the leakage defect failure mode. Each group of columns requires four test combinations (Store 0s, Long Write 1s; Store 1s, Long Write 0s; Store 0s, Long Write 0s; Store 1s, Long Write 1s) for a typical total test time of:
wherein: R=10.sup.11 .OMEGA.
Accordingly, a bottleneck to an efficient and fast throughput test for this leakage problem is an inability of a conventional SRAM to read or write more columns at a time. The total time required to verify that a typical SRAM is free from this type of defect is therefore significant. This problem will become more severe with increases in memory size in the future. A need therefore exists for a SRAM having addressing logic capable of performing "long write" operations simultaneously to more columns of memory bit cells than would be written to in a "write" operation during normal operation.
Summary
A multiple column select circuit enables simultaneous selection of multiple columns of a static RAM to allow a rapid test for leakage defects whereas a fewer number of columns are selected during normal operation of the static RAM.
In accordance with one embodiment of the present invention, the multiple column select circuit comprises an inverter, the output lead of which is coupled to the pull-up circuits of each respective column of a static RAM. When a multiple column select input signal is asserted, a supply voltage supplied to each of the pull-up circuits by the output lead of the inverter switches from V.sub.DD to ground potential, thereby enabling the simultaneous selection of multiple columns of the static RAM.
In accordance with another embodiment of the present invention, the multiple column select circuit drives each individual column select line of the memory. When a multiple column select input signal is asserted, each individual column select line is asserted, thereby enabling selection of all the columns. When the multiple column select input signal is not asserted, a column addressing circuit controls the voltages on the column select lines through the multiple column select circuit.
Hence, with the addition of multiple column select circuitry to a SRAM, a time efficient defect test is performed by simultaneously selecting multiple columns of memory cells. A fewer number of columns of memory cells are later selected during accessing of the memory in normal operation.
Brief Description of the Drawings
FIG. 1a (Prior Art) is a circuit diagram of an array (C columns.times.R rows) of static memory cells, showing the r.sup.th bit cell of the c.sup.th column in greater detail.
FIG. 1b (Prior Art) is a circuit diagram of a row address decoder circuit for a 16-row memory.
FIG. 2 is a diagram of one column of a static random access memory having the pull-up circuitry of every column coupled to a multiple column select circuit.
FIG. 3 is a diagram of one column of a random access memory, the column select input terminals of the column being coupled to the output lead of a 2-input OR gate of a multiple column select circuit, one input of the OR gate being coupled to a multiple column select lead.
Detailed Description of Preferred Embodiments
FIG. 2 shows a static random access memory bit cell 100 of a column of a matrix of memory cells, a row select lead and node 110 extending horizontally from a row addressing circuit (not shown, see FIG. 1a), a column select lead and node 210 extending vertically from a column select addressing circuit (not shown, see FIG. 1a), a column select circuit 200 comprising a column pull-up circuit 300' two bit lines BIT and BIT, and two transistors 201 and 202; and a multiple column select circuit 320. The multiple column select circuit 320 is coupled to the column pull-up circuit 300' of each of the columns of the memory matrix via a multiple column select lead 370'. In FIG. 2, multiple column lead 370' is shown extending to the left from the output terminal of inverter 370. A multiple column select node 360 is coupled to the input terminal of inverter 370 of the multiple column select circuit 320. Nodes 303 and 304 of N-channel pull-up FETs 301' and 302' of pull-up circuit 300' are therefore not directly connected to the V.sub.DD high voltage supply as in FIG. 1a. Under normal read and write operations, nodes 303 and 304 are kept HIGH by asserting a LOW logic level signal onto multiple column select node 360. In some embodiments, bit cell 100 of FIG. 2 has the same structure as bit cell 100 of FIG. 1a. The reads and writes of the c.sup.th column of bit cells are accomplished by asserting appropriate control signals on column select lead and node 210 and row select lead and node 110 as described in detail below.
A write HIGH cycle of bit cell 100 begins with asserting the desired logic level and its complement on data bus lines DATA and DATA, respectively. If DATA is HIGH and DATA is LOW, increasing the voltage on column select node 210 to a HIGH logic level turns both N-channel column transmission gates 201 and 202 ON. This pulls the voltage on bit line BIT LOW while leaving the voltage on bit line BIT HIGH. Similarly, increasing the voltage on row select node 110 to a HIGH logic level turns both bit transmission gates ON, thereby setting output node 120 (see bit cell 100 of FIG. 1a) of bit cell 100 to a HIGH level and complementary bit output node 130 to a LOW level at the end of this write cycle when row select lead and node 110 is returned to its normal LOW state. A write LOW cycle of bit cell 100 is very similar because the static RAM memory cell circuitry is substantially symmetrical.
A read cycle of bit cell 100 occurs as follows. When there are no read or write operations in progress, bit lines BIT and BIT are normally HIGH due to column pull-up circuit 300'. When bit cell 100 is in the HIGH state (i.e., bit output node 120 is HIGH and complementary bit output node 130 is LOW), forcing row select lead and node 110 HIGH turns both bit transmission gates Q1 and Q2 (see bit cell 100 of FIG. 1a) ON, thereby coupling bit output node 120 and complementary bit output node 130 to bit lines BIT and BIT, respectively. In addition, raising the voltage on column select lead and node 210 turns both column transmission gates 201 and 202 ON, thereby coupling bit lines BIT and BIT to data bus lines DATA and DATA, respectively. As a result, the HIGH voltage logic level on bit output node 120, together with the complementary LOW voltage logic level on complementary bit output node 130, are now transmitted onto data bus lines DATA and DATA, respectively. Bit line BIT provides sufficient current to win the logic level contention with high impedance pull-up FET 302'.
Conversely, when bit cell 100 is in the LOW state, increasing the voltage on row select lead and node 110 to a HIGH logic level turns both bit transmission gates Q1 and Q2 ON. Increasing the voltage on column select lead and node 210 to a HIGH logic level turns both column transmission gates 201 and 202 ON. The resulting LOW level on bit output node 120 and the corresponding HIGH on complementary bit output node 130 are transmitted onto data bus lines DATA and DATA, respectively.
To activate a special "long write" test mode, a LOW logic level is supplied to all the pull-up circuits (e.g. pull-up circuit 300' of the c.sup.th column, and of every column in the entire chip) by asserting a HIGH logic level on multiple column select node 360, thereby pulling nodes 303 and 304 to a LOW logic level or to a voltage intended to simulate the voltage applied on the bit lines during normal write operations. This allows all bit lines to be forced to a LOW logic level without requiring individual write operations to be performed on every bit line. Row select lead and node 110 remains LOW (i.e., unasserted) in this test mode.
Using multiple column select circuit 320, it is now possible to ground the bit line pairs of all the columns of the SRAM including bit lines BIT and BIT simultaneously, thereby reducing the total test time t to 2RC (for example, 0.06 seconds using the values of R and C mentioned above). In this embodiment, multiple column select circuit 320 could be as simple as an inverter 370. A test mode signal is supplied to the input terminal of inverter 370. This test mode signal goes HIGH during "long write" testing, but remains LOW during normal circuit operations, thereby providing a HIGH logic level voltage (simulating a V.sub.DD high power supply) to all the bitline pull-up circuits at nodes corresponding to nodes 303 and 304 under normal operating conditions. Other multiple column select circuits are also possible, the basic concept being to isolate multiple bit line pairs (such as nodes 303 and 304 of bit lines BIT and BIT) from the V.sub.DD supply so that parallel testing of multiple bit line pairs is possible.
FIG. 3 shows a column of a SRAM cells in accordance with another embodiment of the present invention. An input terminal of a column select circuit 200 of the column of SRAM cells is coupled to a corresponding output terminal of a multiple column select circuit 220. The multiple column select circuit 220 comprises a plurality of two-input OR gates. One input lead of each of the 0R gates is coupled to a multiple column select node 260 while the other input lead of each OR gate is coupled to a corresponding column select line (i.e., individual column select node 210'). The output lead of each of the 0R gates of the multiple column select circuit 220 is a corresponding one of the output terminals of the multiple column select circuit 220. OR gate 270 in FIG. 3 is one of the OR gates of multiple column select circuit 220. Bit cell 100 is the same as the bit cell structure of FIG. 1a. In a normal read or write operation, column select node 210' is used to select or deselect the column illustrated. This is accomplished by asserting a logic level HIGH onto column select node 210' as well as onto the appropriate row select line (such as row select lead and node 110) as described in greater detail below.
A write HIGH cycle of bit cell 100 begins with asserting the desired logic level and its complement on data bus lines DATA and DATA, respectively, and then raising the voltage on column select node 210' HIGH to turn both column transmission gates 201' and 202' ON. When bus line DATA is HIGH and bus line DATA is LOW, bit line BIT is pulled LOW while leaving bit line BIT HIGH. Although bitlines BIT and BIT are both normally HIGH when bit cell 100 is not selected, as described above, the higher write current provided by data line DATA and DATA wins the voltage contention. Next, forcing the voltage on row select node 110 HIGH turns both bit transmission gates (see FIG. 1a) of bit cell 100 ON, thereby setting the bit output node (see FIG. 1a) of bit cell 100 to a HIGH level and the complementary bit output node (see FIG. 1a) to a LOW level at the end of this write cycle when row select node 110 is returned to its normal LOW logic level. A write LOW cycle of bit cell 100 is very similar because the static RAM memory cell circuitry is symmetrical.
A read cycle of the bit cell 100 is as follows. As described above, when there are no read or write operations in progress, bit lines BIT and e,ovs BIT.times. are normally HIGH due to high impedance pull-up circuit 300. When bit cell 100 is in the HIGH state (i.e., the bit output node is HIGH and the complementary bit output node is LOW), forcing the voltage on row select node 110 HIGH turns both bit transmission gates Q1 and Q2 ON (see bit cell 100 of FIG. 1a), thereby coupling the bit output node and the complementary bit output node to bit lines BIT and BIT, respectively. In addition, raising the voltage on column select node 210' turns both column transmission gates 201' and 202' ON, thereby coupling bit lines BIT and BIT to data bus lines DATA and DATA, respectively. As a result, the HIGH logic level on the bit output node (not shown), together with the complementary LOW level on the complementary bit output node (not shown), are now transmitted onto data bus lines DATA and DATA, respectively. Again as discussed above, bit line BIT wins the logic level contention with high impedance pull-up FET 302.
When the "long write" test is needed, a HIGH logic level is asserted onto multiple column select lead and node 260 to select all columns simultaneously. Row select lead and node 110 remains LOW. Raising the voltage on multiple column select node 260 causes the output lead of OR gate 270 to go HIGH, thereby turning column transmission gates 201' and 202' ON. Asserting a HIGH logic level onto multiple column select lead and node 260 therefore results in the simultaneous selection of all the columns of the SRAM.
In accordance with another embodiment, columns of an SRAM are divided into groups of columns. Each group of columns is coupled to a different "group" multiple column select node which makes it possible to perform a "long write" of multiple columns of the SRAM one group at a time, simply by duplicating the multiple column select circuitry of the first or second embodiment for each group of columns. Other embodiments are also possible. For example, semiconductor elements of opposite polarities to those described above may be used to accomplish the same result (i.e., P-channel FETs may be used instead of N-channel FETs and/or pull-down transistors may be used instead of pull-up transistors).
While this invention has been described with reference to particular embodiments, this description is not intended to be limiting, and other embodiments within the scope of the claimed invention are possible. Bit cell architectures other than the specific bit cell architecture illustrated may be employed in connection with the present invention. The present invention is not limited to the specific column select circuit and the specific pull-up circuit illustrated. Digital logic other than an inverter can be used to control the voltage on nodes of pull-up circuits and digital logic other than 0R gates can be used to drive the column select input terminals of an SRAM. Thus, while this invention has been described in connection with an inverter or an OR gate selecting multiple columns of SRAM, it is be understood that changes, modifications, adaptations and combinations of various features of the above described specific embodiments can be practiced without departing from the scope of the invention as set forth in the appended claims.
Claims
I claim:
1. An integrated circuit, comprising: a plurality of static random access memory cells organized in a matrix having a plurality of rows and a plurality of columns; a row addressing circuit having a plurality of row select leads, each of said row select leads being coupled to a corresponding one of said rows of memory cells; a column addressing circuit having a plurality of column select output terminals; a plurality of column select circuits, each of said column select circuits having a column select input terminal, each of said column select circuits further comprising a bit line coupled to a corresponding column of said memory cells; and a multiple column select circuit coupled to said plurality of said column select circuits, wherein said multiple column select circuit comprises a multiple column select lead, said multiple column select lead being coupled to each of said plurality of column select circuits wherein said multiple column select circuit further comprises a digital logic element having an output terminal, said output terminal of said digital logic element being coupled to said multiple column select lead, said digital logic element being selected from the group consisting of: an inverter, a buffer, a NAND gate, an AND gate, a NOR gate, an OR gate, an exclusive OR gate, an exclusive NOR gate, a latch, and a flip-flop, wherein each of said column select circuits comprises a column pull-up circuits being coupled to said multiple column select lead, said second terminal of each of said column pull-up circuits being coupled to a corresponding one of said bit lines, wherein each of said column select circuits comprises two bit lines, and wherein each column pull-up circuit comprises a first field effect transistor and a second field effect transistor, a gate of said first field effect transistor being coupled to a gate of aid second field effect transistor, a first terminal of said first field effect transistor being coupled to said multiple column select lead, a first terminal of said second field effect transistor being coupled to said multiple column select lead, a second terminal of said first field effect transistor being coupled to one of two bit lines of a column select circuit, a second terminal of said second field effect transistor being coupled to another of said two bit lines of said column select circuit.