Disk Drive Controller

The purpose of this invention is to enable disk drive data written to an output register to be examined after the "write" has occurred. Additionally, the invention allows data from a previous "read" of an input register to be examined. Input and output registers are used in electronic controllers for modifying or monitoring the behavior of a controlled machine. Frequently the next action of the controller depends upon the current state of one or more of its output registers.

Two existing methods are in general use:

(1) Additional logic is added to an output register to allow the output of the register to be read back.

(2) The controller stores an image of the data written to the output register. The image is stored in RAM using additional controller instructions after the data has been written to the output register.

Old method (1) adds complexity to the machine because each output register must have an input register added to it so that the output can be read. This additional complexity reduces the machine reliability. Old method (2) adds complexity to the machine because the control program must include additional instructions to store the image of the data. This reduces the performance of the machine because the time taken to store the image of the data is additional overhead. The design of the control program is an error-prone process; typically an output register may be altered in several places in the control program; the extra instructions required to store the image of the data may be omitted from one or more of these places. The image of the data stored in RAM will then not be the same as the output register contents.

This invention does not require the additional input registers of old method (1) because it uses a RAM to store images of the data written to the output registers [note: most controllers already include a suitable Ram Device]. The invention does not require the additional instructions in the control program of method (2) because the controller logic is designed so that a write-operation to an output register results in a simultaneous write-operation to a corresponding RAM location.

These and other features and advantages of the present invention will be appreciated by workers as they become better understood by reference to the following detailed description of the present preferred embodiments which should be considered in conjunction with the accompanying drawings, wherein like reference symbols denote like elements:

FIG. 1 is a schematic idealized block diagram of a disk drive controller of a "Control" type this being modified in the like diagram of FIG. 2 according to a feature hereof;

FIGS. 2-5 are more detailed circuit diagrams of a modified controller embodiment of the type in FIG. 2; and

FIG. 6 is a schematic block diagram of an overall disk drive logic block apt for using the embodiment (cf. DMPU).

General description, background:

FIG. 2 schematically illustrates a disk drive controller embodiment constructed according to principles of this invention (implemented in the circuits of FIGS. 3-5) This, and other means discussed herein, will generally be understood as constructed and operating as presently known in the art, except where otherwise specified. And, except as otherwise specified, all materials, methods and devices and apparatus herein will be understood as implemented by known expedients according to present good practice.

A block diagram of a control type of intelligent controller is shown in FIG. 1.

The control program for the controller is stored in EPROM. A RAM is used to store temporary values generated by the execution of the control program. The output registers are connected to the machine to be controlled and are used to affect changes in the machine. The input registers are connected to the machine to be controlled and are used to monitor various signals produced by the machine. The microprocessor executes the control program stored in the EPROM. The address bus is generated by the microprocessor and is used to specify a unique location in the EPROM, RAM or a particular input or output register. The data bus is used to transfer data between the addressed device and the microprocessor. The read/write signal specifies the direction of the data transfer, to or from the microprocessor. The address decoder logic generates "select" or "enable" signals for the EPROM, RAM, input and output registers to enable the transfer of data. There are a number of different methods in use for implementing the address decoding function; however, the objective of these methods is to ensure that only one device is transferring data to the data bus, or receiving data from the data bus, at a time. In particular, when the microprocessor is writing data to an output register or reading data from an input register the RAM is not "selected".

The invention differs from the system described in that the address decoding function is designed so that when the microprocessor writes to an output register, the data transferred is simultaneously written to a unique location in the RAM. Also, when the microprocessor reads data from an input register the data is simultaneously written to a unique location in the RAM. This requires that the read/write function of the RAM is controlled by the address decoding logic. Further, the address decoding logic allows the microprocessor to read the contents of the RAM to determine the data written to the output register, or read from the input register. In the present implementation of the invention, the input and output registers are grouped as one of three types, "write-only registers", "read-only registers", and "read/write registers". A specific location in the RAM is reserved for each of the input and output registers and the read/write function of the RAM is controlled as tabulated below (Table I). Thus, writes to the write-only registers, for instance, result in a write to the "shadow RAM", as well as to the I/O register; while a read from a write-only register results in the contents of the "shadow RAM" being transferred to the processor. This allows the processor to "read" write-only registers without having to save an image of them, thereby making it easier to update single bits in a register without affecting the other bits.

The "address map" of the controller is shown below (preferred):

The data written into the RAM by writing data to the output registers at addresses 2060-207F may be examined by reading from addresses 2060-207F or from addresses 0060-007F which correspond to RAM locations 0060-007F. The data written into the RAM by reading from the input registers at addresses 2000-205F may be examined by reading from addresses 0000-005F which correspond to RAM locations 0000-005F. The address decoding scheme is implemented using programmable logic devices.

Workers will perceive that this is a new and unusual address decoding function. For instance, the controller is made to automatically write into the RAM any time it writes into the output register (into locations in RAM dedicated to the output register). Also, whenever data is read from the input register, it is automatically recorded in a prescribed location in RAM.

For example, if the microprocessor writes XXYY into the output register, it will record this in RAM as well. Then, later when the processor initiates a read to the output register, the address decoder can direct it to the selected, associated RAM location--and it will appear that the output register is being read. Workers will appreciate how much convenience this gives to a programmer who may now reference the same memory locations writing to the output register and reading its image.

One problem addressed here is the occasion when such a microprocessor presents data to the output register and later needs to recall it, there is no convenient, known way to initiate such a read (from a write-only device). Heretofore, it has been suggested that one somehow AA: tie input register locations to associated output register locations; or BB: the microprocessor store the same data in a RAM for such later access--but this requires more complex overhead (added instruction bits), etc.

Workers will appreciate the unusual simplicity and other advantages of the instant technique, above described.

FIG. 6 shows a control logic block (e.g., one such for each disk drive actuator unit) apt for using the instant invention (which will be associated with microprocessor stage DMPU and communicate with interface DINT, as workers will understand).

The described invention implies that the input and output registers are "memory mapped". Some microprocessors have separate addressing for memory (EPROMs and RAMs) and input/output registers; the invention could also be applied to these type of controllers, as workers will appreciate.

Key features of this invention are that:

(1) Data written to an output register is simultaneously written to a RAM location.

(2) Data read from an input register is simultaneously written to a RAM location.

(3) The data may be read directly from the RAM to determine the data previously written to an output register or read from an input register.

(4) The same memory address may be used for writing data to an output register and reading the corresponding RAM location.

It will be understood that the preferred embodiments described herein are only exemplary, and that the invention is capable of many modifications and variations in construction, arrangement and use without departing from the spirit of the invention.

Further modifications of the invention are also possible. For example, the means and methods disclosed herein are also applicable to other types of disk files, as well as to related systems. Also, the present invention is applicable for enhancing other controller means.

The above examples of possible variations of the present invention are merely illustrative. Accordingly, the present invention is to be considered as including all possible modifications and variations coming within the scope of the invention as defined by the appended claims.