Circuit and Method for Balun Compensation

This invention relates to baluns and, in particular but not limited to, a circuit and method for compensating baluns.

A balun is a well known device having a single ended (unbalanced) side and a balanced side. The function of a balun is to provide voltages at first and second ports of its balanced side which are substantially equal in amplitude and substantially 180.degree. out of phase with respect to each other. In other words, the balun is to provide equal and opposite voltages to a balanced load with respect to ground.

When utilizing a balun, the balun must be impedance matched with the rest of the system in order to minimize losses and distortion and maximize bandwidth, for example, in balanced amplifier applications. In trying to match the balun with the system, the prior art utilizes traditional measurements on the single ended side of the balun. For example, in measuring the frequency response of a balun, first and second baluns are serially coupled wherein their balanced sides are interconnected. A signal is applied at the single ended side of the first balun, while the signal appearing at the single ended side of the second balun is observed. From this measurement, one can obtain the bandwidth, insertion loss and return loss for each balun (assuming that each balun is substantially identical). However, these measurements do not convey any information about the amplitude and phase relationships appearing at the balanced side of the balun.

Hence, there exists a need for recognizing that the amplitude and phase of the voltage signals appearing at the balanced side of a balun may degrade with frequency and for further providing a circuit and method for providing compensation for such amplitude and phase degradation.

Briefly, the present invention provides a circuit and a method for amplitude and phase compensating first and second voltages appearing at the balanced side of a balun. The present invention first realizes that the amplitude and phase of the voltages appearing at the balanced side of a balun do indeed degrade with frequency. Further, the present invention provides an amplitude and phase compensation circuit having a predetermined optimized electrical length and characteristic impedance that is inserted in series with a port on the balanced side of the balun. The characteristic impedance is optimized such that the amplitude difference between first and second voltage signals is minimized. Further, the electrical length is optimized such that the magnitude of the phase difference between first and second voltage signals is maximized.

FIG. 1 is a detailed schematic diagram illustrating a first embodiment of an amplitude and phase compensated balun in accordance with the present invention;

FIG. 2 is a detailed schematic diagram illustrating a second embodiment of an amplitude and phase compensated balun in accordance with the present invention; and

FIG. 3 is a detailed schematic/block diagram utilizing the present invention to improve performance of an amplifier.

Referring to FIG. 1, a detailed schematic diagram illustrating a circuit and method for providing amplitude and phase compensation for voltage signals appearing at first and second ports on the balanced side of balun 10 is shown. Balun 10 is shown as a three port device having first port P1 coupled to terminal 12, second port P2 coupled through amplitude and phase compensation circuit 14 to terminal 16. Further, balun 10 includes third port P3 coupled to terminal 18. It is understood that port P1 is on the single ended side of balun 10, while ports P2 and P3 are on the balanced side of balun 10. Further, it is understood that balun 10 includes three twisted wires wherein a first wire has a first end coupled to port P1 and a second end coupled to a first end of a second wire and to port P2 Further, the second end of the second wire is coupled to a first end of a third wire, while the second end of the third wire is coupled to port P3.

In general, if an input signal is applied at terminal 12 (and hence to port P1 ), then ideally ports P2 and P3 of balun 10 should provide equal amplitude voltage signals that are substantially 180.degree. out of phase and wherein the amplitude of these voltage signals is substantially equal to one-half the amplitude of the voltage signal applied terminal 12 (less any loss through balun 10 as is understood).

The present invention realizes that as the frequency of operation of balun 10 increases, the voltage signals appearing at ports P2 and P3 degrade with respect to frequency. That is, as the frequency increases, the amplitude difference between the voltage signals appearing at ports P2 and P3 increases, while the phase difference between the voltage signals appearing at ports P2 and P3 are no longer substantially 180.degree. out of phase with respect to each other.

Moreover, the present invention then realizes that by inserting an amplitude and phase compensation circuit such as transmission line 14 in series with port P2 the amplitude and phase of first and second voltage signals respectively appearing at terminals 16 and 18 can be compensated with respect to frequency. In particular, by appropriately selecting optimized values for the characteristic impedance (Zo) and the electrical length (Eo) of transmission line 14 the amplitude difference between the first and second voltage signals can be minimized, while the magnitude of the phase difference between the first and second voltage signals can be maximized. By maximizing the magnitude of the phase difference between the first and second voltage signals, it is intended to mean that the phase difference between the first and second voltage signals is made substantially equal to 180.degree.. In this manner, the first and second voltage signals provided at terminals 16 and 18 are said to be balanced.

In order to optimize the values for the characteristic impedance and the electrical length of transmission line 14 any RF linear analysis program capable of handling distributed elements may be utilized such as Hewlett Packard's Microwave Design System (MDS) or Touchstone. For example, by taking three port measurements at ports P1, P2 and P3 of balun 10, a mathematical model of balun 10 can be created as is well known in the art. Further, by adding transmission line 14 in series at port P2 a mathematical model of the circuit shown in FIG. 1 can be created.

The characteristic impedance and the electrical length of transmission line 14 is then optimized by simultaneously selecting a characteristic impedance such that the amplitude difference between the first and second voltage signals appearing at terminals 16 and 18 is minimized, while the magnitude of the phase difference between the first and second voltage signals appearing at terminals 16 and 18 is concurrently maximized.

In summary, the present invention provides an amplitude and phase compensation circuit in series with a port on a balanced side of a balun in order to provide first and second voltage signals that are balanced. The amplitude and phase compensation circuit has at least two parameters associated therewith: i) a characteristic impedance and ii) an electrical length. The characteristic impedance and the electrical length of the amplitude and phase compensation circuit are selected such that the amplitude difference between the first and second voltage signals is minimized, while the magnitude of the phase difference between the first and second voltage signals is maximized.

Although FIG. 1 shows transmission line 14 being utilized to provide the amplitude in phase compensation, it is understood that a combination of lumped inductive and capacitive components having selected characteristic impedance and electrical length could also be utilized as shown in FIG. 2. In particular, FIG. 2 illustrates the amplitude and phase compensation circuit to include inductor 20 and capacitor 22 wherein inductor 20 is coupled between the second port of balun 10 and terminal 16 while capacitor 22 is coupled between port P2 and ground reference. Moreover, it should be understood that other variations of lumped components may also be utilized such as including an additional capacitor coupled between terminal 16 and ground reference.

Referring to FIG. 3, a detailed schematic/block diagram utilizing the circuit shown in FIG. 1 to improve performance of an amplifier is shown. It is understood that components shown in FIG. 3 that are identical to components shown in FIG. 1 are identified by the same reference numbers. For example, baluns 10' and 10" of FIG. 3 are the same as balun 10 of FIG. 1. Moreover, transmission lines 14' and 14" of FIG. 3 are identical to transmission line 14 of FIG. 1.

The circuit shown in FIG. 3 further includes amplifier 30 for example, a cable television (CATV) amplifier, having balanced inputs and outputs.

In operation, balun 10' is utilized to take a single ended input signal appearing at terminal 32 in order to provide balanced signals at the balanced inputs of amplifier 30 via terminals 16' and 18'. Moreover, balun 10" is utilized to take the balanced outputs of amplifier 30 via terminals 16" and 18" and provide a single ended output signal at terminal 34. Thus, by utilizing baluns 10' and 10" to provide substantially balanced signals at the inputs and outputs of amplifier 30 the performance of amplifier 30 is substantially improved. For example, the bandwidth of amplifier 30 is increased and the distortion of amplifier 30 is reduced. These improvements can be critical for CATV amplifiers.

By now it should be apparent from the foregoing discussion that a novel circuit and method for providing amplitude and phase compensation for a balun in order to provide first and second voltage signals that are balanced has been provided. The compensation is achieved by adding an amplitude and phase compensation circuit such as a transmission line or inductive and capacitive lumped elements in series with one of the ports of the balun on the balanced side. The amplitude and phase compensation circuit includes characteristic impedance and electrical length parameters that are optimized such that the amplitude difference between first and second voltage signals is minimized, while the magnitude of the phase difference between first and second voltage signals is maximized.