Transistor Fabrication of a Twin Tub Using Angled Implant

This invention relates to methods of semiconductor integrated circuit fabrication.

As the use of integrated circuits becomes evermore commonplace, the popularity of CMOS Integrated Circuits has risen commensurately. Many CMOS Integrated Circuits are formed by creating a p-tub or p-well in a portion of a silicon substrate and creating an n-tub or n-well in the remainder of the silicon substrate. Some popular processes utilize fairly thick oxides to mask one tub (for example the already-formed p-tub) while the other tub (for example, the n-tub) is being formed. After both tubs have been formed, the thick oxide is removed. Unfortunately, the thickness of the oxide creates a height difference between the n-tub and the p-tub. The height difference contributes to an undesirably rough topography in the finished integrated circuits. Furthermore, the height difference also creates depth of focus problems for subsequent lithography steps.

Circuit designers have continually searched for methods to reduce the height difference between the n-tub and p-tub so that the deficiencies mentioned above may be alleviated.

The height difference problem is addressed by the present invention which illustratively includes: directing a first conductivity-type dopant species normally at a first portion of a substrate; and forming a material layer over the first portion of the substrate. Then, a second conductivity type dopant species is directed at an angle away from normal at a second portion of the substrate. The material layer substantially absorbs the second type dopant. A first conductivity type region is formed in the first portion of the substrate and a second conductivity type region is formed in the second portion of the substrate. Then at least one transistor is formed in the first region and one transistor is formed in the second region.

FIGS. 1, 2 and 3 are cross-sectional diagrams schematically illustrating a portion of an integrated circuit and useful in an understanding of an illustrative embodiment of the present invention.

In FIG. 1, reference numeral 11 denotes a substrate which may be, typically, silicon, doped silicon, or epitaxial silicon. In general, the term substrate denotes a body or a material upon which layers may be deposited or formed. Reference numeral 13 denotes an oxide layer, typically having a thickness of approximately 100 .ANG.. Layer 13 may be as thin as 50 .ANG.. (In previously used designs, it was necessary that layer 13 have a thickness of approximately 1000 .ANG..)

Reference 15 denotes a patterned photoresist material. Reference numeral 18 denotes a layer of silicon nitride which has been patterned with photoresist 15. Reference 17 denotes a p-type dopant species which is directed at substrate 11. Typically, the p-type dopant species may be boron. As can be appreciated from an examination of FIG. 1, p-type dopant species 17 penetrates oxide 13 and embeds itself in substrate 11. Embedded dopant ions are denoted by reference numeral 12. However, photoresist 15 and silicon nitride layer 18 tend to block the dopant ion 17 by absorbing them. Dopant ions absorbed in photoresist 15 are denoted by reference numeral 16.

After the p-type ion implantation step is completed, photoresist 15 is removed.

In FIG. 2, photoresist 15 has been removed and oxide 19 has been grown over those areas of substrate 11 which were not covered by nitride layer 18. The oxide growth process tends to diffuse embedded ions 12 into substrate 11, thereby forming a p-tub denoted by reference numeral 31. Illustratively, in the present invention, oxide 19 is grown until it has a total thickness, t.sub.1, of approximately 600 .ANG.. (By contrast, in conventional twin tub processing, oxide 19 may be grown to have a thickness of approximately 4000 .ANG..)

Next, nitride layer 18 is removed. Then, an n-type implant species 21 is directed at the entire wafer. Unlike conventional practice in which the n-type dopant species are directed normally at the surface of substrate 11, in the present invention, n-type implant species are directed at an angle .theta., measured away from normal. The n-type implant species tend to be absorbed in thick oxide 19, and they thereby have little effect on the p-tub 31. Typical n-type dopants are phosphorous or arsenic. Phosphorous, for example, may be implanted with a dose of 4.5 E 12/cm.sup.2 and an energy of 140 Kev. (As mentioned before, approximately 4000 .ANG. of oxide was previously grown over the p-tub to protect it from the 140 Kev implant.) Because the n-type dopant is directed at an angle .theta. towards oxide 13 (sometimes termed a screen oxide) oxide 13 appears to be effectively thicker. Consequently, as mentioned before, oxide 13 may have thickness, t.sub.2 as low as 50 .ANG., whereas in previous conventional practice, screen oxide 13 was typically 1000 .ANG.. The n-type dopant species embed themselves in that portion of substrate 11 below screen oxide 13, thereby forming an n-tub 33 (in FIG. 3). The wafer is rotated during the implantation process to prevent shadowing. In FIG. 3, oxides 19 and 13 have been removed leaving substrate 11 with p-tub 31 and n-tub 33. Because oxide 19 was made considerably thinner than usual (for example, approximately 600 .ANG.), the height difference between the top surface 23 of p-tub 31, and the top surface 25 of n-tub 33, denoted by t.sub.3, is considerably smaller than usual. Typically, in current practice the height difference t.sub.3 is equal to 1000-2000 .ANG., but in the present invention, the height difference may be expected to be approximately 200-500 .ANG.. A tub drive-in may be subsequently performed.

Conventional semiconductor processing may begin at this stage. For example, transistors may be formed over each tub region by forming gate oxides and polysilicon layers. The polysilicon and gate oxides may be patterned to form gates and subsequently source and drain regions may be formed. (Usually n-channel transistors are formed over the p-tub and vice-versa.) Then, a dielectric may be formed covering the gate and source regions; windows may be opened to the dielectric and conductors deposited therein. (The process may also be utilized if desired to form an n-tub first and then a p-tub.) Should the designer desire, the process may also be utilized with bipolar technology and one or more bipolar transistors may be formed in each tub.