Delay Line Loop for on-Chip Clock Synthesis With Zero Skew and 50% Duty Cycle

1. A synchronous clock generator a power supply high terminal and a power supply low terminal for synchronizing a synthesized 50% duty cycle clock signal with a reference clock signal, the period of the synthesized clock being equal to, or an integer submultiple of, the reference clock, each clock signal having a first and second state transition during each clock period, comprising: a) a controllable delay line with a nominal delay of one half of a period of the synthesized clock for accepting the synthesized clock signal at its input and a delayed replica at its output; b) a delay line control loop comprising a delay line controller coupled to the controllable delay line for producing at the controllable delay line output synthesized clock waveform with its first transition synchronous with a corresponding first transition of the reference clock signal, the delay of the delay line controlled by the delay line controller by comparing the reference clock first transition with a corresponding first transition of the synthesized clock signal at the output of the delay line; and c) a clock waveform generating loop comprising a clock waveform generator with its output connected to the input of the controllable delay line for synthesizing a 50% duty cycle waveform by selecting the first transition of the reference clock signal, inverting and delaying the first reference clock transition through the controllable delay line for a half-period of the synthesized clock which is representative of the synthesized clock second transition at the output of the controllable delay line, selecting and inverting the second transition of the synthesized clock at the controllable delay line output as an input to the controllable delay line so that after being delayed by the controllable delay line it is representative of a new first transition of the synthesized clock, repeating this process until a prescribed even number of synthesized clock half-period elapse so that the next reference clock transition is selected and inverted thereby repeating the synthesizing process and generating a periodic 50%, duty-cycle, synthesized clock waveform at the output of the controllable delay line with an integer number of periods for each reference clock cycle.

2. The synchronous clock generator as in claim 1 wherein the delay line control loop further comprises: a) a phase detector with a first input port and a second input port, the first input port connected to the reference clock signal, the second input port connected to the synthesized clock signal, for comparing the arrival times of corresponding first transitions of the two inputs and generating an output control signal representative of the first transition arrival time differences; and b) a low-pass filter connected to the output of the phase detector for producing at its output port a smooth output signal representative of the average of the time differences that is applied to the input of the inverting controllable delay line-for controlling the delay.

3. The synchronous clock generator as in claim 2 wherein the phase detector means comprises a D-type flip-flop with complementary output signals.

4. The synchronous clock generator as in claim 3 further comprising a charge pump circuit connected to the output of the D-type flip-flop for accepting from the D-type flip-flop the complementary output signals and generating dual-complementary, non-overlapping signals for controlling current mirroring transistors for increased noise immunity, with its output connected to the input of the low pass filter.

5. The synchronous clock generator as in claim 4 in which the controllable delay line inherent time jitter is made substantially insensitive to variations in the manufacturing process, supply voltage, temperature and reference clock frequency, wherein the charge pump circuit comprises: (a) a reference current source circuit for supplying a reference current to a charge pump controller; (b) a charge pump controller for producing a mirrored current image of the reference current by use of a voltage drop generated by the reference current, and for switching the mirrored current at an output line to provide a balanced capacitor network with selectable charge and discharge current images that are selected in response to the phase detector output control signals, and (c) the balanced capacitor network with its input connected to the output of the charge pump network for accumulating the charge and discharge currents for producing as an output a delay line control signal voltage, the balanced capacitor network comprising substantially equal first and second capacitors connected in series across the synchronous clock generator power supply, and the output line connected to the common junction of the first and second capacitors.

6. The synchronous clock generator as in claim 2 wherein the phase detector is an equal set-up and hold-time flip-flop network for power noise immunity of the charge pump circuit, comprising: (a) an edge triggered D-type flip-flop with a first data input and second data input, a first output and a second output, the first input accepting the input reference clock signal as a sampling clock and the second input accepting the delayed and inserted synthesized clock signal; (b) an output buffer and inversion network for accepting the first and second D-type flip-flop outputs and producing both an inverted buffered and a delayed buffered signal representative of both the first and second D-type flip-flop output for producing four non-overlapping signals as control inputs to the charge pump circuit.

7. The synchronous clock generator as in claim 2 having means for detecting improper operation at wake-up, comprising: (a) a tapped voltage-controlled delay line with tap output terminals having uniform time delay increments; and (b) means connected to the tapped voltage-controlled delay line for detecting improper operation by detecting if all tap output terminal signals are at the same logical level when the synthesized clock signal makes its second transition and, if not, outputting a signal indicative of a malfunction.

8. The synchronous clock generator as in claim 7 further having auto-reset means comprising: (a) means for accepting the malfunction indicator signal; and (b) means connected to the means for accepting the malfunction indicator signal for forcing proper initial system conditions in response to the malfunction indicator.

9. The synchronous clock generator as in claim 2 wherein the clock waveform generator further comprises: (a) input means with a first input for inputting the reference clock and a second input for inputting the delay-line output synthesized clock; (b) a state machine with a first input and a second input, the first input connected to the input means first input, the second input connected to the input means second input, for determining the high and low states, and high-low and low-high transitions of the synthesized and the reference block waveforms and providing an output signal indicative of the clock states and transitions; and (c) a waveform synthesizer means for generating a 50% duty cycle clock by synthesizing a clock signal, controller by the state machine output signal, the waveform synthesizer means output coupled to the delay line input, and the synthesized clock waveform generated as follows: (i) a first transition is made coincident with the reference clock first transition, (ii) a subsequent first state is made to correspond to the first state of the reference immediately after the first transition and persists until a second clock transition is synthesized, (iii) a second transition is made to occur immediately after the first transition of the synthesized clock has passed through a half period delay of the voltage controlled delay line, (iv) a subsequent second state is made to correspond to a state that is the complement of the first state and persists until the first transition of the synthesized clock occurs again and (v) subsequent states are generated by inverting and delaying the synthesized waveforms for a prescribed integer number of synthesized clock periods, and when the first transition of the reference clock wave occurs again, causing the above steps to be repeated.

10. The synchronous clock generator as in claim 9 wherein the waveform synthesizer means further comprises a four way selector switch controlled by the state machine output signal, the four way selector switch for generating the 50% duty cycle clock from a set of selector switch inputs, the set of selector switch inputs comprising the reference clock, the synthesized clock, a signal representative of the logic low state, and a signal representative of the logic high state.

11. A synchronous clock generator as in claim 10 wherein the four way selector switch provides transient free, make-before-break synthesized clock signal generation further comprising: (a) a four way selector switch first input connected to the reference clock for selecting, as the output, the first transition of the reference clock, represented by the change from the second logic state to the first logic sate of the reference clock signal, to be used as the input to the inverting controllable delay line; (b) a four way selector switch second input connected to a signal source representative of the high logic state for selecting as the subsequent selector switch output the input signal representative of the first logic state and holding that input until the second transition occurs; (c) a four way selector switch third input connected to the output of the inverting delay line for subsequently selecting, for the output of the selector switch, a half-period delayed and inverted synthesized clock first transition available out of the inverting delay line as the second transition from the first logic state to the second logic state; (d) a four way selector switch for the input connected to a signal level source representative of the low logic state for subsequently selecting and holding for output the input signal level representative of the second level signal, until the occurrence of the second logic level to first logic level transition of the synthesized clock signal; (e) means for repetitively sequencing through the above steps (c) and (d) for a prescribed number of synthesized clock cycles; and (f) means for repetitively sequencing through use of elements (a)-(e) each time a reference clock first transition occurs.

12. A microprocessor system with a central processing unit (CPU) and peripheral units driven by a common reference clock wherein the CPU comprises: (a) an arithmetic and logic processor operating synchronously with a CPU clock signal; and (b) a synchronous clock generator with an input connected to an externally supplied common reference clock for synthesizing a 50% duty cycle CPU clock signal synchronized with the externally supplied common reference clock, the synthesized CPU clock, connected to the arithmetic processor input, having an integer number of periods per common reference clock period, each clock signal having a first state following a first transition, and a second state following a second transition during each of their respective clock periods, comprising: (i) a controllable delay line with a nominal delay of one half of a period of the synthesized CPU clock for accepting the synthesized CPU clock signal at its input and producing a delayed replica at its output; (ii) a delay line control loop comprising a controllable delay line controller coupled to the controllable delay line for producing at the delay line output a synthesized CPU clock waveform with its first transition synchronous with a corresponding first transition of the reference clock signal, the delay of the controllable delay line controlled by the controllable delay line controller by comparing the reference clock first transition with a corresponding first transition of the synthesized CPU clock waveform at the output of the delay line; and (iii) a clock waveform generating loop comprising a clock waveform generator with its output connected to the input of the controllable delay line for synthesizing a 50% duty cycle waveform by selecting the first transition of the reference clock signal, inverting and delaying the first reference clock transition through the delay line for a half-period of the synthesized CPU clock, this inverted and delayed first transition of the reference clock signal being representative of the synthesized CPU clock second transition at the output of the controllable delay line, selecting and inverting the second transition of the synthesized CPU clock at the controllable delay line output as an input to the delay line so that after being delayed by the controllable delay line it is representative of a new first transition of the synthesized CPU clock, repeating this process until a prescribed even number of synthesized CPU clock half-periods elapse so that the next reference clock transition is selected and inverted thereby repeating the synthesizing process and generating a periodic, 50% duty-cycle, synthesized CPU clock waveform at the output of the delay line having an integer number of cycles for each reference clock cycle.

13. The microprocessor system of claim 12 wherein at least one of the peripheral units operates synchronously with respect to a peripheral unit clock applied to a peripheral unit clock input and comprises a synchronous clock generator with an input connected to the externally supplied common reference clock for synthesizing a 50% duty cycle peripheral unit clock synchronized with the externally supplied common reference clock, the synthesized peripheral unit clock signal output, connected to the peripheral unit clock input, having an integer number of periods per common reference clock period, each clock signal having a first state following a first transition, and a second state following a second transition during each clock period, comprising: a) a controllable delay line with a nominal delay of one half of a period of the synthesized peripherial unit clock, for accepting the synthesized clock signal at its input and producing a delayed replica at its output; b) a delay line control loop comprising a controllable delay line controller coupled to controllable delay line for producing coupled to delay line output a synthesized peripherial unit clock waveform with its first transition synchronous with a corresponding first transition of the reference clock signal, the delay of the controllable delay line controlled by coupled to delay line controller by comparing the reference clock first transition with a corresponding first transition of the synthesized clock signal at the output coupled to delay line; and c) a clock waveform generating loop comprising a clock waveform generator with its output connected to the input of the controllable delay line for synthesizing a 50% duty cycle waveform by selecting the first transition of the reference clock signal, inverting and delaying the first reference clock transition through the delay line for a half-period of the synthesized peripheral unit clock which is representative of the synthesized peripheral unit clock second transition at the output coupled to delay line, selecting and inverting the second transition of the synthesized peripheral unit clock coupled to delay line output as an input coupled to delay line so that after being delayed coupled to delay line it is representative of a new first transition of the synthesized peripheral unit clock, repeating this process until a prescribed even number of synthesized clock half-periods elapse so that the next reference clock transition is selected and inverted thereby repeating the synthesizing process and generating a periodic 50% duty-cycle, synthesized clock waveform at the output coupled to delay line with an integer number of cycles for each reference clock cycle.

14. A method for synthesizing a local clock signal that is synchronized with an external reference clock signal, the synthesized clock signal having a 50% duty cycle independent of the external clock duty cycle, the synthesized clock having an integer number of periods, N, for each period of the reference clock, each of the clocks having a periodic first state following a periodic first transition, and a periodic second state following a periodic second transition during each clock period, the synthesizing steps comprising: a) generating a synthesized clock first transition coincident with the first reference clock transition and generating a synthesized clock first state following the first transition; b) delaying the synthesized clock first transition and state by a controllable delay interval nominally corresponding to 1/2N of the reference clock period; c) inverting the delayed synthesized clock first transition and state for producing a synthesized clock second transition and state; d) delaying the synthesized clock second transition and state by the predetermined nominal delay of 1/2N of the reference clock period; e) inverting the delayed synthesized clock second transition and state for producing a synthesized clock first transition and state; f) repeating steps (b) through (e) until the next reference clock first transition occurs; g) comparing the next reference clock first transition with the corresponding synthesized clock transition that nominally occurs after every N synthesized clock periods; h) adjusting the controllable delay interval so that N periods of the synthesized clock corresponds to the reference clock period; and i) repeating steps a) through h).