Hold Circuit

The present invention relates to a hold circuit to keep a plural number of successive input data in time series.

For example, in a digital filter, a hold circuit keeps an input data in time series and the data is multiplied by a multiplier and integration is performed. Data once kept is successively transferred to the following hold circuit and input into another multiplier.

Conventionally, in a digital filter, hold and transferred data are digital data, and a little level down can be omitted. On the other hand, in computers whose main body is an analog operation, it is necessary to treat an analog data, and hold error can not omitted. However, any hold circuit considering about transferring of hold of an analog data is not known.

The present invention is invented so as to solve the above problems and has a purpose to provide a hold circuit capable of decreasing a hold error of an analog hold during transferring.

A hold circuit according to the present invention keeps a voltage signal, whose voltage level is compensated by a operational amplifier, at a capacitance by two steps, and a holding and transferring of voltage data is performed at the different timing. The accuracy is compensated, as well .

FIG. 1 is a circuit showing an embodiment of a hold circuit relating to the present invention.

FIG. 2 is a block showing a filter circuit using the same embodiment as FIG. 1.

FIG. 3 is a circuit showing a multiplication circuit in a filter circuit.

FIG. 4 is a circuit showing an example of a capacitive coupling.

FIG. 5 is a block diagram showing the second embodiment of a filter circuit.

FIG. 6 is a circuit diagram showing an adding circuit in the second embodiment of a filter circuit.

Hereinafter an embodiment of a hold circuit according to the present invention is described with referring to the attached drawings.

A hold circuit H in FIG. 1 has a pair of operational amplifiers Amp.sub.1 and Amp.sub.2 and a pair of field-effect transistors Tr.sub.1 and Tr.sub.2. An input data d.sub.in is input to a non-inverted input of Amp.sub.1. An output of Amp.sub.1 is connected with a drain of Tr.sub.1. A source of Tr.sub.1 is earthed through a capacitance C.sub.1 and fed back to an inverted inputs of Amp.sub.1. A clock CLK.sub.0 is input to a gate and Tr.sub.1 is conductive when CLK.sub.0 is high level. At the time that Tr.sub.1 is conductive, an output of Amp.sub.1 is controlled in order that a voltage equal to d.sub.in impresses to C.sub.1, and C1 stores electric charges in order that a charged voltage becomes d.sub.in.

A charged voltage of C.sub.1 is connected with a non-inverted input of Amp.sub.2. An output of Amp.sub.2 is connected with a drain of Tr.sub.2 and a source of Tr.sub.2 is earthed through a capacitance C.sub.2 and fed back to an inverted input of Amp.sub.2. In Tr.sub.2, a clock CLK.sub.1 of an inverted phase of CLK.sub.0 is input to a gate, and Tr.sub.2 is conductive in an opposite positioned phase of Tr.sub.1. When Tr.sub.2 is conductive, an output of Amp.sub.2 is controlled in order that a voltage equal to d.sub.in is impressed to a charged voltage of C.sub.1. C.sub.2 stores an electric charge in order that a charged voltage is equal to d.sub.in. And d.sub.out corresponding d.sub.in is output. As a result, d.sub.in by a 1 clock timing is kept and holding is surely performed by the predetermined timing because there is no influence in the following stage during charging of C.sub.1.

A feed back system using operational amplifiers Amp.sub.1 and Amp.sub.2 compensates accuracy of outputs, so that a hold error can be controlled in the minimum.

A hold circuit is used for a filter circuit shown in FIG. 2. Hold circuits are shown by from H.sub.11 to H.sub.18 and from H.sub.21 to H.sub.28 in FIG. 2.

In FIG. 2, a hold circuit has the first summing products circuit MC1 and the second summing products circuit MC2. The first summing products circuit MC1 is composed of a plural number of serially connected hold circuits from H.sub.11 to H.sub.18 and an output of each hold circuit H.sub.1k is input to a multiplication circuit M.sub.1k. On the other hand, the second summing products circuit MC2 is composed of a plural number of serially connected hold circuits from H.sub.21 to H.sub.28 and an output of each hold circuit H.sub.2k is input to a multiplication circuit M.sub.2k.

An input data D.sub.in is input to the first summing products circuit and it is transferred to the next hold circuit after it is once kept in each hold circuit. Then, data in time series of D.sub.in is kept in each hold circuit. This time series data is shown by X(t-k). Beforehand, the predetermined multipliers from a1 to a8 are input to each multiplication circuit from M11 to M18, and a following multiplication for the time series data is executed.

m.sub.1k is a result of multiplication of a multiplying circuit M.sub.1k.

Outputs of a multiplication circuit M.sub.1k and M.sub.1(k+1) are added by an adding circuit A.sub.1k, and an adding result is output to the next adding circuit A.sub.1(k+1). Therefore, an adding circuit A.sub.17 calculates a total of outputs of all multiplying circuits in the first summing products circuit. A following formula shows the total. ##EQU1##

To the second summing products circuit, an output A.sub.17 or an output H.sub.18 are input as an input data D.sub.m through a switch SW, and it is transferred to the next hold circuit after D.sub.m is once kept in each hold circuit from H.sub.21 to H.sub.28. Then, data of time series of D.sub.m is kept in each hold circuit. This sequential data is shown by Y(t-k). Predetermined multipliers from b.sub.1 to b.sub.8 are input in each multiplying circuit from M.sub.21 to M.sub.28, and the following multiplication for the time series data is executed.

m.sub.2k is a multiplied result of a multiplying circuit M.sub.2k.

Outputs of multiplication circuits M.sub.k2 and M.sub.2(k+1) are added by an adding circuit A.sub.2k, and the adding result is output to the next adding circuit A.sub.2(k-1). Therefore, an adding circuit A.sub.27 is a total of outputs of all multiplying circuits in the second summing products circuit. Then the total is shown by the following formula 2. ##EQU2##

And, an output of an adding circuit A.sub.21 is input to an adding circuit A.sub.17 in the first sunning products MC1 and an output of A.sub.17 is a total of multiplied result of both MC1 and MC2.

When SW is connected with a side of H.sub.18, Dm is X (t-8), then an output of MC2 is shown by formula 3. ##EQU3## Here, expressing b.sub.k =a.sub.(k+ 8). a total of MC1 and MC2 output from A.sub.17 is formula 4. ##EQU4## Then a characteristics of FIR type filter is obtained.

When SW is connected with a side of A.sub.17, then formula 5 is shown. ##EQU5## Generally expressing Y(t)=D.sub.m, and a characteristics of IIR type is obtained.

As mentioned above, switching only SW on a special circuit, SW realizes a filter of two types filters of FIR and IIR are realized and a filter with a comparative large stages using all hold circuits and multiplication circuits are realized in FIR type. That is, high speed filter with wide usage can be realized.

FIG. 3 shows an embodiment of a multiplication circuit M.sub.jk, M.sub.jk, has a pair of operational amplifiers Amp.sub.3 and Amp.sub.4, and a pair of field-effects transistors Tr.sub.3 and Tr.sub.4. An input analog data AX is input to a non-inverted input of Amp.sub.3. An output of Amp.sub.3 is connected with a drain of Tr.sub.3, and a source of Tr.sub.3 is earthed through capacitances C.sub.3 and C.sub.4. A voltage between C.sub.3 and C.sub.4 is fed back to an inverted input of Amp.sub.3. Tr.sub.3 is conductive when a digital input B is input to a gate and is high level. When Tr.sub.3 is conductive controlling an output of Amp.sub.3 in order that a voltage equal to AX impresses to C.sub.4, and electric change is stored in order that a charged voltage is Ax in C.sub.4. This time, a source voltage of Tr.sub.3 is Ax{(C.sub.3 -C.sub.4)/C.sub.3 }.

In Amp.sub.4, a non-inverted input is earthed, and its output is connected with a source of Tr.sub.4. A drain of Tr.sub.4 is earthed to C.sub.3 and fed back to an inverted input of Amp.sub.4. A digital data inverting B by an inverter INV is input to a gate of Tr.sub.4, and Tr.sub.4 is conductive when B is low level. When Tr.sub.4 is conductive, an output of Amp.sub.4 is controlled to be 0V at a drain of Tr.sub.4.

A source of Tr.sub.3 and a drain of Tr.sub.4 are connected with a capacitance C.sub.5 for outputting, and a voltage value multiplied a weight decided by a capacitive coupling with C.sub.5 is an output. That is,

M.sub.jk performs {(C.sub.3 -C.sub.4)/C.sub.3 } C.sub.cp.

c.sub.cp is a weight decided by capacitive coupling. Multiplication by multiplier 0 is executed.

A capacitive coupling is a circuit as shown in FIG. 4, and consists of a plural number of capacitances parallelly connected (here 8 capacitances from C.sub.51 to C.sub.58). When voltages from V.sub.1 to V.sub.8 are impressed to these capacitances, an output voltage V.sub.8 is shown by a following formula and a weighted addition is executed.

Providing circuits as FIG. 3 parallelly, inputting each bit of a digital data as B to the circuit, and setting {(C3-C4)/C3} Ccp in 2.sup.n, a multiplication of an analog data AX and a digital data is directly executed.

The above adding circuit A.sub.jk can be realized by the circuit of FIG. 4 with 2 or 3 inputs.

An output signal D.sub.out output by above composition is kept once in H.sub.out.

FIG. 5 shows the second embodiment of a filter circuit. Instead of an adding circuit A.sub.jk, one adding circuit At is used. If an output of each multiplying circuit M.sub.jk is m.sub.jk, then a weighted addition is executed by a capacitive coupling of capacitance C.sub.jk parallelly connecting, as shown FIG. 6. The manners of calculation is same as that of circuit in FIG. 4.

As mentioned above, a hold circuit relating to the present invention keeps a voltage signal, whose voltage level is compensated by a operational amplifier, at a capacitance by two steps, and holding and transferring of voltage data is performed at the different timing. The accuracy is compensated, as well so that a hold circuit capable of controlling a hold error of an analog hold in the minimum during transferring.