Real-Only Memory Device Incorporating Storage Memory Array and Security Memory Array Coupled to Comparator Circuirtry

1. A Read Only Memory (ROM) device for maintaining security of data in the ROM device comprising: a row address buffer connected to a row address pin for generating a row address, a column address buffer connected to a column address pin for generating a column address, row and column decoders each connected to the row and column address buffers, a security memory cell array coupled to said row and column decoders, including a storage memory cell array for storing program data of a user, and a security code cell array in which data bits of a security code are stored for maintaining the security of said program data, a sense amplifier connected to the column decoder, a comparison section connected to the output of the row address buffer and the sense amplifier for comparing data applied from outside the security code cell array with data stored in the security memory cell array, the row and column addresses designating the location of said security code cell array data, an output buffer connected to the comparison section, a control section connected to the comparison section, the row address pin, the column address pin and the row decoder, for providing a control signal, so that, if the comparison result of the comparison section indicates that the data applied from the outside are coincident with the stored security code cell array data in all address, then during the power on state the data of storage memory cell array can be read, otherwise, regardless of the power-on state, the data of storage memory cell array can not be read, an instantaneous pulse generator connected to the control section for forming a initial state of the control section at the time when power is initially turned on, an output enable signal buffer connected to an output enable pin for transmitting an output enable signal, an output buffer drive section, connected to the output enable signal buffer and the control section, for driving the output enable signal, and a chip enable signal buffer connected to the row address buffer, the column address buffer, the sense amplifier, the output enable signal buffer and the output buffer drive section, for applying a chip enable signal to at least one of the row address buffer and column address buffer.

2. The ROM device of claim 1 further comprising a address pattern recognition section connected to the control section for receiving a clock signal and connected to the row address buffer and column address buffer for receiving the row address and column address for operating the comparison section and the control section after reception of a predetermined address pattern, by applying a code comparison enable signal to the control section.

3. The ROM device of claim 2 wherein said comparison section includes a path selection logic section having an input stage connected to the output of the sense amplifier and a mode selection signal of the control section, and an output stage connected to the input stage of the output buffer, for controlling the output path of the sense amplifier and, a comparison output section including a first EXNOR gate array connected to the output of the row address buffer and to the output of the path selection logic section, and a first NAND gate connected to the first EXNOR gate array.

4. The ROM device of claim 3 wherein said control section includes a D-Flip Flop connected to the output stage of the comparison output section in the comparison section and to a set signal stage of the instantaneous pulse generator, a fusable section in which the input stage is connected to the output stage of the D-Flip Flop and the output stage is connected to the output buffer drive section, a counter connected to the output stage of the comparison section through a NOT gate and to a reset signal stage of the instantaneous pulse generator, second and third NAND gates connected to the output stage of the counter, a first NOR gate in which the input stage is connected to the output stage of the second and third NAND gates and the output stage is connected to the output buffer drive section, a mode selection section connected to the first NOR gate, the reset signal stage of the instantaneous pulse generator, the code comparison enable signal and to the fusable section, for generating said mode selection signal, a address transition detect and clock generator connected to the row and column address pins for generating said clock signal according to the address transition detection and then supplying the clock signal to the address pattern recognition section, a first delay section for firstly delaying the clock signal received from the address transition detect and clock generator and then supplying a delayed clock signal to the counter and the D-Flip Flop, a second delay section for secondly delaying the first delayed clock signal received from the first delay section and then supplying a secondly delayed clock signal to the mode selection section.

5. The ROM device of claim 4 wherein said mode selection section includes a first NOT gate connected to the output stage of the fusable section, a toggle flip-flop connected to the output stage of the first NOR gate, a second NOT gate connected to the code comparison enable signal from the output stage of the address pattern recognition section and, a second NOR gate having inputs connected to the first NOT gate output, the toggle flip flop output and to the second NOT gate output.

6. The ROM device of claim 3 wherein said address pattern recognition section includes a reference voltage applying section comprising two MOS FETs for providing a reference voltage of a low or high state, a second EXNOR gate array having a first input connected to the reference voltage applying section and a second input connected to the output stage of the row and column address buffer, a NAND gate array connected to the output stage of the second EXNOR gate array, a third NOR gate connected to the output stage of the NAND gate array, a 7 bit shift register connected to the output stage of the third NOR gate and to a reset signal stage of the instantaneous pulse generator, a second NAND gate having a first input stage directly connected to the first, third, fifth and seventh output bits of the shift register, and a second input stage connected to the second, fourth and sixth output bits of the shift register through respective NOT gates, a fourth NOR gate in which the input stage is connected to the output stage of the second NAND gate, a second toggle Flip-Flop connected to the output stage of the fourth NOR gate and to the reset signal stage of the instantaneous pulse generator for generating said code comparison enable signal, a third delay section connected to the output stage of an address transition detect and clock generator in the control section for delaying the clock signal and then supplying a delayed clock signal to the second toggle Flip-Flop and, a fifth NOR gate in which the input stages are connected to the clock signal generated from the address transition detect and clock generator and to the code comparison enable signal generated from the second toggle flip-flop and, the output stage is connected to the shift register through a NOT gate.

7. The ROM device of claim 1 wherein said comparison section includes a path selection logic section having an input stage connected to the output of the sense amplifier and a mode selection signal of the control section, and an output stage connected to the input stage of the output buffer, for controlling the output path of the sense amplifier and, a comparison output section including a first EXNOR gate array connected to the output of the row address buffer and to the output of the path selection logic section, and a first NAND gate connected to the first EXNOR gate array.

8. The ROM device of claim 7 wherein said control section includes a D-Flip Flop connected to the output stage of the comparison output section in the comparison section and to a set signal stage of the instantaneous pulse generator, a fusable section in which the input stage is connected to the output stage of the D-Flip Flop and the output stage is connected to the output buffer drive section, a counter connected to the output stage of the comparison section through a NOT gate and to a reset signal stage of the instantaneous pulse generator, second and third NAND gates connected to the output stage of the counter, a first NOR gate in which the input stage is connected to the output stage of the second and third NAND gates and the output stage is connected to the output buffer drive section, a mode selection section connected to the first NOR gate, the reset signal stage of the instantaneous pulse generator, a code comparison enable signal and to the fusable section, for generating said mode selection signal, a address transition detect and clock generator connected to the row and column address pins for generating a clock signal according to the address transition detection and then supplying the clock signal to an address pattern recognition section, a first delay section for firstly delaying the clock signal received from the address transition detect and clock generator and then supplying a delayed clock signal to the counter and the D-Flip Flop, a second delay section for secondly delaying the first delayed clock signal received from the first delay section and then supplying a secondly delayed clock signal to the mode selection section.

9. The ROM device of claim 8 wherein said mode selection section includes a first NOT gate connected to the output stage of the fusable section, a toggle flip-flop connected to the output stage of the first NOR gate, a second NOT gate connected to the code comparison enable signal from the output stage of the address pattern recognition section and, a second NOR gate having inputs connected to the first NOT gate output, the toggle flip flop output and to the second NOT gate output.

10. The ROM device of claim 7 wherein an address pattern recognition section includes a reference voltage applying section comprising two MOS FETs for providing a reference voltage of a low or high state, a second EXNOR gate array having a first input connected to the reference voltage applying section and a second input connected to the output stage of the row and column address buffer, a NAND gate array connected to the output stage of the second EXNOR gate array, a third NOR gate connected to the output stage of the NAND gate array, a 7-bit shift register connected to the output stage of the third NOR gate and to a reset signal stage of the instantaneous pulse generator, a second NAND gate having a first input stage directly connected to the first, third, fifth and seventh output bits of the shift, register, and a second input stage connected to the second, fourth and sixth output bits of the shift register through respective NOT gates, a fourth NOR gate in which the input stage is connected to the output stage of the second NAND gate, a second toggle Flip-Flop connected to the output stage of the fourth NOR gate and to the reset signal stage of the instantaneous pulse generator for generating a code comparison enable signal, a third delay section connected to the output stage of an address transition detect and clock generator in the control section for delaying a clock signal and then supplying a delay clock signal to the second toggle Flip-Flop and, a fifth NOR gate in which the input stages are connected to the clock signal generated from the address transition detect and clock generator and to the code comparison enable signal generated from the second toggle Flip-Flop and, the output stage is connected to the shift register through a NOT gate.