Method for Optimizing Piezoelectric Resonator-Based Networks

This invention relates to piezoelectric resonators and, specifically, to a method for optimizing the topology of a piezoelectric resonator-based network so that it may be implemented, either in monolithic or discrete form, with interconnects on one or either principal face of a piezoelectric plate or membrane.

A typical prior piezoelectric resonator comprises a wafer of piezoelectric material such as quartz or ceramic material provided with electrodes mounted on the wafer's opposing lateral surfaces. Upon application of an alternating voltage to the electrodes, the piezoelectric material is driven electrically in a predetermined vibrational mode, for example, thickness shear, thickness extensional, etc., depending on the orientation or polarization of the piezoelectric material. The resonant frequency of the resonator is dependent on the overall wafer and electrode thickness and increases with a decrease in thickness. At high frequencies very thin wafers, plates, or films are required in order to have a half wavelength established across the thickness. These thin structures may be formed by thin film deposition onto a suitable substrate which leaves one principal surface of the material relatively inaccessible for interconnects. Resonators may be fabricated from these thin films and through different network configurations or with additional circuitry, such resonators can be combined to form filters or oscillators.

Prior resonators have been constructed in a number of ways. The most prevalent method is to construct individual resonators, mount and package them and then connect the packaged resonators into various circuit configurations. In an effort to reduce the overall circuit size, more than one resonator may be fabricated on a single plate of piezoelectric material and then interconnected on the plate to form a circuit. As shown in U.S. Pat. No. 3,222,622, the wafer may be cut to a desired thickness and the electrodes then mounted on opposing surfaces of the wafer. Another approach exemplified in U.S. Pat. No. 3,590,287 is to utilize a deposition process. The electrodes and piezoelectric material are deposited as metalization layers and a thin film, respectively, on a substrate such as a quartz wafer.

Although satisfactory resonators can be constructed with these techniques, they have their drawbacks. In both cases the two opposing electrodes of the resonator are on opposing lateral surfaces of the piezoelectric material and not coplanar. These electrodes, which connect the resonator to other circuitry such as integrated circuits or discrete components, may not be favorably positioned for making such connections. This is especially true if the piezoelectric material rests on a substrate and the electrode between the two materials is thus buried. Connecting the buried electrode to a discrete component such as a resistor is quite difficult. The situation is further complicated by the desirability of production testing as many as 600 piezoelectric resonator networks on each 4-inch-diameter wafer substrate prior to final assembly. Microwave probe testing requires all interconnect electrodes be on the top surface of the piezoelectric film.

One solution suggested in U.S. Pat. No. 3,222,622 is to provide a nonplanar conductive interconnect between a poorly positioned electrode and an additional electrode mounted in a more favorable position. Connections to other circuitry may then be made from the additional electrode. As shown therein, an interconnect in the form of a discrete wire is added to a pi-network to connect an electrode mounted on the lower surface of the piezoelectric material to an electrode mounted on the upper surface of the material. The interconnect extends around the edge of the material, and is added as an additional step in the process of constructing the resonator.

An alternative solution might be to fabricate a via interconnect that extends through the piezoelectric material to make the desired connection. The interconnect is fabricated with additional steps in the process of constructing the resonator.

Neither of these solutions, however, is conducive to high volume, low cost manufacturing and testing by microelectronic techniques. Both add additional, costly steps to the manufacturing process. Within the microelectronic manufacturing context piezoelectric resonator networks must be designed and patterned to be compatible with manufacturing methods not employed within the conventional quartz crystal industry.

Therefore, an object of the invention is to provide a method for optimizing the topology of a piezoelectric resonator-based network which overcomes the drawbacks of the prior art.

Another object of the invention is to provide piezoelectric resonator-based networks in which electrodes may be selectively placed on the piezoelectric material to provide desired connections to other circuitry without the need for additional, nonplanar interconnects.

In accordance with these objects, the method of the invention comprises decomposing an original resonator within a network into a pair of serially connected resonators which share a common electrode. The composite characteristics of the serial connected resonators are chosen to match the characteristics of the original resonator. By such decomposition, an additional electrode is added to the network and is placed on the piezoelectric material surface opposing the surface to which is mounted the shared electrode for making a desired connection to other circuitry. The method does not require a nonplanar interconnect for connecting an electrode on one surface of the piezoelectric material to circuitry present at the opposing surface. The invention thereby eliminates the difficulty of providing access to electrodes of the resonator network for connection to other circuitry or for wafer scale testing during manufacturing.

The invention is applicable to monolithic resonator circuits as well as to discrete resonator circuits.

The foregoing and other objects, features, and advantages of the invention will become more apparent from the following detailed description of several preferred embodiments which proceeds with reference to the following drawings.

FIG. 1 is a schematic diagram of an electrical circuit that includes a piezoelectric resonator.

FIGS. 2A.1 and 2A.2 are perspective and cross sectional views of a discrete embodiment of the resonator represented in FIG. 1.

FIGS. 2B.1 and 2B.2 are perspective and cross sectional views of a second embodiment of the resonator represented in FIG. 1 including a full substrate supporting the piezoelectric material.

FIGS. 2C.1 and 2C.2 are perspective and cross sectional views of a third embodiment of the resonator represented in FIG. 1 including a partial substrate supporting the piezoelectric material.

FIG. 3 is a schematic diagram of an equivalent resonator formed by decomposing the original resonator into a pair of series connected resonators.

FIGS. 4A-B are perspective and cross sectional views of an implementation of the series connected resonators of FIG. 3 such that both electrodes are on the top surface.

FIGS. 5A-D illustrate the process for fabricating the series connected resonators of FIG. 4.

FIG. 6 is a schematic diagram of an electrical circuit that includes a T network comprising several piezoelectric resonators and/or shunt elements.

FIGS. 7A-C are perspective and cross sectional views of a monolithic implementation of the T network represented in FIG. 6

FIG. 8 is a schematic diagram of an equivalent T network formed by decomposing a resonator in the T network into a pair of series connected resonators.

FIGS. 9A-C are perspective and cross sectional views of an implementation of the T network represented in FIG. 8.

FIGS. 10A-D illustrate the process for fabricating the T network of FIG. 9.

FIG. 11 is a schematic diagram of an electrical circuit that includes a pi network comprising piezoelectric resonators.

FIG. 12 is a perspective view of a monolithic implementation of the pi network represented in FIG. 11.

FIG. 13 is a schematic diagram of an equivalent pi network formed by decomposing each resonator of the network into a pair of series connected resonators.

FIG. 14 is a perspective view of an implementation of the pi network represented in FIG. 13.

FIGS. 15A-D illustrate the process for fabricating the pi network represented in FIG. 14.

FIG. 16 is a schematic diagram of an electrical circuit that includes an L network comprising piezoelectric resonators and shunt elements.

FIG. 17 is a perspective view of a monolithic implementation of the L network represented in FIG. 16.

FIG. 18 is schematic diagram of an equivalent L network formed by decomposing each of its resonators into a pair of series connected resonators.

FIG. 19 is a perspective view of an implementation of the L network represented in FIG. 18.

FIGS. 20A-D illustrate the process for fabricating the L network of FIG. 19.

FIG. 21 is a schematic diagram of an electrical circuit that includes a ladder network comprising piezoelectric resonators and shunt elements.

FIG. 22 is a perspective view of a monolithic implementation of the ladder network represented in FIG. 21.

FIG. 23 is a schematic diagram of an equivalent ladder network formed by decomposing a resonator of the network into a pair of series connected resonators.

FIG. 24 is a perspective view of an implementation of the ladder network represented in FIG. 23.

FIGS. 25A-D illustrate the process for fabricating the ladder network of FIG. 24.

Referring now to FIG. 1, there is shown a schematic diagram of an electrical circuit that includes a piezoelectric resonator X1. Resonator X1 is of conventional design and includes a pair of electrodes M1 and M2 mounted on opposing surfaces of piezoelectric material 30. The resonator X1 is shown connected within an electrical circuit that includes a voltage source V.sub.g in series with a generator impedance represented by resistor R.sub.g. The resistor R.sub.g is connected to the first electrode M1 of resonator X1. The second electrode M2 is connected to a load impedance represented by resistor R.sub.i, which in turn is also connected to the voltage source V.sub.g to complete the circuit. Resonator X1 in this circuit is a simple filter, with electrode M1 receiving an input signal and electrode M2 providing an output signal. As a filter, resonator X1 passes electrical signals with the same frequency as its piezoelectric material's series resonant frequency and attenuates or suppresses signals of other frequencies.

FIGS. 2A-C show different possible embodiments (not to scale) of the resonator X1 based on the circuit topology of FIG. 1. FIGS. 2A.1 and 2A.2 illustrate a bulk crystal resonator X1 comprising overlapping, opposing electrodes M1 and M2 mounted on opposing surfaces of the piezoelectric material 30. To construct the resonator using known techniques, the crystal material is placed in a vacuum chamber and the metal for electrodes M1 and M2 is introduced as a vapor that deposits on the material's surfaces 42 and 44. The metal is then etched to form the desired electrodes. Resonators of this type are typically driven at their fundamental frequency. The portion of the embodiment between the dashed lines in FIG. 2A.2 forms the actual resonator X1. The portion 38 of electrode M1 outside the dashed lines forms a lead for interconnecting the resonator to other circuit elements such as resistor R.sub.g. Similarly, the portion 40 of electrode M2 outside the dashed lines forms a lead for interconnecting the resonator to other circuit elements such as resistor R.sub.i.

FIGS. 2B.1 and 2B.2 show a second embodiment of the resonator X1. Electrode M2 is deposited as a metal layer on a supporting substrate 32 such as silicon for a transducer or resonator. Deposited on top of layer M2 is a film of piezoelectric material 30. To complete the resonator X1 the metal layer M1 is deposited on top of the piezoelectric material 30. This embodiment may be used, for example, where it is desirable to place the resonator on a semiconductor wafer for interconnection to portions of adjacent integrated circuits. As is known in the art, the supporting substrate underneath the actual resonator X1 changes the electrical characteristics of the resonator from that of FIG. 2A. The resonator of FIG. 2B is an overmoded resonator and is operated at high harmonics of the fundamental frequency.

FIGS. 2C.1 and 2C.2 show a third embodiment of the resonator X1 in which a selected part of the substrate 32 directly below the resonator has been removed. The remaining substrate has no effect on the electrical characteristics of the resonator. The resonator X1 in FIG. 2C can thus have the same electrical characteristics as the resonator X1 in FIG. 2A, and may be constructed on a semiconductor wafer for interconnection to other circuitry on the substrate.

For the sake of simplicity, the present invention and prior art will be further described only with respect to resonators of a type such as shown in FIGS. 2C.1 and 2C.2 with substrate 32 eliminated from the drawings. It should be understood, however, that the invention is also equally applicable to other types of resonators such as those shown in FIGS. 2A and 2B.

A drawback of the conventional topology of FIG. 1 and resultant embodiments of FIGS. 2A-C is the consequent nonplanar locations of the electrodes M1 and M2. The lead 40 of electrode M2, for example, is mounted to the lower surface of the piezoelectric material 30 and, if substrate 32 is present, buried between the substrate and piezoelectric material 30. To connect lead 40 to a discrete component such as resistor R.sub.i requires a bonding pad on the upper surface 42 of material 30 and either (1) a discrete nonplanar interconnect from the electrode M2 around the edge of the piezoelectric material (as in U.S. Pat. No. 3,222,622) or (2) a via interconnect through the material 30 to its upper surface. If, on the other hand, resistors R.sub.g and R.sub.i are implemented in monolithic form on substrate 32, it may be desirable to connect to resistor R.sub.g on the substrate 32 at the lower surface 44 of the material 30. This connection would require a interconnect from electrode M1 to the lower surface.

Regardless of where connections are desired, both connecting options are poor. A discrete nonplanar interconnect is too costly to design into a monolithic implementation with wafer scale manufacturing. A via interconnect requires forming a high definition hole in the piezoelectric material 30 and depositing conducting material into the hole to electrically connect an electrode to the opposing material surface. In typical piezoelectric resonators, extremely high height-to-width ratios are encountered which affect the reliability of such internal interconnects. Reducing the ratio, however, requires that the width of the via be increased. This in turn may unacceptably increase the lateral area required for the via. Moreover, forming the via interconnect would require additional fabrication processing steps and the processing steps and chemical composition might not be compatible with the substrate 32 material.

The present invention provides a method of optimizing the topology of a piezoelectric resonator-based network so that nonplanar interconnects are not required for making such connections. The method, which is applicable to the single resonator of FIG. 1 as well as to multiple resonator networks to be discussed, places additional electrodes where they are desired and provides a resonator network with electrical characteristics equivalent to the characteristics of the original resonator network.

FIG. 3 is a schematic diagram of a resonator equivalent to the resonator of FIG. 1 in which the topology is optimized for placing an additional electrode. The optimized network is formed by decomposing resonator X1 into a pair of series connected resonators X11 and X12. This decomposition in the present embodiment comprises locating a resonator in the network, such as X1, and replacing it with two series connected resonators X11 and X12 which are connected only to each other at a shared electrode M2. Electrode M2 is referred to as a floating electrode since it does not connect the resonators to other circuitry. Electrodes M1 and M3, on the other hand, are referred to as connecting electrodes since they connect the network to other circuitry, such as resistors R.sub.g and R.sub.i. The two series resonators X11 and X12 are designed to have composite characteristics that match those of the resonator X1 to preserve the original characteristics of the resonator. From a functional point of view, the resonators of FIG. 3 are equivalent to the resonator of FIG. 1, but an additional electrode M3 has been added which replaces electrode M2 as a connecting electrode to other circuitry.

The difference between the conventional and new circuit topologies can be seen in the perspective and cross sectional views of the implementation of the equivalent circuit in FIGS. 4A-B. Whereas the electrodes that connect to other circuitry were on opposing surfaces of piezoelectric material 30 in FIGS. 2A-C, they are now on the same surface in FIG. 4 because of the addition of the third electrode M3. Electrodes M1 and M3 now form such a pair of planar connecting electrodes mounted to surface 42 of the piezoelectric material 30. Electrode M2, which is shared by resonators X11 and X12, is mounted to the opposing surface 44. Electrode M1 and M3 are mounted in overlapping relation to electrode M2 to create two series connected resonators that are connected only to each other at electrode M2. Electrode M2 is thus a floating electrode that does not connect to other circuitry. By decomposing the resonator X1 into the series connected resonators X11 and X12, the third electrode M3 is added on a surface opposing the surface on which the shared electrode M2 resides. This arrangement allows the network to connect to resistors R.sub.g and R.sub.i through leads 38 of electrode M1 and lead 46 of electrode M3. If desired, electrodes M1 and M3 could as easily be placed on the lower surface 44 (if R.sub.g and R.sub.i were substrate-based resistors) by reversing the implementation's fabrication steps.

The method is not limited to placing connecting electrodes on the same surface of the piezoelectric material, but may be employed for placing them on opposing surfaces as well. This may occur, as will be seen, where a connection to an adjacent integrated circuit is desired at the lower surface 44 as well as a connection to a discrete component at the upper surface 42.

The method for optimizing the circuit topology therefore comprises the following steps. First an electrical resonator in the network is decomposed into a pair of series connected resonators to add an additional electrode to the network, the resonators sharing a common electrode. The composite characteristics of the series connected resonators are matched to those of the original resonator to preserve the original characteristics of the network. In the implementation of FIG. 4, this matching is done by changing the overlapping areas of the electrodes M1,M2 and M3,M2 so that the bulk capacitance of each series connected resonator X11, X12 is double the original bulk capacitance of resonator X1:

The additional electrode is then placed on a surface of the piezoelectric material 30 opposing the surface to which the shared electrode is mounted for making the desired connection. For example, a one GigaHz aluminum nitride resonator 400 micrometers.times.400 micrometers.times.5 micrometers thick has a capacitive reactance of 50 ohms. Such a resonator could be decomposed into two resonators each 566 micrometers.times.566 micrometers and series connected. The increase in device area caused by the decomposition is partially offset by not having to etch a via to gain access to bottom electrode or provide for insulating the bottom electrode extension from substrate 32.

FIGS. 5A-D illustrate the process for fabricating the series connected resonators of FIG. 3 as implemented in FIG. 4 on a substrate 32. FIG. 5A shows the first layer metalizations that form electrode M2. FIG. 5B shows the deposition of the piezoelectric material 30. FIG. 5C shows a second layer metalization that forms electrodes M1 and M3. FIG. 5D is a schematic view showing the relative locations of resonators X11 and X12 within the implementation.

The described method may be applied to any resonator network for the purpose of placing an additional connecting electrode on a desired surface of the piezoelectric material 30. In the embodiment described above, the additional connecting electrode was placed on the same surface as the connecting electrode M1 was placed. It may be desirable in some cases, however, to place an additional connecting electrode on the surface opposing the other connecting electrode so that the connections to other circuitry are on opposing surfaces of the piezoelectric material 30.

FIG. 6 is a schematic diagram of an electrical circuit that includes a T resonator network. The T network is comprised of resonator X1, a series resonator X2 and a shunt element such as piezoelectric resonator X3. All of the resonators share a common electrode M2. Electrode M1 connects the T network via resonator X1 to other circuitry such as resistor R.sub.g and electrode M3 connects the network via resonator X2 to other circuitry such as resistor R.sub.i. Another electrode MG connects the network via resonator X3 to signal ground. Electrode M2 in this network is a floating electrode.

FIGS. 7A-C are perspective and cross sectional views of an implementation of the T network based on the circuit topology of FIG. 6. Electrodes M1, M3 and MG are mounted as coplanar metal layers on supporting substrate 32 (not shown). Deposited on top of these electrodes is the film of piezoelectric material 30. To complete resonators X1, X2 and X3, the metal layer M2 is deposited on the upper surface 42 of the piezoelectric material 30. The portion of the implementation between pairs of dashed lines form the resonators X1, X2, and X3, respectively. The darker shading of FIG. 7A illustrates the top and bottom electrode overlap regions that form resonators X1, X2, and X3. The portion 38 of electrode M1 outside resonator X1 forms a lead for interconnecting the resonator to other circuit elements such as resistor R.sub.g. Similarly, the portion 46 of electrode M3 outside the dashed lines defining resonator X2 forms a lead for interconnecting the resonator to other circuit elements such as resistor R.sub.i. Both electrodes M1 and M3 are buried between substrate 32 (not shown) and material 30.

If it is desired to make a connection to the network at the upper surface 42 of piezoelectric material 30, the method of the present invention is employed to optimize the network's topology for that purpose. FIG. 8 is a schematic diagram of an equivalent T network formed by decomposing resonator X2 into a pair of series connected resonators X21 and X22. Resonators X1 and X21 form a pair of series connected resonators sharing a first electrode M2. Resonator X3 is a shunt element that also connects to electrode M2 and to signal ground via electrode MG. A resonator X22 is series connected to resonator X21 at electrode M3. But unlike other electrodes within the T network, only the two resonators are connected at electrode M3. The additional resonator X22 adds an additional connecting electrode M4 to the T network. The composite characteristics of the series connected resonators are chosen to match the characteristics of resonator X2 which they replace so that the network's electrical characteristics remain unchanged.

FIGS. 9A-C are perspective and cross sectional views of a monolithic implementation of the network of FIG. 8. With resonator X2 replaced with series connected resonators X21 and X22, the additional connecting electrode M4 is deposited on the upper material surface 42. Resonators X21 and X22 are formed by overlapping areas of electrodes M2, M3 and M4, as indicated by the dashed lines or heavy shading defining the resonators. The portion of electrode M4 outside the dashed lines defining resonator X22 forms a lead 64 on the upper surface 42 of piezoelectric material 30 for interconnecting the T network to other circuitry. With this additional electrode, electrode M1 may connect to an adjacent integrated circuit at lower surface 44 and electrode M4 may be bonded to a discrete component at upper surface 42.

FIGS. 10A-D illustrate the process for fabricating the implementation of FIG. 8 as implemented in FIG. 9. FIG. 10A shows the first layer metalization that form electrodes M1, M3 and MG. FIG. 10B shows the deposition of the piezoelectric material 30. FIG. 10C shows a second layer metalization that forms electrodes M2 and M4. FIG. 10D is a schematic view showing the relative locations of resonators X1, X21, X22 and X3 within the implementation of the T network.

If desired, resonator X3 of FIG. 8 may be decomposed to produce a pair of series connected resonators as the shunt element. This decomposition would place signal ground on an opposing surface of material 30 from other electrodes X1 and X2 that connect the network to other circuitry.

The method of the invention covers other resonator networks as well. FIG. 11 shows the topology of a conventional pi network within a circuit. The network comprises several connected resonators X1, X2 and X3. Electrode M1 is shared by resonators X1 and X2 and provides a lead for interconnecting the network to other circuitry such as resistor R.sub.g to receive an input for the network. Similarly, electrode M2 is shared by resonators X1 and X3 and provides a lead for interconnecting the network to other circuitry such as resistor R.sub.i to provide an output for the network. Electrodes MG1 and MG2 complete resonators X2 and X3, respectively, and are leads for interconnecting the network to signal ground. These electrodes, however, are on opposing surfaces of the piezoelectric material 30 because of the circuit topology.

FIG. 12 is a perspective view of a monolithic implementation of the pi network of FIG. 11. Electrodes M1 and MG are on upper material surface 42 and electrodes MG1 and M2 is adjacent to the lower material surface 44.

The topology of the circuit in FIG. 11 has a distinct disadvantage when implemented in either monolithic or discrete form. The electrodes MG1 and MG2 are on opposing surfaces of piezoelectric material 30, although they are both signal ground. To join them requires a nonplanar interconnect. If the two electrodes were on the same surface, however, they could be combined into a single electrode. If it is desired to connect electrode M2 to other circuitry at the lower surface 44, then a nonplanar interconnect from electrode M2 to the lower surface is required.

These disadvantages are overcome by application of the present method to optimize the circuit's topology. FIG. 13 is a schematic diagram of an equivalent pi network formed according to the method by decomposing each resonator into a pair of series connected resonators. Resonator X1 is replaced with series connected resonators X11 and X12, adding an additional electrode M3. Resonator X2 is replaced with series connected resonators X21 and X22, adding an additional electrode M4. Resonator X3 is replaced with series connected resonators X31 and X32, adding an additional electrode M5. In each case, the composite characteristics of the series connected resonators are chosen to match the characteristics of the replaced resonator so that the pi network's electrical characteristics remain unchanged.

The replacement of resonators X2 and X3 is optional, depending only on the desired location of the signal ground electrode MG. An equivalent pi network that includes resonators X2 and X3 would comprise a first pair of resonators such as X11 and X2 sharing a first electrode for connection to other circuitry. A second pair of resonators such as X12 and X3 would share a second electrode for connection to other circuitry. A series connected pair of resonators would then be formed comprising resonators X11 and X12 and a third electrode such as electrode M2. The series connected pair of resonators would be the only connections to electrode M2.

FIG. 14 is a perspective view of a monolithic implementation of the equivalent network of FIG. 13, taken to show the coplanar electrodes M1, M3, MG1, and MG2 mounted on upper surface 42 for connection to other circuitry. Electrodes M2, M4 and M5 are adjacent to the lower surface 44 of the piezoelectric material 30. Electrodes MG1 and MG2 are combined into a single electrode. Alternatively, electrodes M1 and M3 may be mounted adjacent to the lower surface 44, with the positions of the other electrodes reversed accordingly, by changing the fabrication steps. If it is desired to have electrodes MG1 and MG2 on a surface opposing the electrodes M1 and M3, then resonators X2 and X3 are not decomposed and electrodes M4 and M5 are not added.

FIGS. 15A-D illustrate the process for fabricating the series connected resonators of FIG. 13 as implemented in FIG. 14. FIG. 15A shows the first layer metalization that forms electrodes M2, M4 and M5. FIG. 15B shows the deposition of the piezoelectric material 30. FIG. 15C shows a second layer metalization that forms electrodes M1, M3 and MG1 and MG2 combined. FIG. 15D is a schematic view showing the relative locations of the six resonators within the monolithic implementation of the pi network.

The optimizing method also covers networks such as L networks. FIG. 16 shows the topology of a conventional L-network within an electrical circuit. The L network comprises a series resonator X1 and a shunt element such as resonator X2. Electrode M1 of resonator X1 provides a lead for interconnecting the network to other circuitry such as resistor R.sub.g to receive an input for the network. Similarly, electrode M2, which is shared by resonators X1 and X2, provides a lead for interconnecting the network to other circuitry such as resistor R.sub.i to provide an output for the network. Electrode MG completes resonator X2 and is a lead for interconnecting the network to signal ground.

FIG. 17 is a perspective view of an implementation of the network of FIG. 16. It can be readily seen that the electrodes M1 and M2 are on opposing surfaces of the piezoelectric material 30. If both leads 38 and 40 are to be located on lower surface 44 of material 30, then lead 38 will have to be moved to lower surface 44.

With the method of the invention, this connection is made by decomposing resonator X1 into series connected resonators X11 and X12, as shown in the schematic diagram of FIG. 18. This adds an additional electrode M3 on the upper surface 42. If it is desirable to have electrode MG (signal ground) on the upper surface as well, then resonator X2 should be decomposed into series connected resonators X21 and X22, adding the additional floating electrode M4. The optimized L network thus comprises a first resonator such as X12 that includes a first electrode M3 for connection to other circuitry. A shunt element such as resonator X2 of FIG. 16 is connected to the resonator X12 at electrode M3. To add the additional electrode needed for connecting at upper surface 42, resonator X11 is series connected to resonator X12 at electrode M2. Resonators X11 and X12 are the only connections to electrode M2. The series connected resonators place electrode M1 on the same upper surface 44 as electrode M3.

FIG. 19 is a perspective view of a monolithic implementation of the equivalent network of FIG. 18, taken to show the coplanar electrodes M1 and M3 on upper surface 42. Alternatively, electrodes M1 and M3 may be mounted adjacent to the lower surface 44, with the positions of the other electrodes reversed accordingly. If it is desired to have electrode MG on a surface opposing electrodes M1 and M3, then resonator X2 is not decomposed and electrode M4 is not added.

FIGS. 20A-D illustrate the process for fabricating the series connected resonators of FIG. 18 as implemented in FIG. 19. FIG. 20A shows the first layer metalization that forms electrodes M2 and M4. FIG. 20B shows the deposition of the piezoelectric material 30. FIG. 20C shows a second layer metalization that forms electrodes M1, M3 and MG. FIG. 20D is a schematic view showing the relative locations of the four resonators within the monolithic implementation of the optimized L network.

The method is not limited, of course, to the basic resonator networks described above. It may be applied wherever it is desirable to place an electrode on a specific surface of the piezoelectric material for making a connection to other circuitry. The versatility of the method can be seen in optimizing the circuit of FIG. 21. The circuit shown is a T ladder network comprising a number of piezoelectric resonators and shunt elements that may also be piezoelectric resonators.

FIG. 22 is a perspective view of the ladder network of FIG. 21. It can be readily seen that the electrode M1 is adjacent to upper surface 42 and electrode M4 adjacent to lower surface 44 of the piezoelectric material 30. Consequently lead 38 of electrode M1 is exposed on the upper surface and lead 64 of electrode M4 is adjacent to the piezoelectric material's lower surface 44. If electrode M4 is to be bonded to discrete components, then lead 64 must be connected to the upper surface 42.

With the method of the invention, this connection can be made by decomposing resonator X2 into series connected resonators X21 and X22, as shown in the schematic diagram of FIG. 23. This adds an additional electrode M5 on the upper surface 42, as shown in FIG. 24, with its own lead 70. Both leads 38 and 70, which connect the ladder network to other circuitry, are now in a position where such connection may be easily made. Electrodes MG1 and MG2 (signal grounds) are also on upper surface 42 for ease of connection.

FIGS. 25A-D illustrate the process for fabricating the series connected resonators of FIG. 23 as implemented in FIG. 24. FIG. 25A shows the first layer metalization that forms electrodes M2 and M4. FIG. 25B shows the deposition of the piezoelectric material 30. FIG. 25C shows a second layer metalization that forms electrodes M1, M3, M5 and signal ground (electrodes MG1 and MG2). FIG. 25D is a schematic view showing the relative locations of the six resonators within the monolithic implementation of the optimized T ladder network.

Similar implementations made be constructed for generalized pi and L ladder networks.

Having illustrated and described the principles of the invention in several preferred embodiments, it should be apparent to those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. For example, these principles are readily applied to discrete implementations of piezoelectric-based resonator networks as well as monolithic implementations. I therefore claim all modifications coming within the spirit and scope of the following claims.