Packet Switching System

1. Field of the Invention

The present invention relates generally to a packet switching system. More specifically, the invention relates to a packet switching technology in a digital communication network employing a packet.

2. Description of the Related Art

High attention has been attracted for a high speed packet switching system for transmitting and exchanging information at ultra-high speed by transforming all information, such as voice, data, image and so forth in packets and employing simplified protocol. In such high speed packet switching system, a large scale packet switching system for more than several hundreds of channels is realized by connecting middle or small scale packet switches in a plurality of stages.

In such case, there is a system, in which the first stage packet switch does not perform a path selection for the input packet and the input packet is uniformly supplied to subsequent stages of packet switch regardless of its address information and path selection is performed in the subsequent stages of packet switch for simplification of a path selection control

and for preventing an internal blocking (which means a condition wherein a call cannot be connected due to blocking of an internal link despite of presence of vacant capacity of incoming channel and outgoing channel).

In this system, since each of packets of the same call passes different paths and thus it causes different delay time of respective packets having passed different paths, the order of the packet in the same call has an irregular sequence. A solution for this problem has been disclosed in a paper entitled "A Study on Control Algorithm for Large Scale ATM Switch" in The Institute of Electronics, Information and Communication Engineers Technical Study Report, Switching System Engineering--SSE 89-173, 1989.

The conventional system will be discussed hereinafter with reference to FIG. 9. FIG. 9 shows the block diagram of the conventional system. In the above-identified literature, the switching system is constituted of three stages of switches, as shown in FIG. 9. Each of the input ports 7.sub.11 -7.sub.88 are provided for each of the first stage switches and each of the eight output ports 9.sub.11 -9.sub.88 are provided for each of the third stage switches.

Time stamping circuits 4.sub.11 -4.sub.88 are provided for each of the input ports and packet buffer circuit 5.sub.11 -5.sub.88 are also provided for each of the output ports. The time stamping circuit provides a time stamp representing input time information for each of the packets input at an input port. Each of input packets is distributed to respective second stage switches 2.sub.1 -2.sub.8 by the first stage switch regardless of address information, and then switched to desired destination per packet by the second stage switches 2.sub.1 -2.sub.8 and third stage switches 3.sub.1 -3.sub.8. After having passed through switches, the packets are once stored in packet sorting circuits 5.sub.11 -5.sub.88 which are provided at outlets of the third stage of switches 3.sub.1 -3.sub.8. Those stored packet are output to output ports 9.sub.11 -9.sub.88 in accordance with the time information order of a period longer than a predetermined period of time (a possible maximum delay period required for passing through the first stage switches 1.sub.1 -1.sub.8 to the third stage switches 3.sub.1 -3.sub.8) and whereby each of the packets of the same cell is arranged in order.

In such packet switching system, the delay period of the packet is inherently increased since the packet buffer circuits provide delay the packet for a period longer than the predetermined period of time. In addition, it is inherently required to make judgement whether the delay period exceeds the predetermined period of time for respective packets for large amount of control which results in complicated hardware construction.

Therefore, it is an object of the present invention to provide a packet switching system which can suppress increasing of a delay period of the packet and is easy to control.

Another object of the invention is to provide the packet switching system which can simplify a hardware necessary for controlling the arrangement of the packets in order.

In order to accomplish the above-mentioned and other objects, a packet switching system, according to one aspect of the invention, comprises:

a plurality of incoming channels, through which packets arrive;

time information providing means for providing arrival time information for header information of respective packets;

copying means for copying respective of the arrival time information provided in header information of respective of packets;

arrival time information accumulating means for accumulating the copied arrival time information in an order of the arrival time;

packet accumulating means for accumulating the packet provided with the arrival time information in its header information in an order of the arrival time;

control means for outputting the packets accumulated in the packet accumulating means and having the arrival time information consistent with the arrival time information accumulated at the leading end of the arrival time information accumulating means;

first switching means for routing the packets output from the packet accumulating means according to destinations contained in the header information thereof; and

a plurality of outgoing channels for feeding out the routed packets.

In the preferred construction, the packet switching system further comprises second switching means for routing respective packets provided with the arrival time information depending upon the destinations contained in the header information thereof, and

each packet routed by the second switching means is supplied to the packet accumulating means corresponding to the route.

According to another aspect of the invention, a packet switching system includes a plurality of incoming channels, through which packets arrive, means for providing arrival time information for header information of respective packets, switching means for routing the packets output from the packet accumulating means according to destinations contained in the header information thereof, means for sorting the routed packets according to the order of arrival time information, and a plurality of outgoing channels for feeding out the packets sorted by the sorting means, the system comprises:

copying means for copying respective of the arrival time information provided in header information of respective of packets; and

means for transferring the arrival time information copied by the copying means to the sorting means,

the sorting means including:

means for accumulating the transferred arrival time information in an order of the arrival time;

means for outputting the packets having the arrival time information consistent with the arrival time information at the leading end of the accumulating mean.

In the preferred construction, the copying means includes means for counting the number of packets provided with the same arrival time information,

the transferring means includes means for transferring the counted number with the associated arrival time information,

the sorting means includes means for storing the counted number with establishing correspondence with the arrival time information and means for updating the number stored by subtracting one at every occurrence of feeding out of the packet having the header information containing the same arrival time information.

The present invention will be understood more fully from the detailed description given herebelow and from the accompanying drawings of the preferred embodiment of the invention, which, however, should not be taken to be limitative to the invention, but are for explanation and understanding only.

In the drawings:

FIG. 1 is a schematic block diagram of one embodiment of packet switching system according to the present invention;

FIG. 2 is a block diagram of a second stage switch in one embodiment of the packet switching system;

FIG. 3 is a block diagram of a third stage switch in one embodiment of the packet switching system;

FIG. 4 is an illustration showing the operation of one embodiment of the packet switching system according to the present invention;

FIG. 5 is an illustration showing the operation of one embodiment of the packet switching system according to the present invention;

FIG. 6 is a block diagram of a second stage switch in another embodiment of the packet switching system according to the present invention;

FIG. 7 is a block diagram of a third stage switch in another embodiment of the packet switching system according to the present invention;

FIG. 8 is an illustration showing the operation of another embodiment of the packet switching system according to the invention; and

FIG. 9 is a schematic block diagram of the conventional packet switching system.

The preferred embodiments of a packet switching system according to the present invention will be discussed hereinafter with deference to the accompanying drawings.

FIG. 1 shows the block diagram of one embodiment of a packet switching system in accordance with the present invention. In FIG. 1, there is provided 64 incoming channels 7.sub.11 -7.sub.88, through which packets arrive. For routing the packets, input through the incoming channels 7.sub.11 -7.sub.88, to respective destinations according to the header information of respective packets, crosslinked first stage switches 1.sub.1 -1.sub.8, second stage switches 2.sub.1 -2.sub.8 and third stage switches 3.sub.1 -3.sub.8 are provided in this order.

The first stage switches 1.sub.1 -1.sub.8 respectively comprise time stamping portions 14.sub.1 -14.sub.8 and packet distributing portions 6.sub.11 -6.sub.18. The time stamping portions provide arrival time information to the header information of respective input packets. Each packet distributing portion is a distributing switch to which input and output are connected in one-to-one relationship for varying state of connection.

The second stage switches 2.sub.1 -2.sub.8 comprise respectively address and time stamp detecting portions 8.sub.1 -8.sub.8 and packet switching portions 6.sub.21 -6.sub.28. The address/time stamp detecting portions detect the arrival time information contained in the header information of respective packets and copy the detected information. Each packet switching portion switches each of the packets without changing the order of arrival.

The third stage switch 3.sub.1 -3.sub.8 comprise packet sorting portions 15.sub.1 -15.sub.8 and packet switching portions 3.sub.1 -3.sub.8. The packet sorting portions arrange and store the arrival time information transferred from the second stage switches 2.sub.1 -2.sub.8 in the order of the arrival time. At this time, the packet sorting portions perform rearrangement of the received packets with reference to the arrival time information, and output the packet, whose arrival time information in the header coincides with the arrival time information stored in the leading end of the packet storing portion, to the third packet switching portion 6.sub.31.-6.sub.38. The packet switching portions 6.sub.31 -6.sub.38 have the same construction and function as those of the packet switching portions 6.sub.21 -6.sub.28.

Respective output packets of the third stage switch 3.sub.1 -3.sub.8 are fed to the outgoing channels 9.sub.11 -9 .sub.88.

Next, the operations of respective portions of the shown embodiment of the packet switching system according to the present invention will be discussed with reference to FIGS. 2-5. For facilitating understanding, the operations will be discussed separately for the first stage switch 1.sub.1, the second stage switch 2.sub.1 and the third stage switch 3.sub.1. FIG. 2 is a block diagram of the second stage switch 2.sub.1 of the shown embodiment of the packet switching system of the invention. FIG. 3 is a block diagram of the third stage switch 3.sub.1 of the shown embodiment of the invention. FIGS. 4 and 5 are illustrations showing operation of the shown embodiment of the packet switching system of the invention.

In the first stage switch 1.sub.1, the time stamp, arrival time information is provided for the header information of the packet input through the incoming channels 7.sub.11 -7.sub.18 by the time stamping portion 14.sub.1. In order to avoid collision of the packets, the packets are distributed to eight output routes by the packet distributing portions 6.sub.11 -6.sub.18 for outputting to the second stage switch 2.sub.1.

As shown in FIG. 2, in address and time stamp detecting circuits 18.sub.1 -18.sub.8 of the address and time stamp detecting portion 8.sub.1 of the second stage switch 2.sub.1, address and time stamp are copied from the header information of the input packet. The copied time stamp is transferred to one of the third stage switches 3.sub.1 -3.sub.8 which accommodates one of outgoing channels 9.sub.11 -9.sub.88 corresponding to the address by a time stamp feeding circuit 80.

On the other hand, when two or more time stamps of the same time are transferred to the same third stage switch 3.sub.1 -3.sub.8, they are transferred to the third stage switch 3.sub.1 -3.sub.8 as one.

The packet past through the address and time stamp detecting circuit 18.sub.1 -18.sub.8 is temporarily stored in packet buffer 64.sub.1 -64.sub.8 corresponding to the address in the header information which is detected by address filter 62.sub.1 -62.sub.8 via a time division multiplexing bus 60, and then output to respective third stage switches 3.sub.1 -3.sub.8. The packet buffers 64.sub.1 -64.sub.8 are adapted to output empty packets to the third stage switch 3.sub.1 -3.sub.8 when no packet is accumulated therein.

As shown in FIG. 3, in the third stage switch 3.sub.1, the time stamps transferred from the second stage switches 2.sub.1 -2.sub.8 are accumulated in a time stamp buffer 55 in the order of arrival. In case that two or more time stamps of the same time are transferred from the different second stage switches 2.sub.1 -2.sub.8, a time stamp detecting circuit 51 accumulates those time stamps as a single stamp in the time stamp buffer 55. Since these time stamps do not pass any intermediate buffer, they are accumulated in the time stamp buffer 55 while maintaining the order of input.

The packets transferred from the packet buffers 64.sub.1 -64.sub.8 of the second stage switches 2.sub.1 -2.sub.8 are accumulated in the packet sorting buffers 52.sub.1 -52.sub.8 in the third stage switch 3.sub.1. The packets accumulated in the packet sorting buffers 52.sub.1 -52.sub.8 are output to a multiplexing circuit 58 without destructing the order under the control of an empty packet detecting portions 50.sub.1 -50.sub.8,a buffer condition monitoring portion 54 and a time stamp comparing portion 56.

The empty packet detection portions 50.sub.1 -50.sub.8 are provided corresponding to respective inputs of the packet sorting buffers 52.sub.1 -52.sub.8 for detecting that the packets input from the second stage switches 2.sub.1 -2.sub.8 are empty packet to report to the buffer condition monitoring portion 54. Namely, each of the empty packet detecting portions 50.sub.1 to 50.sub.8 detects the fact that no packet transferred from the packet buffers 64.sub.1 -64.sub.8 of the second stage switch is present.

The packet condition monitoring portion 54 monitors the packet accumulating condition of respective buffers 52.sub.1 -52.sub.8 to output a comparison enabling signal to a time stamp comparing portion 56 according to the packet accumulating condition and the result of detection by the empty packet detecting portions 50.sub.1 -50.sub.8.

In practice, the buffer condition monitoring portion 54 outputs the comparison enabling signal to the comparing portion 56 when the fact that no packet is present in the second stage switch corresponding to the empty packet sorting buffer is detected by the empty packet detecting portions 50.sub.1 -50.sub.8. Also, when packets are full in all packet sorting buffers 52.sub.1 -52.sub.8, the buffer condition monitoring portion 54 outputs the comparison enabling signal to the time stamp comparing portion 56.

In response to the comparison enabling signal, the time stamp comparing portion 56 compares the time of the leading time stamp among those accumulated in the time stamp buffer 55 and the time of the time stamp given for the leading packet of the packet sorting buffers 52.sub.1 -52.sub.8 to perform control for feeding the packet, time stamp of which matches with that of the leading time stamp in the time stamp buffer 55, to the multiplexing circuit 58.

With the control set forth above, it becomes possible to avoid a packet, which has not arrived yet to the 3rd stage switch, for any reason, and this packet is not joined in the packet sorting procedure.

When all packets provided with the time stamps consistent with the time of the leading time stamp of the time stamp buffer 55 are fed out from the packet sorting buffer, the leading time stamp of the time stamp buffer 55 is disposed and the next time stamp is shifted up to be the leading time stamp. With the similar procedure for the shifted new leading time stamp, the packets are transferred to the multiplexing circuit 58. The output of the multiplexing circuit 58 is input to the packet switching portion 6.sub.31.

In the packet switching portion 6.sub.31, the packets are distributed depending on destinations by the address filters 62.sub.1 -62.sub.8 and then accumulated in the packet buffers 64.sub.1 -64.sub.8. The packets accumulated in the packet buffers 64.sub.1 -64.sub.8 are fed out to the outgoing channels 9.sub.11 -9.sub.18.

The operation of the third stage switch 3.sub.1 is illustrated for better understanding in FIGS. 4 and 5. As shown in FIG. 4, the time of the leading time stamp of the time stamp buffer 55 is 4, and the time stamp provided for the leading packet of the packet sorting buffer 52.sub.1 is also 4. Accordingly, the packet provided the time stamp 4 is output to the multiplexing circuit 58.

As shown in FIG. 5, the packet having the time stamp consistent with the time 4 of the time stamp of the leading time stamp in the time stamp buffer 55, is not present any more in the packet sorting buffer 52.sub.1 -52.sub.8. Therefore, the time stamp having the time 4 is disposed.

Next, the second embodiment of the packet switching system according to the present invention will be discussed with reference to FIGS. 6-8. FIG. 6 is a block diagram of the second stage switch 2.sub.1 in the second embodiment of the invention. FIG. 7 is a block diagram of the third stage switch 3.sub.1 in the second embodiment of the invention. FIG. 8 is an illustration showing the operation of the second embodiment of the packet switching system according to the invention.

As shown in FIG. 6, in the second stage switch 2.sub.1, the packets transferred from the first stage switches 1.sub.1 -1.sub.8 are accumulated in the packet buffers 64.sub.1 -64.sub.8 with distribution by the address filters 62.sub.1 -62.sub.8 via the time division multiplexing bus 60. At this time, the time stamps provided in the header information of the packets are copied by the address and time stamp detecting portion 8.sub.1. By packet number computing circuits 82.sub.1 -82.sub.8 provided in the address and time stamp detecting portion 8.sub.1 corresponding to the packet buffers 64.sub.1 -64.sub.8, the time stamps are copied from the header information of the packets. At this time, the packet number computing circuits 82.sub.1 -82.sub.8 counts the number of time stamps of the same time. The time information of the time stamps and the number information of the time stamps having the same time are transferred to the third stage switches 3.sub.1 -3.sub.8.

As shown in FIG. 7, in the third stage switch 3.sub.1, the time stamp comparing circuit 56 compares the time of the time stamps of the leading packets in the packets accumulated in the packet sorting buffer 52.sub.1 -52.sub.8 and the time of the time stamp accumulated in the time stamp buffer 55. Number of the leading time stamp of the time stamps of the time stamp buffer 55 is accumulated in the packet number buffer 59 corresponding to the leading time stamp.

When the consistent time stamp is present, such packets are fed out from the packet sorting buffer 52.sub.1 -52 .sub.8. Then, the number of the fed out packets is decremented from the value in the packet number buffer 59 by a packet decrementing circuit 57. When the number of the leading time stamps accumulated at the leading portions becomes "0", the leading time stamp of the time stamp buffer 55 is disposed. Then, the next time stamp is shifted to be the leading time stamp for repeating the operation set forth above.

On the other hand, the packet sorting buffers 52.sub.1 -52.sub.8 send a notice to the second stage switch 2.sub.1 to stop outputting the packet when the packet sorting buffers 52.sub.1 -52.sub.8 have no vacancy.

As shown in FIG. 8, when the number of time stamps accumulated at the leading portion of the packet number buffer 59 becomes "0", the leading time stamp of the time stamp buffer 55 is disposed. Simultaneously, the leading data of the packet number buffer 59 is also disposed.

In the above-mentioned second embodiment, by providing the packet number buffer 59, the packet sorting portion 15.sub.1 can detect the number of packets having the time stamps of the same arrival time. By this, it becomes possible to avoid the exclusion a packet, which has the not yet arrived from packet sorting procedure even when packet sorting procedure is initiated before all packets arrive. Therefore, further higher speed packet switching system than the former, first embodiment can be realized.

It should be noted that as the packet buffers 64.sub.1 -64.sub.8, the packet sorting buffers 52.sub.1 -52.sub.8 and the time stamp buffer 55, FIFO (First in First out memory) is preferably employed so that read control can be simplified.

As set forth above, according to the present invention, the internal blocking can be avoided by eliminating necessity of preliminary routing and a period required for sorting the packet can be shortened. In addition, the control necessary for sorting the packet can be simplified.

Although the invention has been illustrated and described with respect to exemplary embodiments thereof, it should be understood by those skilled in the art that the foregoing and various other changes, omissions and additions may be made therein and thereto, without departing from the spirit and scope of the present invention. Therefore, the present invention should not be understood as limited to the specific embodiment set out above but to include all possible embodiments which can be embodies within a scope encompassed and equivalents thereof with respect to the feature set out in the appended claims.