Liquid Crystal Display Device With TFTS in Which Pixel Electrodes Are Formed in the Same Plane as the Gate Electrodes With Anodized Oxide Films Before the Deposition of Silicon

1. Field of the Invention

This invention relates to a liquid crystal display device and a method for manufacturing a liquid crystal display device, particularly a liquid crystal display device of an active matrix type using thin film transistors, or the like.

2. Description of the Prior Arts

In a liquid crystal display device of an active matrix type, non-linear devices (switching devices) are disposed in such a manner as to correspond to a plurality of pixel electrodes arranged in matrix, respectively. The liquid crystal in each pixel is always driven, in principle, i.e., it has a duty ratio of 1.0. In comparison with a so-called "simple matrix type" which employs a time division driving system, therefore, the active system has better contrast and has become an indispensable technique particularly in a color liquid crystal display device. A typical example of the switching devices is a thin film transistor (TFT).

FIG. 17 is a sectional view showing part of a conventional active matrix type liquid crystal display device. In this liquid crystal display device, a gate electrode GT is disposed on a transparent glass substrate SUB1, an insulating film GI used as a gate insulating film is disposed on the gate electrode GT, an i-type semiconductor layer AS is disposed on the insulating film GI, a video signal line DL is disposed on the insulating film GI, a source electrode SD11 and a drain electrode SD21 are disposed on both sides of the i-type semiconductor layer AS and a transparent pixel electrode ITO11 is disposed and connected with the source electrode SD11.

FIG. 18 is a sectional view showing part of another conventional active matrix type liquid crystal display device, such as described in the Proceedings of the SID, Vol. 31/1, 1990, pp 13-17. In this liquid crystal display device, a gate electrode GT is disposed on a transparent glass substrate SUB1, an insulating film GI1 consisting of a silicon nitride film is disposed on the gate electrode GT, a transparent pixel electrode ITO12 is disposed on the insulating film GI1, an insulating film GI2 consisting of a silicon nitride film is disposed on the transparent pixel electrode ITO12, an i-type semiconductor layer AS is disposed on the insulating film GI12, a video signal line DL is disposed on the insulating film GI12, a source electrode SD11 and a drain electrode SD21 are disposed on both sides of the i-type semiconductor layer AS, and the source electrode SD11 and the transparent pixel electrode ITO12 are connected through a through hole bored in the insulating film GI2.

In the liquid crystal display device shown in FIG. 17, the video signal line DL and the transparent pixel electrode ITO11 are formed on the same plane. Accordingly, the video signal line DL and the transparent pixel electrode ITO11 adjacent to each other undergo short-circuit and invite point defects and deterioration of display performance.

In the liquid crystal display device shown in FIG. 18, the video signal line DL and the transparent pixel electrode ITO12 are not formed on the same plane. Accordingly, the video signal line DL and the transparent pixel electrode ITO12 hardly short-circuit. However, two layers of insulating films GI1 and GI2 are disposed and if these insulating films GI1, GI2 are formed by a plasma CVD process, generation of dust due to the plasma reaction is extremely great inside a plasma CVD apparatus, so that defects are likely to occur in the insulating films GI1, GI2. For example, short circuits occur between the gate electrode GT and the source and drain electrodes SD11, SD21. Therefore, point defects occur and display performance deteriorates.

In order to solve the problems described above, the present invention is directed to provide a liquid crystal display device having excellent display performance.

In a liquid crystal display device of an active matrix system using a thin film transistor and a pixel electrode as constituent elements of a pixel (or picture cell), the object of the invention described above can be accomplished by effecting a first insulating film (formed as an anodized oxide film of a metal constituting a gate electrode of the thin film transistor) and a second, different insulating film used as a gate insulating film of the thin film transistor formed between the pixel electrode and a video signal line.

In this case, the gate insulating film of the thin film transistor may be constituted by the first insulating film and the second insulating film.

The pixel electrode described above may be formed on the same plane as the gate electrode.

Furthermore, in a liquid crystal display device of an active matrix system using a thin film transistor and a pixel electrode as constituent element of a pixel, the liquid crystal display device of the invention is characterized in that a third insulating film used as the gate insulating film of the thin film transistor described above is formed between the pixel electrode and a video signal line, and the third insulating film on the pixel electrode is removed substantially.

In a liquid crystal display device of an active matrix system using a thin film transistor and a pixel electrode as constituent elements of a pixel, the liquid crystal display device of the invention is characterized in that an isolated pattern consisting of a silicon film is formed on at least part of the peripheral portion of a hole bored in a fourth insulating film used as a gate insulating film of the thin film transistor described above and consisting of a silicon nitride film.

In the liquid crystal display device of the present invention, the second insulating film is formed between the pixel electrode and the video signal line to avoid a short circuit between them.

If the gate insulating film of the thin film transistor is constituted by the first insulating film and the second insulating film described above, the short-circuit between electrodes at the thin film transistor portion can be prevented.

Furthermore, if the pixel electrode is formed on the same plane as the gate electrode, the number of insulating films can be reduced.

In the liquid crystal display device of the present invention, the third insulating film used as the gate insulating film of the thin film transistor is formed between the pixel electrode and the video signal line. Accordingly, the pixel electrode and the video signal line do not short-circuit. Since the third insulating film on the pixel electrode is removed substantially, the total film thickness of the insulating films formed on the pixel electrode becomes smaller.

Furthermore, in the liquid crystal display device of the present invention, the isolated pattern consisting of the silicon film is formed on at least part of the periphery of the hole bored in the fourth insulating film used as the gate insulating film of the thin film transistor and consisting of the silicon nitride film. Accordingly, the edge surface of the hole becomes a slope surface.

FIG. 1 is a top plan view showing an essential portion of one pixel of the liquid crystal display of the color liquid crystal display circuit of active matrix type, to which the present invention is to be applied.

FIG. 2A is a section taken along line IIA--IIA of FIG. 1 and showing a peripheral portion of the seal portion.

FIG. 2B is a section taken along line IIB--IIB of FIG. 1.

FIG. 2C is a sectional view illustrating a portion of a gate terminal of the liquid crystal display device shown in FIG. 1.

FIG. 3 is a top plan view showing an essential portion of a liquid crystal display circuit arranged with a plurality of pixels shown in FIG. 1.

FIGS. 4 to 6 are top plan views showing certain-level layers of the pixels shown in FIG. 1.

FIG. 7 is a top plan view showing an essential portion of only the pixel electrode layer, the light-shielding layer and the color filter layer shown in FIG. 3.

FIG. 8 is an equivalent circuit diagram showing a display unit of the active matrix color liquid crystal display device.

FIG. 9 is an equivalent circuit diagram of the pixels shown in FIG. 1.

FIG. 10 is a diagram showing the relation between the film thickness of an insulating film and anodized oxide film and an increasing ratio of a mutual conductance gm.

FIG. 11 is a diagram showing current characteristics of the anodized oxide film.

FIG. 12 is an explanatory view of a production method of the liquid crystal display device shown in FIG. 1.

FIG. 13 is a diagram showing the relation between a heat-treating temperature and a leakage current.

FIG. 14 is a sectional view showing part of a liquid crystal display portion of an active matrix type liquid crystal display device of another embodiment of the present invention.

FIG. 15 is a plan view showing the principal portions of one pixel of a liquid crystal display portion of an active matrix type color liquid crystal display device of still another embodiment of the present invention;

FIG. 16 is a sectional view taken along line XVI--XVI of FIG. 15.

FIGS. 17 and 18 are sectional views, each showing part of a conventional liquid crystal display device.

FIG. 19A is a plan view showing still another embodiment of the present invention.

FIG. 19B is a sectional view of an additional capacitor Cadd along line 19B--19B of FIG. 19A.

A detailed description of the present invention in consideration of embodiments of a color liquid crystal display circuit of active matrix type will now be given.

Incidentally, the parts having identical functions are designated at identical reference characters throughout all the Figures relating to the embodiments, and their repeated descriptions will be omitted.

FIG. 1 is a top plan view showing one embodiment of one pixel and its peripheral portion of the active matrix type color liquid crystal display circuit to which the present invention is to be applied. FIG. 2A is a section taken along line IIA--IIA of FIG. 1 and shows the embodiment and the vicinity of the sealing portion of the display panel. FIG. 2B is a section taken along IIB--IIB of FIG. 1 and shows the embodiment. On the other hand, FIG. 3 (showing an essential portion) is a top plan view showing one embodiment in the case in which a number of pixels shown in FIG. 1 are arranged.

As shown in FIG. 1, each pixel is arranged in a cross region (defined by four signal lines, i.e., two operation signal lines and two video signal lines) between two adjacent operation signal lines (e.g., gate signal lines or horizontal signal lines) GL and two video signal lines (e.g., drain signal lines or vertical signal lines) DL. Each pixel includes a thin film transistor TFT, a pixel electrode ITO1 and an additional capacitor Cadd. The scanning signal lines GL are extended in the row direction and arranged in plurality in the column direction. The video signal lines DL are extended in the column direction and arranged in plurality in the row direction.

As shown in FIG. 2A, the thin film transistor TFT and the transparent pixel electrode ITO1 are formed at the side (or inner surface) of a lower transparent glass substrate SUB1 across a liquid crystal layer LC, and a color film FIL and a black matrix pattern BM for light shielding are formed at the side (or inner surface) of an upper transparent glass substrate SUB2. The side of the lower transparent glass substrate SUB1 is made to have a thickness of about 1.1 (mm), for example.

On the both surfaces of each of transparent glass substrate SUB1 and SUB2 are formed silicon oxide layers SIO deposited by dip treatment. Accordingly, even if there exist sharp defects at the surfaces of the transparent glass substrates SUB1 and SUB2, the scanning signal lines GL as well as the color filter FIL are protected from defects since the defects are covered by the silicon oxide layer SIO.

FIG. 2A presents a section of one pixel portion at its center and a section of the portion, i.e., the lefthand side edges of the transparent glass substrates SUB1 and SUB2, in which the external leading-out wires are present, at its lefthand side. The righthand side presents a section of a portion, i.e., the righthand side edges of the transparent glass substrates SUB1 and SUB2, in which the leading-out wires are absent.

Sealing members SL, as indicated at the lefthand and righthand sides of FIG. 2A, are made to seal up the liquid crystal LC and are formed along the whole edges of the transparent glass substrates SUB1 and SUB2 excepting the liquid crystal sealing port (although not shown). The sealing members SL are made of an epoxy resin, for example.

A common transparent pixel electrode ITO2 at the inner surface of the aforementioned upper transparent glass substrate SUB2 has at least one portion thereof connected with the external leading-out wire, which is formed at the inner surface of the lower transparent glass substrate SUB1, by means of silver paste SIL. This leading-out wire is formed at the fabrication step shared with the aforementioned gate electrode GT, source electrode SD1 and drain electrode SD2.

The individual layers of alignment films ORI1 and ORI2, transparent pixel electrode ITO1, common transparent pixel electrode ITO2, passivation films PSV1 and PSV2 and insulating film GI are formed inside of the sealing member SL. Polarizers POL1 and POL2 are formed on the individual outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2.

A liquid crystal LC is filled between the lower alignment film ORI1 and upper alignment film ORI2 for setting the orientations of the liquid crystal molecules and is sealed with the sealing member SL.

The lower alignment film ORI1 is formed over the passivation film PSV1 at the side (or inner surface) of the lower transparent glass substrate SUB1.

On the inner surface (at the liquid crystal side) of the upper transparent glass substrate SUB2, through the silicon oxide layer SIO, there are sequentially laminated a light shielding film BM, a color filter FIL, a passivation film PSV2, a common transparent pixel electrode (COM) ITO2 and an upper alignment film ORI2.

This liquid crystal display circuit is assembled by forming the individual layers at the inner surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, by subsequently superposing the upper and lower transparent glass substrates SUB1 and SUB2 and by filling the liquid crystal LC between the two.

If a positive bias is applied to the gate electrode GT, the thin film transistor TFT has its channel resistance reduced between its source and drain. If the bias is reduced to zero, the thin film transistor TFT operates to have its channel resistance increased.

The thin film transistor TFT of each pixel is divided into two (or plurality) in the pixel so that it is composed of thin film transistors (or divided thin film transistors) TFT1 and TFT2. These thin film transistors TFT1 and TFT2 are individually made to have a substantially equal size (in the channel length and width). Each of these divided thin film transistors TFT1 and TFT2 is composed mainly of a gate electrode GT, a gate insulating film GI, an i-type (i.e., intrinsic type not doped with a conductivity type determining impurity) amorphous Si semiconductor layer AS, and a pair of source electrode SD1 and drain electrode SD2. Incidentally, the source and drain are intrinsically determined in dependence upon the bias polarity inbetween, and this polarity is inverted during the operation in the circuit of the present display circuit. Thus, it should be understood that the source and drain are interchanged during the operation. In the following description, however, one is fixed as the source whereas the other is fixed as the drain, for convenience only.

The gate electrode GT is formed to project perpendicularly (i.e., upward, as viewed in FIGS. 1 and 4) from the scanning signal lines GL (or branched in the "T-shape"), as shown in detail in FIG. 4 (presenting a top plan view showing the layer g2 and AS of FIG. 1 only). The gate electrode GT is extended to the regions to be individually formed with the thin film transistors TFT1 and TFT2. These thin film transistors TFT1 and TFT2 have their individual gate electrodes GT integrated (as their common gate electrode) to merge into the scanning signal line GL. The gate electrode GT is constituted by a single level conductive layer g2. The conductive layer g2 is formed, for example, by sputtering aluminum in the thickness of about 1,000 to 5,500 angstroms. On the gate electrode GT an anodized oxide film of aluminum AOF is provided.

This gate electrode GT is made so slightly large as to cover the semiconductor layer AS completely (as viewed upward), as shown in FIGS. 1 and 2A and FIG. 4. In case, therefore, a back light BL such as a fluorescent lamp is attached to the bottom of the substrate SUB1, this opaque aluminum gate electrode GT establishes a shadow to shield the semiconductor layer AS from the back light, thus substantially eliminating the conducting phenomenon due to the optical irradiation, i.e., the deterioration of the OF characteristics of the TFTs. Here, the intrinsic size of the gate electrode GT is given the least necessary width (including the positioning allowance of the gate electrode of the source/drain electrodes) for extending between the source/drain electrodes SD1 and SD2. The depth for determining the channel width W is determined in dependence upon the factor W/L determining the mutual conductance gm, i.e., the ratio to the distance (i.e., the channel length) L between the source/drain electrodes.

The size of the gate electrode in the present embodiment is naturally made larger than the aforementioned intrinsic size.

The aforementioned scanning signal line GL is constituted by the second-level conductive film g2. The second-level conductive film g2 of the scanning signal line GL is formed at the same step and integrally with the second-level conductive film g2 of the aforementioned gate electrode GT.

An anodized oxide film (Al.sub.2 O.sub.3) AOF is formed by anodizing the second conductive film g2. This anodized oxide film AOF is formed at a crossover portion of the scanning signal line GL with the video signal line DL, at the gate electrode portion GT and at the electrode portion PL1. Therefore, no short circuit occurs between the electrodes at the thin film transistor portion TFT or between the signal lines at the wiring crossover portion. Moreover, since the anodized oxide film AOF is disposed only at part of the scanning signal line GL, the wiring resistance of the scanning signal line GL can be limited to a low level. Furthermore, the dielectric constant of Al.sub.2 O.sub.3 is 9.2 and the dielectric constant of silicon nitride is 6.7. Since the dielectric constant of Al.sub.2 O.sub.3 is about 30% higher than that of silicon nitride, the mutual conductance of the thin film transistor TFT can be improved by about 1.5 times. Moreover, since the area of the additional capacitor Cadd can be reduced, an open ratio can be improved. Unlike the prior art structure in which two layers of insulating films GI1, GI2 consisting of the silicon nitride film are disposed, the present invention does not need additionally expensive CVD apparatuses and hence, the production cost does not become higher.

The insulating film GI is used as the individual gate insulating films of the thin film transistors TFT1 and TFT2. The insulating film GI is formed over the gate electrode GT and the scanning signal line GL and the transparent pixel electrode ITO1. The insulating film GI is formed of, for example, a silicon nitride film prepared by the plasma CVD.

Next, the film thickness of the insulating film GI and that of the anodized oxide film AOF will be explained. FIG. 10 is a diagram showing the relation between the film thickness of the insulating film GI and that of the anodized film AOF with an increasing ratio of the mutual conductance gm when the gate insulating film is composed of the anodized oxide film AOF and the insulating film GI and when the mutual conductance gm of an ordinary insulating film GI (which is 0.3 .mu.m thick) is 1. If the film thickness of the insulating film Gi and the film thickness of the anodized oxide film AOF are determined so that the relation falls within the range represented by oblique lines in the diagram, the mutual conductance gm can be improved. Under a practical operation condition, on the other hand, a maximum 25 V voltage is applied between the gate electrode GT and the source electrode SD1 and between the gate electrode GT and the drain electrode SD2, and screening of 75 V, which is thrice this voltage, is effected. Since it is necessary to consider that there exist the portions which do not have the insulating film GI and the portions which do not have the anodized oxide film AOF, the film thickness of each of the insulating film GI and the anodized oxide film must be sufficient to withstand the 75 V voltage. The film thickness of the insulating film GI capable of withstanding the 75 V voltage is 1,200 .ANG. (angstrom units) and the film thickness of the anodized oxide film AOF capable of withstanding this 75 V voltage is 1,100 .ANG., and this corresponds to the anodizing voltage of 80 V. FIG. 11 is a diagram showing the leakage current characteristics of the anodized oxide film AOF. Since the OFF current of the thin film transistor TFT is about 10.sup.-8 A/cm.sup.2, the leakage current must be below 10.sup.-8 A/cm.sup.2. It is when the anodizing voltage is 80 V or above that the leakage current is below 10.sup.-8 A/cm.sup.2. From these aspects, too, the film thickness of the anodized oxide film AOF must be at least 1,100 .ANG.. On the other hand, when the anodizing voltage exceeds the withstand voltage of the resist at the time of anodization, the resist undergoes breakdown and the second conductive film g2 below the resist disappears. Therefore, it is not appropriate to raise the anodizing voltage, and it is preferred to set the anodizing voltage to 150 V or below (at which the film thickness of the anodized oxide film AOF is about 2,100 .ANG.). It is preferred from the explanation given above that the film thickness of the gate insulating film GI be from 1,200 to 2,200 .ANG. and the film thickness of the anodized oxide film AOF be from 1,100 to 2,100 .ANG., or in other words, both of their film thickness be the values within the range of the grid mesh shown in FIG. 10.

The i-type semiconductor layer AS is used as the individual channel forming regions of the thin film transistors TFT1 and TFT2 is divided into a plurality of parts, as shown in FIG. 4. The i-type semiconductor layer AS is formed of an amorphous silicon film or polycrystalline silicon film to have a thickness of about 1,800 angstroms.

This i-type semiconductor layer AS is formed subsequent to the formation of the Si.sub.3 N.sub.4 gate insulating film GI by changing the components of supply gases but by using the common plasma CVD system such that it is not exposed from the system to the outside. On the other hand, an N.sup.+ -type layer d0 (shown in FIG. 2A) doped with P for the ohmic contact is likewise formed subsequently to have a thickness of about 200 TO 500 .ANG.. After this, the lower substrate SUB1 is taken out of the CVD system, and the N.sup.+ -type layer d0 and the i-type AS are patterned into independent islands by the photographic technology, as shown in FIGS. 1 and 2A.

The i-type semiconductor layer AS is also formed between the intersecting portions (or crossover portions) of the scanning signal line GL and the video signal line DL, as shown in detail in FIG. 1 and FIG. 4. This crossover i-type semiconductor layer AS is formed to reduce the short-circuiting between the scanning signal line GL and the video signal line DL at the intersecting portion.

The individual source electrodes SD1 and drain electrodes SD2 of the divided thin film transistors TFT1 and TFT2 are formed over the semiconductor layer AS and separately from each other, as shown in detail in FIGS. 1 and 2A and in FIG. 5 (presenting a top plan view showing the layers d1 to d3 of FIG. 1 only).

Each of the source electrode SD1 and the drain electrode SD2 is formed by overlaying a second conductive film d2 and a third conductive film d3 sequentially from the lower side contacting with the N.sup.+ -type semiconductor layer d0. These second conductive film d2 and third conductive film d3 of the source electrode SD1 are formed at the same fabrication step as those of the drain electrode SD2.

The second conductive film d2 is formed of a sputtered chromium film to have a thickness of 500 to 1,000 .ANG. (e.g., about 600 .ANG. in the present embodiment). The chromium film is formed to have a thickness no more than 2,000 .ANG. because it establishes a high stress if it is made excessively thick. The chromium film has an excellent contact with the N.sup.+ -type semiconductor layer d0. The chromium film constitutes so called barrier layer preventing aluminum of the third conducting film d3 described hereinafter from diffusing into the N.sup.+ type semiconductor layer d0. The second conductive film d2 may be made of not only the aforementioned chromium film but also a refractory metal (e.g., Mo, Ti, Ta or W) film or its silicide (e.g., MoSi.sub.2, TiSi.sub.2, TaSi.sub.2 or WSi.sub.2).

After the second conductive film d2 has been patterned with the photography, the N.sup.+ -type layer d0 is removed by using the same photographic mask or the second conductive film d2. Specifically, the N.sup.+ -type layer d0 left on the i-th layer AS is removed in self-alignment while leaving the second conductive film d2 as is. Since, at this time, the N.sup.+ -type layer d0 is etched to remove its whole thickness, the i-th layer AS is slightly etched off at its surface portion, but this removal may be controlled by the etching period.

After this, the third conductive film d3 is formed by sputtering or resistive-heating-evaporation aluminum to have a thickness of 3,000 to 8,000 .ANG. angstrom units (e.g., about 3,500 .ANG. in the present embodiment). The aluminum layer is less stressed than the chromium layer so that it can be formed to have larger thickness thereby to reduce the resistances of the source electrode SD1, the drain electrode SD2 and the video signal line DL.

Each of the second conductive film d2 of the source electrode SD1 and the second conductive film d2 of the drain electrode SD2 is internally (i.e., into the channel region) turned more deeply than the upper lying third conductive film d3. In other words, the second conductive films d2 in those portions is enabled to regulate (define) the channel length L of the thin film transistor TFT independently of the layer d3.

The source electrode SD1 is connected with the transparent pixel electrode ITO1, as has been described hereinbefore. The source electrode SD1 is formed along the stepped shape (i.e., the step corresponding to the sum of the thicknesses of the second conductive film d2, the N.sup.+ -type layer d0 and the i-type semiconductor layer AS) of the i-type semiconductor layer AS.

More specifically, the source electrode SD1 is composed of the second conductive film d2 formed along the stepped shape of the i-type semiconductor layer AS and the third conductive film d3 formed over the second conductive film d2.

This third conductive film d3 of the source electrode SD1 is formed to ride over the i-type semiconductor layer AS because the chromium film of the second conductive film d2 cannot be made so thick because of the increase in the stress as to ride over the stepped shape of the i-type semiconductor layer AS. In short, the second conductive film d2 is made thick to improve the step coverage. The third conductive film d3 can be made thick so that it can highly contribute to the reduction of the resistance of the source electrode SD1 (as well as those of the drain electrode SD2 and the video signal line DL).

The transparent pixel electrode ITO1 constitutes one of the parts of a pixel electrode of a liquid crystal display portion. The transparent pixel electrode ITO1 is connected with the source electrode SD1 through a through hole CNT formed in the insulating film GI.

The transparent pixel electrode ITO1 is constituted by the first conductive film d1. The transparent pixel electrode ITO1 is comprised of a transparent conductive film (Indium-Tin-Oxide, ITO, NESA film) formed by sputtering to have a thickness of about 1,000 to 2,000 .ANG. (e.g., in this embodiment about 1,200 .ANG.).

The transparent pixel electrode ITO1 is connected to the source electrode SD1 of the thin film transistor TFT1 and to the source electrode SD1 of the thin film transistor TFT2. If any defect occurs in one transistor TFT1, for example, the thin film transistor TFT1 is disconnected from the video signal line DL and the pixel electrode ITO1 by a laser beam, etc, during the manufacturing process. Accordingly, neither dot defect nor line defect occur and moreover, since the defect hardly occurs simultaneously in both of the two thin film transistors TFT1 and TFT2, the probability of the occurrence of the dot defect can be extremely reduced.

Moreover, since the transparent pixel electrode ITO1 is insulated from the gate electrode GT by the anodized oxide film AOF and also insulated from the video signal line D1 by the insulating film GI, the dot defects can be extremely reduced to obtain excellent display quality.

Furthermore, since the transparent pixel electrode ITO1 is formed in the same plane as the gate electrode GT, the number of insulating films can be reduced to make the manufacturing cost lower.

Over the thin film transistor TFT and the transparent pixel electrode ITO1, there is formed the passivation film PSV1, which is provided mainly for protecting the thin film transistor TFT against humidity or the like. Thus, the passivation film PSV1 to be used is highly transparent and humidity resistant. The passivation film PSV1 is formed of a silicon oxide film or silicon nitride film prepared by the plasma CVD, to have a thickness of about 1 micron.

The gate terminal GTM is constituted by the first conductive layer g1 and the first conductive layer d1 as shown in FIG. 2C.

The first-level conductive layer g1 is formed by, for example, sputtering chromium (Cr) in the thickness of about 1,000 angstroms.

At the inner surface side of the upper substrate SUB2, there is disposed the shielding film BM for shielding any external light (i.e., the light coming from the top of FIG. 2A) from entering the i-type semiconductor layer As to be used as the channel forming region, as hatched to have the pattern shown in FIG. 6. Here, FIG. 6 is a top plan view showing only the first conductive layer d1 comprised of the ITO film, the filter layer FIL and the shielding film BM of FIG. 1. The shielding film BM is formed of a film having a high shielding property to the light, e.g., an aluminum film or chromium film. In the present embodiment, the shielding film BM is formed of a chromium film by the sputtering, to have a thickness of about 1,300 .ANG..

As a result, the common semiconductor layer AS shared by the TFT1 and TFT2 is sandwiched between the upper shielding film BM and the lower but larger gate electrode GT so that it is shielded from the outside natural light or the back light. The shielding film BM is formed around the pixel, as hatched in FIG. 6. Specifically, the shielding film BM is formed in a lattice (of black matrix) shape, which defines the effective display region of one pixel. As a result, the contour of each pixel is clarified to improve the contrast by the shielding film BM. In other words, this shielding film BM has two functions, i.e., the shielding for the semiconductor layer AS and black matrix functions.

Further, since the portion of the transparent pixel electrode ITO1 (at the lower right hand portion in FIG. 1) opposite to the foot of the rubbing direction is shielded from light by the shielding film BM, even if domain is induced at the above portion, the display characteristics is hardly deteriorated because the domain is shaded.

Incidentally, the back light may be attached to the side of SUB2, whereas the SUB1 may be disposed at the observation side (exposed to the outside).

The common transparent pixel electrode ITO2 is opposed to the transparent pixel electrode ITO1, which is provided for each pixel at the side of the lower transparent glass substrate SUB1, so that the liquid crystal has its optical state varied in response to the potential difference (or electric field) between each pixel electrode ITO1 and the common pixel electrode ITO2. This common transparent pixel electrode ITO2 is fed with the common voltage Vcom. This common voltage Vcom is at an intermediate potential between a driving voltage Vdmin at the low level and a driving voltage Vdmax at the high level, both of which are applied to the video signal line DL.

The color filter FIL is prepared by cooling a dyeing base, which is made of a resin material such as an acrylic resin, with a dye. The color filter FIL is formed (as shown in FIG. 7) in the shape of stripe and in a position to face the pixel. (FIG. 7 shows the first conductive film d1, the black matrix layer BM and the color filter layer FIL of FIG. 3 only, and the B, G and R filters are hatched at 45 degrees and 135 degrees and in a cloth, respectively.)

The color filter FIL is made slightly large to cover the pixel electrode ITO1 in its entirety, as shown in FIG. 6. The shielding film BM is so formed inside of the peripheral edge of the pixel electrode ITO1 as to overlap the color filter FIL and the pixel electrode ITO1.

The color filter FIL can be formed in the following manner. First of all, the dyeing base is formed on the surface of the upper transparent glass substrate SUB2, and the dyeing base other than that in the red color filter forming region is removed by the photolithographic technology. After this, the dyeing base is dyed with the red dye and fixed to form the red filter R. Next, the green filter G and blue filter B are sequentially formed by the similar steps.

The passivation film PSV2 is provided for preventing the dyes for the different colors of the aforementioned color filter FIL from leaking into the liquid crystal LC. The passivation film PSV2 is made of a transparent resin material such as an acrylic resin or epoxy resin.

FIG. 8 shows an equivalent circuit diagram of the display matrix portion and a wiring diagram of its peripheral circuits. Though this drawing is a circuit diagram, it is depicted in such a manner as to correspond to a practical geometric arrangement Symbol AR represents a matrix array formed by disposing a plurality of pixels as a two-dimensional arrangement.

In the drawing, symbol X represents the video signal line, and suffixes G, G and R are corresponding to green, blue and red pixels, respectively. Symbol Y represents the scanning signal line GL and suffixes 1, 2, 3, . . . , end are put in accordance with the sequence of scanning timing.

The video signal line X (whose suffix is omitted) is alternately connected to the upper (or odd-numbered) video signal driving circuit He and to the lower (or even-numbered) video signal driving circuit Ho.

Symbol SUP represents a circuit which includes a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source and a circuit for converting data for CRT (cathode-ray tube) from a host (higher order operational processor) to data for the TFT liquid crystal display device.

The transparent pixel electrodes ITO1 is formed to overlap the adjoining scanning signal line GL at the end opposite to the end to be connected with the thin film transistor TFT. This superposition constitutes a latching capacitance element (or electrostatic capacitance element) Cadd which uses the transparent pixel electrode ITO1 as its one electrode PL1 and the adjoining scanning signal line GL as its other electrode PL2, as is apparent from FIG. 2B. This latching capacitance element Cadd has its dielectric films formed of the anodized oxide film AOF.

The latching capacitor Cadd is formed in the widened portion of the second-level conductive layer g2 of the gate line GL, as is apparent from FIG. 4. Here, the layer g2 at the portion intersecting the drain line DL is thinned to reduce the probability of the short-circuiting with the drain line.

(Equivalent Circuit of Additional Capacitor Cadd and its Operations)

The equivalent circuit of the pixel shown in FIG. 1 is shown in FIG. 9. In FIG. 9, letters Cgs designate a parasitic capacitor to be formed between the gate electrode GT and the source electrode SD1 of the thin film transistor TFT. The parasitic capacitor Cgs has its dielectric film made of the anodized oxide film AOF and the insulating film GI. Letters Cpix designate a liquid crystal capacitor to be formed between the transparent pixel electrode ITO1 (or PIX) and the common transparent pixel electrode ITO2 (or COM). The dielectric film of the liquid capacitor Cpix is formed of the liquid crystal LC, the insulating film GI, the passivation film PSV1 and the alignment films ORI1 and ORI2. Letters Vlc designate a midpoint potential.

The aforementioned latching capacitance element Cadd functions to reduce the influences of the gate potential variation "delta" Vg upon the center potential (e.g., the pixel electrode potential) Vlc when the TFT switches, as expressed by the following formula:

wherein "delta" Vlc designates the variation of the central potential due to "delta" Vg.

This variation "delta" Vlc causes the DC component to be added to the liquid crystal and can be reduced the more for the higher latching capacitor Cadd.

Moreover, the latching capacitor Cadd functions to elongate the discharge time and stores the video information for a long time after the TFT is turned off. The DC component to be applied to the liquid crystal LC can improve the lifetime of the liquid crystal LC, if reduced, to reduce the so-called "printing", by which the preceding image is left at the time of switching the liquid crystal display frame.

Since the gate electrode GT is enlarged to such an extent as to cover the semiconductor layer AS completely, as has been described hereinbefore, the overlapped area with the source/drain electrodes SD1 and SD2 is increased to cause an adverse effect that the parasitic capacitance Cgs is increased to make the center potential Vlc liable to be influenced by the gate ((scanning) signal Vg. However, this disadvantage can be eliminated by providing the latching capacitor Cadd.

The latching capacity of the aforementioned latching capacitance element Cadd is set from the pixel writing characteristics to a level four to eight times as large as that of the liquid crystal capacitance Cpix (4 Cpix<Cadd<8 Cpix) and eight to thirty two times as large as that of the capacitance Cgs (8 Cgs<Cadd<32 Cgs).

The initial stage scanning signal line GL (i.e., Yo) to be used only as the capacitance electrode line is connected with the common transparent pixel electrode (Vcom) ITO2, as shown in FIG. 8. The common transparent pixel electrode ITO2 is connected with a leading-out line in the peripheral edge of the liquid crystal display circuit by means of a silver paste SL, as shown in FIG. 2A. Moreover, this leading-out line has its partial conductive layer (g1 or g2) prepared at the same step as that of the gate external terminals GTM and the scanning signal line GL. As a result, the final stage capacitance electrode line GL can be easily connected with the common transparent pixel electrode ITO2.

The first stage capacitor electrode line Yo may be connected to either the final stage scanning line Y.sub.end, a D.C. voltage potential (A.C. common potential) other than V.sub.com or the vertical scanning circuit V to receive an additional or redundant scanning pulse Yo.

Next, the method for manufacturing the liquid crystal display device as shown in FIG. 1 etc. will be explained. To begin with, a silicon dioxide film SIO is deposited by dip treatment on both surfaces of a lower transparent glass substrate SUB1 made of 7059 glass (trade name) and then baking is carried out at 500.degree. C. for 60 minutes.

Next, a first conductive film g1 consisting of a 1,100 angstrom-thick chrominum film is deposited on the lower transparent glass substrate SUB1 by sputtering. The first conductive film g1 is then etched selectively by photoetching using a ceric amonium nitrate solution as an etching solution, thereby forming a gate terminal GTM and a drain terminal DTM and forming also a power supply line ASL for anodization for connecting the gate terminal GTM and a pad PAD connected to the power supply line ASL for anodization, as shown in FIG. 12.

After the resist is removed by a peeling solution S502 (trade name), O.sub.2 asher is carried out for one minute. Next, a second conductive film g2 consisting of a 2,600 angstrom-thick film of aluminum is disposed by sputtering.

The second conductive film g2 is etched selectively by photoetching using a mixed acid solution of phosphoric acid, nitric acid and acetic acid as the etching solution, forming thereby the scanning signal line GL, the gate electrode GT and the electrode PL1 of a retention capacitance device Cadd. In this case, the overlapping portion between the second conductive film g2 with the first conductive film g1 is formed in a comb shape and the portion near the overlapping portion is shaped in a stripe form having a width of below 10 microns.

Next, an SF.sub.6 gas is introduced into a dry etching apparatus and after a residue such as silicon is removed, the resist is removed.

Next, after a 3 Microm thick resist is coated, the resist at the crossover portion between the scanning signal line GL and the video signal line DL, at the gate electrode portion GT and at the electrode portion PL1 is removed by a photoetching process. Next, the anodized oxide film AOF is formed by immersing the assembly into an anodizing solution prepared by neutralizing a 3% tartaric acid solution with ammonia, diluting the solution ten-fold with ethylene glycol or propylene glycol and adjusting the pH of the solution to 7.+-.0.5, and by applying an anodizing voltage to the pad PAD so as to anodize the second conductive film g2. In this case, the voltage is gradually raised from 0 to +120 V so that a current density is 0.5-10 mA/cm.sup.2 at the beginning (constant current anodization), and after the voltage reaches +120 V, it is kept at that value. Then, the second conductive film g2 which is about 1,100 .ANG. thick is oxidized in the course of about 30 minutes and an anodized oxide film AOF of about 1,700 .ANG. in thickness can be obtained. After the resist is removed, heating is carried out at 200.degree.-400.degree. C. for 60 minutes at the atmospheric pressure or in vacuum. The first conductive film d1 which consists of a 1,000 .ANG.-thick ITO film is the disposed by sputtering. The first conductive film d1 is selectively etched by a photoetching process using a mixed solution of hydrochloric acid and nitric acid as an etching solution, forming thereby the transparent pixel electrode ITO1 and the uppermost layer of the gate terminal GTM and drain terminal DRM.

Next, ammonia gas, silane gas and nitrogen gas are introduced into a plasma CVD apparatus and a silicon nitride film GI having a film thickness of 200 to 1,000 .ANG. is disposed. Silane gas and hydrogen gas are then introduced into the plasma CVD apparatus and an i-type amorphous silicon film AS having a film thickness of 2,100 .ANG. is disposed. Thereafter, hydrogen gas and phosphine gas are introduced and an N.sup.+ -type silicon film d0 having a film thickness of 200 to 500 .ANG. doped with phosphor of 0.6 to 2.5% is disposed.

The N.sup.+ -type silicon film d0 and the i-type amorphous silicon film AS are selectively etched by photoetching using SF.sub.6 and CCl.sub.4 as a dry etching gas, thereby forming an i-type semiconductor layer AS.

After the resist is removed, the silicon nitride film GI is selectively etched by photoetching using SF.sub.6 as the dry etching gas to form an insulating film GI and provide the through-hole CNT for connecting the source electrode SD1 and the transparent pixel electrode ITO1.

After the resist is removed, the second conductive film d2 consisting of a chrominum film having a thickness of 500 to 1,000 .ANG. is disposed by sputtering. Next, the second conductive film d2 is selectively etched by photoetching, forming thereby the video signal line DL, the source electrode SD1, the first layer of the drain electrode SD2 to also form the dielectric breakdown prevention line (not shown) for connecting the drain electrode DTM, and connected to the power supply line ASL for anodization shown in FIG. 12.

Before the resist is removed, CCl.sub.4 and SF.sub.6 are introduced into the dry etching apparatus and the N.sup.+ -type silicon film is selectively etched to form an N.sup.+ -type semiconductor layer d0. Then, after the resist is removed, O.sub.2 asher is carried out for one minute.

Next, the third conductive film d3 consisting of a 3,000 to 8,000 angstrom-thick film of aluminum is disposed by sputtering or resistive-heating evaporation.

Then, the third conductive film d3 is selectively etched by photoetching, forming thereby the video signal line DL, the source electrode SD1 and the second layer of the drain electrode SD2. Next, after the resist is removed, O.sub.2 asher is carried out for one minute.

After the resist is removed, ammonia gas, silane gas and nitrogen gas are introduced into the plasma CVD apparatus and a silicon nitride film having a film thickness of one micron is deposited. Next, the silicon nitride film is selectively etched by photoetching using SF.sub.6 as the dry etching gas to form the protective film PSV1.

In the production method of this liquid crystal device, the overlap portion between the second conductive film g2 and the first conductive film g1 is shaped in the comb form and the portion near the overlap portion is shaped in the form of stripes having a line width of up to 10 .mu.m. Accordingly, the occurrence of whiskers can be prevented. It has been found by experiments carried out by the present inventors that the whisker density is 4.9.times.10.sup.-6 pcs/cm.sup.2 when the line width of the aluminum film is 70 .mu.m, is 3.6.times.10.sup.-6 pcs/cm.sup.2 when the line width is 25 .mu.m and is 0 pc/cm.sup.2 when the line width is 10 .mu.m. Since heat-treatment is carried out at 200.degree.-400.degree. C. for 60 minutes after the anodized oxide film AOF is disposed, the leakage current of the anodized oxide film AOF can be reduced by the order of one digit as is obvious from FIG. 13, too. The heat-treating temperature is preferably below 400.degree. C. because the second conductive film g2 is likely to peel if the heat-treating temperature is higher than 400.degree. C.

FIG. 14 is a sectional view showing part of the liquid crystal display portion of the active matrix type color liquid crystal device in another embodiment of the invention. In this liquid crystal display device, an isolated pattern ISP consisting of an i-type amorphous silicon layer (AS) and an N.sup.+ -type silicon layer (d0) is formed around the periphery of the through-hole CNT bored in the insulating film GI consisting of the silicon nitride film. Therefore, the edge surface of the through-hole becomes a slope surface, so that the transparent pixel electrode ITO1 and the source electrode SD1 can be reliably connected through this through-hole.

The liquid crystal display device shown in FIG. 14 can be produced in the following way. First of all, the transparent pixel electrode ITO1 is formed and then, the silicon nitride layer (GI) is disposed. After the i-type amorphous silicon layer (AS) is disposed, the N.sup.+ -type silicon (d0) is disposed. Next, the N.sup.+ -type silicon layer (d0) and the i-type amorphous silicon layer (AS) are selectively etched, forming thereby the i-type semiconductor layer AS. The isolated pattern ISP having a dimension somewhat greater than the through-hole CNT is then formed. Next, the silicon nitride layer (GI) is selectively etched to provide the insulating film GI, and the through-hole CNT is formed, whereby the edge surface of the through-hole CNT becomes the slope surface.

FIG. 15 is a plan view showing the principal portions of one pixel of the liquid crystal display portion of another active matrix type color liquid display device in the present invention, and FIG. 16 is a sectional view taken along line XVI--XVI of FIG. 15. In this liquid crystal display device, a hole portion HOP is disposed in the insulating film GI, and the transparent pixel electrode ITO1 and the source electrode SD1 are connected through the end portion of this hole portion HOP. Since the insulating film GI on the transparent pixel electrode ITO1 is substantially eliminated by disposing the hole portion HOP, the film thickness of the insulating film formed on the transparent pixel electrode ITO1 becomes smaller, so that the voltage acting on the liquid crystal LC can be made greater. Moreover, the insulating film GI is formed between the transparent pixel electrode ITO1 and the video signal line DL and hence, the transparent pixel electrode ITO1 and the video signal line DL do not short-circuit. Accordingly, dot defects do not occur and display performance is excellent.

FIG. 19A is a plan view showing another embodiment of the present invention and FIG. 19B is a sectional view of an additional capacitor Cadd taken along line 19B--19B of FIG. 19A.

A great difference of this embodiment from the embodiments shown in FIGS. 2B and 15 is that the upper electrode PL2 of the additional capacitor Cadd is formed by layers d2 and d3 having the same level as the source drain electrodes SD1, SD2 and its dielectric is composed of the anodized oxide film AOF and the SiN insulating film GI.

In the embodiments described already, the dielectric of the additional capacitor Cadd is a single layer of the anodized oxide film AOF and has a relatively simple structure. Therefore, it has a merit that utilization efficiency of the planar area is high. On the other hand, the analysis carried out by the present inventors reveals that insulation defects occur more so in comparison with the insulating films formed by a CVD (Chemical Vapor Deposition) process and a thermal oxidation process. In this respect, since this embodiment uses the insulating film GI having high film quality, which is formed by the CVD process, as the dielectric of the capacitor, the embodiment has the effects of reducing the leakage current between the opposed electrodes and preventing the short-circuit.

One of the electrodes of this additional capacitor Cadd (PL2 in this embodiment) must be connected to the source electrode SD1 or to the transparent pixel electrode ITO1 from the aspect of the circuit function. In this embodiment, since the pattern is formed so that the conductive layer d2 and the transparent electrode layer d1 overlap inside the hole portion HOP of the afore-mentioned insulating film GI, the transparent pixel electrode ITO1 and the upper capacitance electrode PL2 are brought into mutual contact without increasing the number of the production steps and masks for photo-processing.

Although the invention completed by the present inventors has thus been described definitely with the embodiments thereof given above, the present invention is not particularly limited thereto but can of course be changed or modified in various ways without departing from the spirit thereof.

For example, in the embodiments given above, the scanning signal line GL and the gate electrode GT are constituted by the second conductive film g2 made of aluminum, but it is also possible to dispose an anodized oxide film of tantalum, etc, at the gate electrode GT portion by using a metal such as tantalum (Ta). In the embodiments given above, the transparent pixel electrode ITO1 is constituted by the first conductive film d1 consisting of the ITO film, but the pixel electrode may be constituted by a metal film in the case of a reflection type. Furthermore, the embodiments given above use the aluminum film as the second conductive film g2, but an aluminum film containing 1% or less silicon or palladium (Pd) can also be used. Though the embodiments given above use the aluminum film as the third conductive film d3, an aluminum film containing silicon or palladium can also be used. Though the additional capacitor Cadd is formed between the adjacent scanning signal lines GL in the embodiments given above, the additional capacitor need not be disposed. The additional capacitor may be formed between the scanning signal lines of the same stage.