Apparatus for and Method of Calculating Sum of Products

1. Field of the Invention

This invention relates to an apparatus for and a method of calculating a sum of products.

2. Description of the Related Art

In a digital filter of, for example, order p, products of p input data and p predetermined coefficients are successively added cumulatively. In other words, a sum of products of the p data and the p predetermined coefficients is calculated so that a desired filter output is outputted from the digital filter of order p.

In a conventional digital filter, when coefficients for calculation of a sum of products of data are processed in a fixed-point form, the accuracy of the coefficients is limited by a word length (bit number) handled in the apparatus. Accordingly, there is a subject that a round-off error takes place and consequently a desired filter output cannot be obtained.

It is one of possible solutions to the subject to increase the number of bits Which can be handled by the apparatus in order to reduce round-off errors. However, the solution still has a subject that the number of elements constituting the apparatus is increased and the power dissipation of the apparatus is increased.

Further, in a digital filter designed, for example, as a low-pass filter, since the absolute values of coefficients which are symmetrical with respect to a coefficient of order 0 generally decrease as the order number increases, when the number of bits which can be handled by the apparatus is increased, high order bits are not used with those coefficients which are high in order number, that is, those coefficients which are small in absolute value. Accordingly, the efficiency is low.

There is a method wherein coefficients are handled separately for an exponent part and a mantissa part, that is, in the floating point form. However, when products (products of data and coefficient) having comparatively small exponent parts are to be added cumulatively to products having comparatively large exponent parts, since the method truncates low bits of mantissa parts of the products having comparatively small exponent parts in order to make the sizes of the exponent parts of all of the products equal to one another, that is, to adjust the number of columns, it has a subject that it involves a number of round-off errors.

It is an object of the present invention to provide an apparatus for and a method of calculating a sum of products by which calculation of a sum of products can be performed with a high degree of accuracy.

In order to attain the object, according to an aspect of the present invention, there is provided an apparatus for calculating a sum of products, which comprises data storage means for storing data therein, coefficient storage means for storing coefficients therein, and cumulative adding means for calculating the products of the data stored in the data storage means and the coefficients stored in the coefficient storage means in order of magnitude of the exponent parts of the coefficients stored in the coefficient storage means and for cumulatively adding the products.

With the apparatus, data are stored into the storage means while coefficients are stored into the coefficient storage means. Then, the products of the data stored in the data storage means and the coefficients stored in the coefficient storage means are calculated in order of magnitude of the exponent parts of the coefficients stored in the coefficient storage means and then the products are added cumulatively by the cumulative adding means. Accordingly, even when the coefficients include, in a mixed condition, those coefficients which have large exponent parts and those coefficients which have small exponent parts, calculation of a sum of products can be achieved with a high degree of accuracy.

The cumulative adding means may calculate the products of the data stored in the data storage means and the coefficients stored in the coefficient storage means in reverse order of magnitude of the exponent parts of the coefficients stored in the coefficient storage means and cumulatively add the products. Thus, round-off errors which take place with coefficients having small exponent parts, that is, having small absolute values, can be reduced.

Preferably, the apparatus for calculating a sum of products further comprises coefficient read-out means for reading out the coefficients stored in the coefficient storage means in reverse order of the exponent parts of the coefficients. Since cumulative addition is thus performed in reverse order of magnitude of the exponent parts of the coefficients, round-off errors which take place with coefficients having small exponent parts, that is, having small absolute values, can be reduced.

Preferably, the apparatus for calculating a sum of products further comprises data read-out means for reading out the data stored in the data storage means in the order corresponding to the order in which the coefficients stored in the coefficient storage means are read out by the coefficient read-out means. Thus, cumulative addition of the products of desired coefficients and data can be performed.

The cumulative adding means may calculate the products of the data stored in the data storage means and the coefficients stored in the coefficient storage means in the order in which the exponent parts of the coefficients stored in the coefficient storage means increase monotonously and cumulatively add the products. Since the products of the coefficients and the data are cumulatively added substantially in the order in which the absolute value of the coefficient increases, cancelling of a coefficient having a small absolute value is prevented.

The cumulative adding means may calculate the products of the data stored in the data storage means and the coefficients stored in the coefficient storage means in the order in which the differences between adjacent ones of the exponent parts of the coefficients stored in the coefficient storage means exhibit the value of either 0 or 1 and cumulatively add the products. Since the products of the coefficients and the data are cumulatively added in the order in which the absolute values of the coefficients do not vary by a great amount, cancelling of a coefficient having a small absolute value is prevented.

The cumulative adding means may develop the coefficients stored in the coefficient storage means into the form of sums having an arbitrary number of terms in accordance with the magnitudes of the exponent parts of the coefficients, calculate the products of the sums and the data stored in the data storage means and cumulatively add the products. Since the absolute values of the coefficients developed into the form of sums are small and the difference between the maximum value and the minimum value of the absolute values of the coefficients is small, cancelling of a coefficient is prevented.

Preferably, the apparatus for calculating a sum of products further comprises bit shifting means for bit shifting the products cumulatively added by the cumulative adding means in accordance with the differences between the exponent parts of the coefficients stored in the coefficient storage means. Thus, the products calculated from the coefficients which are different in value of the exponent parts can be adjusted in column.

The coefficient storage means may store the differences between the exponent parts of the coefficients therein. The storage capacity of the coefficient storage means can be reduced comparing with the case wherein the exponent parts of the coefficients are stored in the coefficient storage means.

According to another aspect of the present invention, there is provided a method of calculating a sum of products, which comprises the steps of storing data, storing coefficients, and calculating the products between the data and the coefficients in order of magnitude of the exponent parts of the coefficients and cumulatively adding the products.

In the method, data are stored first and then coefficients are stored, whereafter the products of the data and the coefficients are calculated in order of magnitude of the exponent parts of the coefficients and then are cumulatively added. Accordingly, with the method, even when coefficients having large exponent parts and coefficients having small exponent parts are mixed in the coefficients, cumulative addition can be performed with a high degree of accuracy.

According to a further aspect of the present invention, there is provided an apparatus for calculating a sum of products, which comprises storage means for storing data therein, multiplying means for calculating the products of the data stored in the storage means and the mantissa parts of coefficients, cumulative adding means for cumulatively adding the products calculated by the multiplying means, and bit shifting means for bit shifting the products cumulatively added by the cumulative adding means in accordance with the differences between the exponent parts of the coefficients.

In the apparatus, data are stored into the storage means, and the products of the stored data and mantissa parts of coefficients, which may be represented in the floating point form, are calculated by the multiplying means. The products thus calculated are added cumulatively and then bit shifted in accordance with the differences between the exponent parts of the coefficients. Accordingly, with the apparatus, cancelling when the products calculated from the coefficients which are different in value of the exponent parts are to be adjusted in column can be minimized.

The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings in which like parts or elements are denoted by like reference characters.

FIG. 1 is a block diagram of a digital low-pass filter to which an apparatus for calculating a sum of products according to the present invention is applied showing a first preferred embodiment of the present invention;

FIG. 2 is a diagram showing an impulse response of the digital low-pass filter of FIG. 1;

FIG. 3 is a table showing the mantissa parts of coefficients and differences between exponent parts of the coefficients stored in a coefficient memory of the low-pass filter of FIG. 1;

FIG. 4 is a table illustrating a relationship between the input value and the output value of an exclusive OR circuit of the low-pass filter of FIG. 1;

FIG. 5 is a time chart illustrating operation of the low-pass filter of FIG. 1;

FIG. 6 is a table showing the mantissa parts of coefficients and differences between the exponent parts of the coefficients stored in the coefficient memory shown in FIG. 1;

FIG. 7 is a table illustrating adjustment of the mantissa parts of coefficients so that the exponent parts of the coefficients may increase monotonously;

FIG. 8 is a table illustrating calculation of a sum of products of data and coefficients in reverse order of magnitude of the exponent parts of the coefficients;

FIG. 9 is a block diagram of another digital low-pass filter to which an apparatus for calculating a sum of products according to the present invention is applied showing another preferred embodiment of the present invention;

FIG. 10 is a block diagram of a further digital low-pass filter to which an apparatus for calculating a sum of products according to the present invention is applied showing a further preferred embodiment of the present invention; and

FIG. 11 is a flow chart illustrating operation of the digital low-pass filter of FIG. 10.

Referring first to FIG. 1, there is shown a digital low-pass filter (LPF) to which an apparatus for calculating a sum of products according to the present invention is applied. The digital low-pass filter shown includes a data memory 1 into which input data of, for example, 16 bits inputted from an input terminal DI thereof are stored. The data memory 1 receives an address signal at an address terminal AD thereof and outputs data stored at an address designated by the address signal by way of an output terminal DO thereof to a latch circuit 2, an adder 3 and a switch 14. The latch circuit 2 receives, at a clock terminal CLK thereof, a clock signal having a period of 2/CK equal to twice a period of 1/CK (frequency CK) in which data are read out from the data memory 1, at a timing 16-bit data read out from the data memory 1 at a timing at which the clock signal is inputted. The latch circuit 2 outputs the thus latched 16-bit data to an input terminal A of the adder 3. In other words, the latch circuit 2 latches every other one of data read out from the data memory 1 and supplies the latched data to the adder 3.

The adder 3 extends most significant bits (MSBs) of 16-bit data outputted from the latch circuit 2 and 16-bit data outputted from the data memory 1 each by one bit and copies the most significant bits, that is, the sign bits, of data outputted from the latch circuit 2 and data outputted from the data memory 1 each to the thus extended one bit, thereby providing a countermeasure for an overflow which may be caused by addition of data. The adder 3 truncates the least significant bit (LSB) of each 17-bit data obtained by the addition and outputs the upper 16 bits to a multiplier 4.

A coefficient memory 5 stores in advance therein coefficients C.sub.n (n is a natural number) of the digital low-pass filter, for example, separately for the mantissa parts of 8 bits and differences between the exponent parts of the coefficients C.sub.n and the exponent parts of the coefficients C.sub.n-1 of preceding order. The coefficient memory 5 receives an output of a down counter 10 at an address terminal AD thereof and supplies the mantissa part of a coefficient C.sub.n and the corresponding index part difference stored at an address thereof designated by the output of the down counter 10 to the multiplier 4 and a shifter 8. It is to be noted that, in the present digital low-pass filter, the mantissa parts of the coefficients stored in the coefficient memory 5 are adjusted so that the difference between the exponent parts of each adjacent coefficients may consist of one bit, that is, the difference may be either 0 or 1.

Here, the digital low-pass filter is in the form of a digital filter of the interpolation type of order 39 which twofold oversamples an input digital signal to produce a filter output. The digital low-pass filter is designed so that the impulse response thereof presents such a waveform as shown in FIG. 2. As can be seen from the impulse response shown in FIG. 2, the coefficients of the low-pass filter have a tendency that the absolute values thereof decrease as the order number increases, and are symmetrical with respect to the coefficient Co of order 0 and are of the interpolation type. Accordingly, the coefficients C.sub.2, C.sub.4, C.sub.6, C.sub.8, C.sub.10, C.sub.12, C.sub.14, C.sub.16 and C.sub.18 of even-numbered order except the coefficient C.sub.0 (=1) of order 0 are all equal to zero. Further, the coefficients of odd-numbered order are such as follows:

C.sub.1 =0.6328

C.sub.3 =-0.2031

C.sub.5 =0.1152

C.sub.7 =-0.07520

C.sub.9 =0.05078

C.sub.11 =-0.03516

C.sub.13 =0.02393

C.sub.15 =-0.01587

C.sub.17 =0.009888

C.sub.19 =-0.008057

In this manner, in the present digital low-pass filter, since the coefficients C.sub.2 to C.sub.18 (C.sub.2, C.sub.4, C.sub.6, C.sub.8, C.sub.10, C.sub.12, C.sub.14, C.sub.16 and C.sub.18) of even-numbered order except order 0 are equal to zero, the difference between each adjacent coefficients C.sub.1 to C.sub.19 (C.sub.1 , C.sub.3, C.sub.5, C.sub.7, C.sub.9, C.sub.11, C.sub.13, C.sub.15, C.sub.17 and C.sub.19) of odd-numbered order except the coefficients C.sub.2 to C.sub.18 of even-numbered order, that is, the difference between the exponent parts of the coefficients C.sub.2q+1 and C.sub.2q-1, is used as a difference between the exponent parts of each adjacent coefficients. Accordingly, the exponent part difference of the coefficient C.sub.2q+1 is defined as a difference between the exponent parts of the coefficients C.sub.2q+1 and C.sub.2q-1. Here, q is a natural number.

The coefficients C.sub.1 to C.sub.19 of odd-numbered order can be represented in the following manner in the form of a floating point form wherein the mantissa part thereof includes 8 bits and the exponent part difference is either 0 or 1:

C.sub.1 =01010001.times.2.sup.-7

C.sub.3 =11001100.times.2.sup.-8

C.sub.5 =00111011.times.2.sup.-9

C.sub.7 =10110011.times.2.sup.-10

C.sub.9 =01101000.times.2.sup.-11

C.sub.11 =10111000.times.2.sup.-11

C.sub.13 =01100010.times.2.sup.-12

C.sub.15 =10111111.times.2.sup.-12

C.sub.17 =01010001.times.2.sup.-13

C.sub.19 =10111110.times.2.sup.-13

The coefficients C.sub.1 to C.sub.19, the mantissa parts of which are adjusted such that the difference between the exponent parts of the coefficients C.sub.1 and C.sub.3 is 1; the difference between the exponent parts of the coefficients C.sub.3 and C.sub.5 is 1; the difference between the exponent parts of the coefficients C.sub.5 and C.sub.7 is 1; the difference between the exponent parts of the coefficients C.sub.7 and C.sub.9 is 1; the difference between the exponent parts of the coefficients C.sub.9 and C.sub.11 is 0; the difference between the exponent parts of the coefficients C.sub.11 and C.sub.13 is 1; the difference between the exponent parts of the coefficients C.sub.13 and C.sub.15 is 0; the difference between the exponent parts of the coefficients C.sub.15 and C.sub.17 is 1; and the difference between the exponent parts of the coefficients C.sub.17 and C.sub.19 is 0 in this manner, are stored in advance in the coefficient memory 5, for example, starting at address 0 as seen in FIG. 3. In the present low-pass filter, however, since the position of the decimal point of the coefficient C.sub.1 stored at address 0 of the coefficient memory 5 is treated as a reference decimal point position, the exponent part difference of the coefficient C.sub.1 is stored as "0" in the coefficient memory 5.

The multiplier 4 calculates the product of 16-bit data outputted from the adder 3 and the 8-bit mantissa part of a coefficient C.sub.n stored in the coefficient memory 5 and outputs a result of the calculation of 23 bits. Here, since each of the most significant bits of the 16-bit data outputted from the adder 3 and the 8-bit mantissa part of the coefficient C.sub.n stored in the coefficient memory 5 is a sign bit, the product thus calculate does not include 24 bits (=16 bits.times.8 bits) but includes 23 bits (=15 bits.times.7 bits +1 bit (sign bit)).

A cumulative adder 6 receives, at input terminals B.sub.0 to B.sub.23 thereof, 24-bit data obtained by extension by one bit of the most significant bit of 23-bit data (product) outputted from the multiplier 4, and further receives, at input terminals A.sub.0 to A.sub.23 thereof, 24-bit data stored in and outputted from an accumulator (ACC) 7. The cumulative adder 6 thus adds the two 24-bit input data and outputs a result of the addition from output terminals .SIGMA..sub.0 to .SIGMA..sub.23 thereof.

The shifter 8 connects the output terminals .SIGMA..sub.0 to .SIGMA..sub.23 of the cumulative adder 6 to input terminals D.sub.0 to D.sub.23 of the accumulator 7, respectively, when the exponent part difference of a coefficient corresponding to the mantissa part read out from the coefficient memory 5 is 0. On the other hand, when the exponent part difference of the coefficient corresponding to the mantissa part read out from the coefficient memory 5 is 1, the shifter 8 connects the output terminals .SIGMA..sub.1 to .SIGMA..sub.23 of the cumulative adder 6 to the input terminals D.sub.0 to D.sub.22 of the accumulator 7, respectively, and connects the output terminal .SIGMA..sub.23 of the cumulative adder 6 to the input terminal D.sub.23 of the accumulator 7. Accordingly, the outputs of the cumulative adder 6 are shifted down by one bit when they are supplied to the accumulator 7.

The accumulator 7 receives a clock signal of the period of 2/CK at a clock terminal CLK thereof and temporarily stores therein 24-bit data outputted from the cumulative adder 6 by way of the shifter 8 at the timing of the clock signal. Further, the accumulator 7 receives a clear signal of the period of 1/fs at a clear terminal CLR thereof and resets, at the timing of the clear signal, the stored contents thereof to zero.

The switch 14 is switched in the period of 1/fs and-alternately outputs data read out from the data memory 1 and data stored in the accumulator 9 to an output flip-flop (FF) 9. The output flip-flop 9 latches therein data read out from the data memory or data received from the accumulator 7 by way of the switch 14 and supplies the latched data, for example, to a digital to analog converter or some other circuit not shown.

The down counter 10 receives a load signal of the period of 1/fs and sets a predetermined initial value, for example, 14H (the suffix H denotes a hexadecimal value), thereto at the timing of the load signal. Then, each time a clock signal of the period of 1/CK is supplied to a clock terminal CLK of the down counter 10, the down counter 10 decrements its count value until 0H is reached, and the count value of the down counter 10 is supplied to an exclusive OR (XOR) circuit 11. Further, the upper four bits of the count value of the down counter 10 are supplied to an address terminal AD of the coefficient memory 5.

The exclusive OR circuit 11 includes four exclusive OR gates. The upper four bits of the count value of the down counter 10 are inputted to first input terminals of the exclusive OR circuits while the least significant bit of the count value of the down counter 10 is inputted commonly to the other or second input terminals of the exclusive OR circuits. When the least significant bit of the count value of the down counter 10 inputted to the second input terminals of the exclusive OR circuit 11 is 0, the exclusive OR circuit 11 outputs the upper four bits of the count value of the down counter 10 inputted to the first input terminals of the exclusive OR circuit 11 as they are without modifying them. On the other hand, when the least significant bit of the count value inputted to the second input terminal terminals of the exclusive OR circuit 11 is 1, the exclusive OR circuit 11 inverts the upper four bits of the count value inputted to the first input terminals thereof and outputs the inverted bits therefrom. The exclusive OR circuit 11 then adds, to the bit train of the four bits thus obtained, the least significant bit of the count value outputted from the down counter 10 as the most significant bit to the bit train and supplies the thus obtained bit train of 5 bits to an input terminal B of an adder 13.

A base counter 12 receives a clock signal of the period of 1/fs at a clock terminal CLK thereof and increments its count value at the timing of the clock signal. The adder 13 adds a count value outputted from the base counter 12 and a value outputted from the exclusive OR circuit 11 and outputs the thus obtained sum value to the address terminal AD of the data memory 1.

Referring now to FIG. 5, in operation, sampling is performed at the sampling frequency of fs at the data memory 1 so that input digital data supplied for each period of 1/fs (refer to the curve (a) in FIG. 5) is successively stored or written into the data memory 1 starting at address 0 (refer to the curve (h) of FIG. 5).

Here, generally one frame of data includes the (order number n of the digital filter+1) samples of data D.sub.-n, D.sub.-(n-1), . . . , D.sub.-1, D.sub.0, D.sub.1, . . . , D.sub.n-1 and D.sub.n. However, in the present digital low-pass filter, since it is a digital filter of the interpolation type, one frame of data includes the number of data equal to the number of filter coefficients of odd-numbered order (FIG. 2), that is, a total of 20 sample data D.sub.-19, D.sub.-17, D.sub.-15, D.sub.-13, D.sub.-11, D.sub.-9, D.sub.-7, D.sub.-5, D.sub.-3, D.sub.-1, D.sub.1, D.sub.3, D.sub.5, D.sub.7, D.sub.9, D.sub.11, D.sub.13, D.sub.15, D.sub.17 and D.sub.19.

The count value of the base counter 12 is incremented at each timing at which data of one frame are stored into the data memory 1, that is, in the period of 1/fs. Since the count value of the base counter 12 is initially set so that it may be equal to an address of the data memory 1 to which data D.sub.1 is to be stored, it always indicates an address of the data memory 1 to which data D.sub.1 is to be successively stored.

On the other hand, when a load (counter synchronized load) signal of the period of 1 /fs is inputted to the down counter 10 (refer to the curve (e) of FIG. 5), the down counter 10 is set to its initial value of 14H ("00010100" in binary value). Then, the count value of the down counter 10 is decremented at each timing at which a clock signal of the frequency CK, which is equal to a multiple of the frequency of fs at least by the number of data of one frame, for example, equal to 32 times the frequency of fs, and accordingly of the period of 1/CK, is supplied (refer to the curve (d) of FIG. 5) until the count value is reduced to 0H ("00000000" in binary value) (refer to the curve (f) in FIG. 5). The count value of the down counter 10 is supplied to the exclusive OR circuit 11. The exclusive OR circuit 11 converts, when the least significant bit of the count value outputted from the down counter 10 is 0, the 5-bit count value outputted from the down counter 10 into a bit train wherein the least significant bit of the count value is substituted into the most significant bit. On the other hand, when the least significant bit of the count value outputted from the down counter 10 is 1, the exclusive OR circuit 11 inverts the upper four bits of the count value of the down counter 10 and adds the least significant bit of the count value of the down counter 10 as the most significant bit to the bit train of the four bits to obtain a bit train of 5 bits. The exclusive OR circuit 11 outputs the bit train of 5 bits thus obtained to the input terminal B of the adder 13 (refer to the curve (g) of FIG. 5).

FIG. 4 illustrates the relationship between the count value outputted from the down counter 10 and the bit train outputted from the exclusive OR circuit 11. When the count value is 14H, that is, 00010100.sub.2 (the subscript 2 denotes a binary value), the least significant bit of the count value is 1, and accordingly, the output of the exclusive OR circuit 11 is, replacing the least significant bit of the count value into the most significant bit, the bit train of 00001010.sub.2, that is, 10 in decimal notation. When the count value is 13H, that is, 00010011.sub.2, since the least significant bit of the count value is 1, the output of the exclusive OR circuit 11 is, inverting the upper four bits of the count value (00001001.sub.2 .fwdarw.00000110.sub.2) and adding the least significant bit of 12 of the count value as the most significant bit to the bit train, the bit train of 00010110.sub.2, that is, -10. The values shown in FIG. 4 are successively outputted in a similar manner from the exclusive OR circuit 11.

It can be seen from FIG. 4 that the values successively outputted from the exclusive OR circuit 11 are offset values of the addresses of the data D.sub.-19 to D.sub.19 (D.sub.-19, D.sub.-17, D.sub.-15, D.sub.-13, D.sub.-11, D.sub.-9, D.sub.-7, D.sub.-5, D.sub.-3, D.sub.-1, D.sub.1, D.sub.3, D.sub.5, D.sub.7, D.sub.9, D.sub.11, D.sub.13, D.sub.15, D.sub.17 and D.sub.19) stored in the data memory 1 with reference to the address of the data memory 1 in which data D.sub.1 is stored.

The adder 13 adds an address of the data memory 1 which is outputted from the base counter 12 and in which the data D.sub.1 is stored and an offset address outputted from the exclusive OR circuit 11, and outputs the sum thus obtained to the address terminal AD of the data memory 1. The data D.sub.n stored at the address of the data memory 1 supplied from the adder 13 is read out from the data memory 1 and supplied to the latch circuit 2, the adder 3 and the switch 14. Accordingly, data are successively read out from the data memory 1 in the period of 1/CK, in which an address is outputted from the adder 13, starting at data which is multiplied at the multiplier 4 by a coefficients C.sub.n having a highest order number, that is, a coefficient having a comparatively low absolute value. Thus, data are read out in the order of D.sub.-19, D.sub.19, D.sub.-17, D.sub.17, D.sub.-15, D.sub.15, D.sub.-13, D.sub.13, D.sub.-11, D.sub.11, D.sub.-9, D.sub.9, D.sub.-7, D.sub.7, D.sub.-5, D.sub.5, D.sub.-3, D.sub.3, D.sub.-1 and D.sub.1 (refer to the curve (i) in FIG. 5).

Of the data D-19, D.sub.19, D.sub.-17, D.sub.17, D.sub.-15, D.sub.15, D.sub.-13, D.sub.13, D.sub.-11, D.sub.11, D.sub.-9, D.sub.9, D.sub.-7, D.sub.7, D.sub.-5, D.sub.5, D.sub.-3, D.sub.3, D.sub.-1 and D.sub.1 read out in this order from the data memory 1 in the period of 1/CK in this manner, the data D.sub.-19, D.sub.-17, D.sub.-15, D.sub.-13, D.sub.-11, D.sub.-9, D.sub.-7, D.sub.-5, D.sub.-3 and D.sub.-1 are successively latched by the latch circuit 2 (refer to the curve (j) of FIG. 5) at the timing at which the clock signal (curve (c) of FIG. 5) of the period of 2/CK is inputted to the clock terminal CLK of the latch circuit 2. Data is thus latched for each period of 2/CK by the latch circuit 2 and then supplied to the adder 3. Meanwhile, data is read out from the data memory 1 for each period of 1/CK and supplied to the adder 3 similarly.

Accordingly, at the adder 3, the data D.sub.-19 to D.sub.-1 successively latched by the latch circuit 2 in the period of 2/CK (i.e., D.sub.-19, D.sub.-17, D.sub.-15, D.sub.-13, D.sub.-11, D.sub.-9, D.sub.-7, D.sub.-5, D.sub.-3 and D.sub.-1) and, of the data D.sub.-19, D.sub.19, D.sub.-17, D.sub.17, D.sub.-15, D.sub.15, D.sub.-13, D.sub.13, D.sub.-11, D.sub.11, D.sub.-9, D.sub.9, D.sub.-7, D.sub.7, D.sub.-5, D.sub.5, D.sub.-3, D.sub.3, D.sub.-1 and D.sub.1 read out from the data memory 1 in the period of 1/CK, those data D.sub.19, D.sub.17, D.sub.15, D.sub.13, D.sub.11, D.sub.9, D.sub.7, D.sub.5, D.sub.3 and D.sub.1 which have not been latched by the latch circuit 2 are added, respectively. The sum data thus obtained, that is, data D.sub.-19 +D.sub.19, D.sub.-17 +D.sub.17, D.sub.-15 +D.sub.15, D.sub.-13 +D.sub.13, D.sub.-11 +D.sub.11, D.sub.-9 +D.sub.9, D.sub.-7 +D.sub.7, D.sub.-5 +D.sub.5, D.sub.-3 +D.sub.3 and D.sub.-1 +D.sub.1, are successively outputted to the multiplier 4 at the timing at which data D.sub.n is latched by the latch circuit 2, that is, in the period of 2/CK.

Meanwhile, from the coefficient memory 5, a coefficient stored at an address corresponding to the upper four bits of the count value outputted from the down counter 10 is read Out and outputted to the multiplier 4.

Here, the upper four bits of the count value supplied from the down counter 18 repetitively appear twice except the upper 4 bits of the initial value of 00010101.sub.2 (14H) as seen from FIG. 4. Since the count value of the down counter 10 is decremented by one for each period of 1/CK as described hereinabove, the upper four bits of the count value are decremented by one from 9 for each period of 2/CK except when it is equal to the initial value of 00001010.sub.2, that is, 10 in decimal notation. In the present digital low-pass filter, since data is written into the data memory 1 when the count value of the down counter 10 assumes its initial value of 00010101.sub.2 (refer to the curve (h) of FIG. 5), thereafter the mantissa parts of the coefficients C.sub.19 to C.sub.1 stored at addresses corresponding to the count value of the down counter 10, which is successively decremented from 9 to 0, are successively read out in the period of 2/CK from the coefficient memory 5 and supplied to the multiplexer 4.

Accordingly, the mantissa parts of the coefficients which are stored in the coefficient memory 5 and adjusted so that each exponent part difference may be equal to either 0 or 1 are read out successively in reverse order of magnitude of the exponent parts (FIG. 3). In other words, the mantissa parts of the coefficients stored in the coefficient memory 5 are read out in such a order that the decimal point position is not changed or is shifted rightwardly by one column.

As described so far, the sum data D.sub.-19 +D.sub.19, D.sub.-17 +D.sub.17, D.sub.-15 +D.sub.15, D.sub.-13 +D.sub.13, D.sub.-11 +D.sub.11, D.sub.-9 +D.sub.9, D.sub.-7 +D.sub.7, D.sub.-5 +D.sub.5, D.sub.-3 +D.sub.3 and D.sub.-1 +D.sub.-1 are successively outputted in the period of 2/CK from the adder 3 to the multiplier 4, and the mantissa parts of the coefficients C.sub.19 to C.sub.1 stored in addresses corresponding to the count value of the down counter 10, which is successively decremented from 9 to 0, are successively supplied in the period of 2/CK from the coefficient memory 5 to the multiplier 4. The multiplier 4 successively calculates in the period of 2/CK the product of the data D.sub.-19 +D.sub.19 and the mantissa part of the coefficient C.sub.19, the product of the data D.sub.-17 +D.sub.17 and the mantissa part of the coefficient C.sub.17, the product of the data D.sub.-15 +D.sub.15 and the mantissa part of the coefficient C.sub.15, the product of the data D.sub.-13 +D.sub.13 and the mantissa part of the coefficient C.sub.13, the product of the data D.sub.-11 +D.sub.11 and the mantissa part of the coefficient C.sub.11, the product of the data D.sub.-9 +D.sub.9 and the mantissa part of the coefficient C.sub.9, the product of the data D.sub.-7 +D.sub.7 and the mantissa part of the coefficient C.sub.7, the product of the data D.sub.-5 +D.sub.5 and the mantissa part of the coefficient C.sub.5, the product of the data D.sub.-3 +D.sub.3 and the mantissa part of the coefficient C.sub.3, and the product of the data D.sub.-1 +D.sub.1 and the mantissa part of the coefficient C.sub.1. The products thus calculated are successively outputted to the cumulative adder 6.

The cumulative adder 6 adds a product outputted from the multiplier 4 and a value outputted from the accumulator 7 so that the products successively outputted from the multiplier 4 are added cumulatively, and the cumulative sum is outputted from the cumulative adder 6 to the shifter 8. When the exponent part difference (FIG. 3) corresponding to the mantissa part of a coefficient supplied from the coefficient memory 5 to the multiplier 4 is 0, the sum value outputted from the cumulative adder 6 is supplied as it is by way of the shifter 8 to the accumulator 7 (refer to the curve (m) of FIG. 5). On the other hand, when the exponent part difference (FIG. 3) corresponding to the mantissa part of the coefficient supplied from the coefficient memory 5 to the multiplier 4 is 1, the sum value outputted from the cumulative adder 6 is shifted down by one bit by the shifter 8 and then supplied to the accumulator 7 (refer to the curve (m) of FIG. 5).

Here, the mantissa parts of the coefficients which are stored in the coefficient memory 5 and adjusted so that the exponent part differences thereof may be equal to either 0 or 1 are read out successively in reverse order of magnitude of the exponent parts described hereinabove (FIG. 3). In other words, the mantissa parts of the coefficients stored in the coefficient memory 5 are read out in such a order that the decimal point position is not changed or is shifted rightwardly by one column. Accordingly, when the exponent part difference (FIG. 3) corresponding to the mantissa part of a coefficient supplied currently from the coefficient memory 5 to the multiplier 4 is 0, the decimal point position of the mantissa part of the coefficient and the decimal point position of the mantissa part of a coefficient for which the product of an output value of the adder 3 is to be subsequently calculated by the multiplier 4 are equal to each other, and accordingly, bit shifting for the adjustment in column between the mantissa parts of the two coefficients is not performed by the shifter 8.

On the other hand, when the exponent part difference (FIG. 3) corresponding to the mantissa part of the coefficient supplied currently from the coefficient memory 5 to the multiplier 4 is 1, the decimal point position of the mantissa part of the coefficient is at a position higher by one column distance (a position shifted leftwardly by one column distance) than the decimal point position of the mantissa part of a coefficient for which the product of an output value of the adder 3 is to be subsequently calculated by the multiplier 4, and accordingly, bit shifting for the adjustment in column between the two values is performed by the shifter 8. In particular, the value obtained by cumulative addition by the cumulative adder 6 of the product calculated by the multiplier 4 between the exponent part of the coefficient currently read out from the coefficient memory 5 and the output of the adder 3 is shifted rightwardly by one column distance (shifted down by one bit).

A value outputted from the shifter 8 is latched in the period of 2/CK by the accumulator 7 and outputted to the cumulative adder 6 and the switch 14.

In this manner, a value outputted from the cumulative adder 6 by way of the shifter 8 is latched in the period of 2/CK by the accumulator 7, and the thus latched value is outputted to the cumulative adder 6. Meanwhile, the products calculated by the multiplier 4, that is, the product of the data D.sub.-19 +D.sub.19 and the mantissa part of the coefficient C.sub.19, the product of the data D.sub.-17 +D.sub.17 and the mantissa part of the coefficient C.sub.17, the product of the data D.sub.-15 +D.sub.15 and the mantissa part of the coefficient C.sub.15, the product of the data D.sub.-13 +D.sub.13 and the mantissa part of the coefficient C.sub.13, the product of the data D.sub.-11 +D.sub.11 and the mantissa part of the coefficient C.sub.11, the product of the data D.sub.-9 +D.sub.9 and the mantissa part of the coefficient C.sub.9, the product of the data D.sub.-7 +D.sub.7 and the mantissa part of the coefficient C.sub.7, the product of the data D.sub.-5 +D.sub.5 and the mantissa part of the coefficient C.sub.5, the product of the data D.sub.-3 +D.sub.3 and the mantissa part of the coefficient C.sub.3, and the product of the data D.sub.-1 +D.sub.1 and the mantissa part of the coefficient C.sub.1, are successively outputted in the period of 2/CK to the cumulative adder 6.

Accordingly, at the cumulative adder 6, the product of the data D.sub.-19 +D.sub.19 and the mantissa part of the coefficient C.sub.19, the product of the data D.sub.-17 +D.sub.17 and the mantissa part of the coefficient C.sub.17, the product of the data D.sub.-15 +D.sub.15 and the mantissa part of the coefficient C.sub.15, the product of the data D.sub.-13 +D.sub.13 and the mantissa part of the coefficient C.sub.13, the product of the data D.sub.-11 +D.sub.11 and the mantissa part of the coefficient C.sub.11, the product of the data D.sub.-9 +D.sub.9 and the mantissa part of the coefficient C.sub.9, the product of the data D.sub.-7 +D.sub.7 and the mantissa part of the coefficient C.sub.7, the product of the data D.sub.-5 +D.sub.5 and the mantissa part of the coefficient C.sub.5, the product of the data D.sub.-3 +D.sub.3 and the mantissa part of the coefficient C.sub.3, and the product of the data D.sub.-1 +D.sub.1 and the mantissa part of the coefficient C.sub.1, which are successively outputted in the period of 2/CK from the multiplier 4, are successively added while they are adjusted in column thereof by the shifter 8. Consequently, a sum total of all of the products of the data D.sub.-19 +D.sub.19 and the mantissa part of the coefficient C.sub.19, the product of the data D.sub.-17 +D.sub.17 and the mantissa part of the coefficient C.sub.17, the product of the data D.sub.-15 +D.sub.15 and the mantissa part of the coefficient C.sub.15, the product of the data D.sub.-13 +D.sub.13 and the mantissa part of the coefficient C.sub.13, the product of the data D.sub.-11 +D.sub.11 and the mantissa part of the coefficient C.sub.11, the product of the data D.sub.-9 +D.sub.9 and the mantissa part of the coefficient C.sub.9, the product of the data D.sub.-7 +D.sub.7 and the mantissa part of the coefficient C.sub.7, the product of the data D.sub.-5 +D.sub.5 and the mantissa part of the coefficient C.sub.5, the product of the data D.sub.-3 +D.sub.3 and the mantissa part of the coefficient C.sub.3, and the product of the data D.sub.-1 +D.sub.1 and the mantissa part of the coefficient C.sub.1, that is, a sum of products of the data D.sub.-19 to D.sub.19 (data D.sub.-1 +D.sub.1 to D.sub.-19 +D.sub.19) and the coefficients C.sub.1 to C.sub.19, respectively, is finally latched in the accumulator 7 (refer to the curve (m) in FIG. 5).

A cumulative sum value latched in the accumulator 7 and data D.sub.1 supplied from the data memory 1 are alternately selected by the switch 14, which is switched in the period of 2/fs, and supplied to the output flip-flop 9. Thus, the cumulative sum value latched in the accumulator 7 is latched as an output of an odd-numbered sample (ODD) of the digital low-pass filter by the output flip-flop 9, and the data D.sub.1 supplied from the data memory 1 is latched as an output of an even-numbered sample (EVEN) of the digital low-pass filter (refer to the curves (i) and (p) of FIG. 5, respectively). The output of the digital low-pass filter is supplied to a digital to analog (D/A) converter or the like connected to it.

As described so far, in the present digital low-pass filter, coefficients are stored separately for the mantissa parts and the exponent part differences and calculation of a sum of products is performed in reverse order of magnitude of the exponent parts while bit shifting (shifting down) of an interim result of the calculation of a sum of products is performed in accordance with the exponent part difference. Consequently, the bit length (range) which the apparatus can handle is utilized effectively and calculation of a sum of products can be performed with a high degree of accuracy.

It is to be noted that, the latched contents of the accumulator 7 are reset in response to a reset signal supplied to it in the period of 1/fs (refer to the curve (n) in FIG. 5).

While, in the digital low-pass filter described above, the exponent part difference of a coefficient C.sub.2q+1 stored in the coefficient memory 5 is defined as a difference between the exponent part of the coefficient C.sub.2q+1 and the exponent part of the coefficient C.sub.2q-1 (FIG. 3), the exponent part difference of the coefficient C.sub.2q-1 stored in the coefficient memory 5 can be defined as the difference between the exponent part of the coefficient C.sub.2q+1 and the exponent part of the coefficient C.sub.2q-1 if the shifter 8 for adjustment in column, which is interposed between the output terminals .SIGMA..sub.0 to .SIGMA..sub.23 of the cumulative adder 6 and the input terminals D.sub.0 to D.sub.23 of the accumulator 7 in the digital low-pass filter described above, is interposed otherwise between the output-terminals Q.sub.0 to Q.sub.23 of the accumulator 7 and the input terminals A.sub.0 to A.sub.23 of the cumulative adder 6 (refer to FIG. 6).

Further, in the case of such a coefficient of a popular digital filter of the FIR type wherein the maximum point increases while the exponent part increases and decreases as shown in FIG. 7, calculation of a sum of products which minimizes the influence of the round-off error by adjusting the exponent parts of the coefficients so that the exponent parts of the coefficients except the coefficient which has the greatest exponent part increase monotonously toward the maximum exponent part (in FIG. 7, the exponent part of the coefficient C.sub.1) and the exponent part differences may be equal to either 0 or 1.

Further, in this instance, a sum of products can be calculated with a higher degree of accuracy than that of the case of FIG. 7 by generating an address of a coefficient stored in the coefficient memory 5, for example, by a program so that calculation of a sum of products may proceed in reverse order of exponent parts as seen in FIG. 8.

In the present digital low-pass filter, when a coefficient for which calculation of a sum of products is to be performed is, for example, 81.5, if the coefficient of 81.5 is represented in the floating point form having an 8-bit mantissa part, then the result is

and accordingly, the accuracy is deteriorated. However, if the coefficient of 81.5 is represented in the developed (divided) values of 82/2 and 81/2 and 81/2 (82/2+81/2=81.5), then are given as

and

Accordingly, the 8-bit mantissa part can be represented in the floating point form without deteriorating the accuracy. Accordingly, calculation of a sum of products can be performed without deteriorating the accuracy by developing a coefficient and storing the developed coefficient into the coefficient memory 5 in this manner.

It is to be noted that, while, in the digital low-pass filter described above, the exponent part difference assumes either 0 or 1 if the number of bits with which an exponent part difference can be stored is increased in the coefficient memory 5 and the shifter 8 is replaced by another shifter which can shift down an exponent part difference within the number of bits, then calculation of a sum of products with a high degree of accuracy can be performed for an arbitrary exponent part difference.

Referring now to FIG. 9, there is shown another digital low-pass filter to which an apparatus for calculating a sum of products according to the present invention is applied. The present digital low-pass filter is a digital filter of the interpolation type of order 39 which can twofold oversample an input digital signal to produce a filter output, similarly as in the digital low-pass filter described hereinabove with reference to FIG. 1. Also the digital low-pass filter is designed so that the impulse response thereof presents such a waveform as shown in FIG. 2. The coefficients of the present low-pass filter are symmetrical with respect to the coefficient C.sub.0 of order 0, and the coefficients C.sub.2, C.sub.4, C.sub.6, C.sub.8, C.sub.10, C.sub.12, C.sub.14, C.sub.16 and C.sub.18 of even-numbered order except the coefficient C.sub.0 (=1) of order 0 are all equal to zero.

Each of registers 21.sub.1 to 21.sub.20 of a register section 21 latches, in the period of 1/fs, time series data sampled at the sampling period of fs and inputted from the register 21.sub.20 and outputs the latched data successively to a left-side one of the registers 21.sub.1 to 21.sub.20. Adders 22.sub.1 to 22.sub.10 of an adding section 22 add data D.sub.-1 and D.sub.1, data D.sub.-3 and D.sub.3, data D.sub.-5 and D.sub.5, data D.sub.-7 and D.sub.7, data D.sub.-9 and D.sub.9, data D.sub.-11 and D.sub.11, data D.sub.-13 and D.sub.13, data D.sub.-15 and D.sub.15, data D.sub.-17 and D.sub.17, and data D.sub.-19 and D.sub.19 latched in the register section 21, respectively.

Multipliers 23.sub.1 to 23.sub.10 of a multiplying section 23 multiply values outputted from the adders 22.sub.1 to 22.sub.10 by the mantissa parts of coefficients same as those of the digital low-pass filter described hereinabove with reference to FIG. 1, that is, by the mantissa parts (FIG. 3) of the coefficients C.sub.1 to C.sub.19, respectively.

Shifters 25.sub.1 to 25.sub.6 of a shifter section 25 shift down values outputted from adders 24.sub.2 to 24.sub.5, 24.sub.7 and 24.sub.9, respectively, of an adder section 24 by one bit.

The adder 24.sub.9 of the adding section 24 calculates a sum of the output of the multiplier 23.sub.10 and the output of the multiplier 23.sub.9. An adder 24.sub.8 of the adding section 24 calculates a sum of the output of the shifter 25.sub.6 and the multiplier 23.sub.8. The adder 24.sub.7 of the adding section 24 calculates a sum of the output of the adder 24.sub.8 and the output of the multiplier 23.sub.7. An adder 24.sub.6 of the adding section 24 calculates a sum of the output of the shifter 25.sub.5 and the output of the multiplier 23.sub.6. The adder 24.sub.5 of the adding section 24 calculates a sum of the output of the adder 24.sub.6 and the output of the multiplier 23.sub.5. The adder 24.sub.4 of the adding section 24 calculates a sum of the output of the shifter 25.sub.4 and the output of the multiplier 23.sub.4. The adder 24.sub.3 of the adding section 24 calculates a sum of the output of the shifter 25.sub.3 and the output of the multiplier 23.sub.3. The adder 24.sub.2 of the adding section 24 calculates a sum of the output of the shifter 25.sub.2 and the output of the multiplier 23.sub.2. The adder 24.sub.1 of the adding section 24 calculates a sum of the output of the shifter 25.sub.1 and the output of the multiplier 23.sub.1.

A register 26 latches data, which is latched in the period of 1/fs by the register 21.sub.11, in the period of 1/2fs equal to one half the period of 1/fs.

In the digital low-pass filter of FIG. 9, an odd-numbered sample (ODD) of the filter output obtained by twofold oversampling is given as a sum of the products of input data and the coefficients C.sub.1 to C.sub.19 having odd-numbered suffixes, but an even-numbered sample (EVEN) is given as the product of the coefficient C.sub.0 and input data because the coefficients C.sub.2, C.sub.4, C.sub.6, C.sub.8, C.sub.10, C.sub.12, C.sub.14, C.sub.16 and C.sub.18 are all equal to 0. Since the coefficient C.sub.0 is 1, the even-number sample is input data (data D.sub.0) itself for which the product of the coefficient C.sub.0 is to be calculated. Further, since data inputted in the period of fs is twofold oversampled, if it is assumed imaginarily that data obtained by interpolation to the input data is inputted in the period of 1/2fs, then when an odd-numbered sample of the filter output is outputted, data D.sub.1 for which the product of the coefficient C.sub.1 is calculated corresponds to the data D.sub.0 after lapse of the time of 1/2fs.

Consequently, if data D.sub.1 latched in the period of 1/fs by the register 21.sub.11 is latched in the period of 1/2fs by the register 26, then a twofold sampled even-numbered sample of the filter output is obtained.

The switch 27 is switched in the period of 1/2fs and alternately supplies the outputs of the data D.sub.0 latched by the register 26 (or the data D.sub.1 after lapse of the time of 1/2fs) and the adder 24.sub.1, for example, to a digital to analog converter connected to the digital low-pass filter.

In operation, data D.sub.-1 and D.sub.1, data D.sub.-3 and D.sub.3, data D.sub.-5 and D.sub.5, data D.sub.-7 and D.sub.7, data D.sub.-9 and D.sub.9, data D.sub.-11 and D.sub.11, data D.sub.-13 and D.sub.13, data D.sub.-15 and D.sub.15, data D.sub.-17 and D.sub.17, and data D.sub.-19 and D.sub.19 latched in the period of 1/fs by the register section 21 are added by the adders 22.sub.1 to 22.sub.10, respectively. The thus obtained sum data D.sub.-1 +D.sub.1, D.sub.-3 +D.sub.3, D.sub.-5 +D.sub.5, D.sub.-7 +D.sub.7, D.sub.-9 +D.sub.9, D.sub.-11 +D.sub.11, D.sub.-13 +D.sub.13, D.sub.-15 +D.sub.15, D.sub.-17 +D.sub.17 and D.sub.-19 +D.sub.19 are supplied to the multipliers 23.sub.1 to 23.sub.10, respectively.

The multipliers 23.sub.1 to 23.sub.10 calculate the product of the data D.sub.-1 +D.sub.1 and the mantissa part of the coefficient C.sub.1, the data D.sub.-3 +D.sub.3 and the mantissa part of the coefficient C.sub.3, the data D.sub.-5 +D.sub.5 and the mantissa part of the coefficient C.sub.5, the data D.sub.-7 +D.sub.7 and the mantissa part of the coefficient C.sub.7, the data D.sub.-9 +D.sub.9 and the mantissa part of the coefficient C.sub.9, the data D.sub.-11 +D.sub.11 and the mantissa part of the coefficient C.sub.11, the data D.sub.-13 +D.sub.13 and the mantissa part of the coefficient C.sub.13, the data D.sub.-15 +D.sub.15 and the mantissa part of the coefficient C.sub.15, the data D.sub.-17 +D.sub.17 and the mantissa part of the coefficient C.sub.17, and the data D.sub.-19 +D.sub.19 and the mantissa part of the coefficient C.sub.19, respectively.

Here, the mantissa parts of the coefficients for which the products of data supplied from the adding section 22 are calculated by the multiplying section 23 are the same as those in the digital low-pass filter described hereinabove with reference to FIG. 1 (FIG. 3).

Since the exponent part difference of the coefficient C.sub.19 having the mantissa part for which the product of the data D.sub.-19 +D.sub.19 is calculated by the multiplier 23.sub.10 is 0, that is, the difference between the exponent part of the coefficient C.sub.19 having the mantissa part for which the product of the data D.sub.-19 +D.sub.19 is calculated by the multiplier 23.sub.10 and the exponent part of the coefficient C.sub.17 having the mantissa part for which the product of the data D.sub.-17 +D.sub.17 is calculated by the multiplier 23.sub.9 is 0 (FIG. 3), the product of the data D.sub.-19 +D.sub.19 and the mantissa part of the coefficient C.sub.19 calculated by the multiplier 23.sub.10 is supplied as it is to the adder 24.sub.9. Then at the adder 24.sub.9, a sum of the product of the data D.sub.-19 +D.sub.19 and the mantissa part of the coefficient C.sub.19 supplied from the multiplier 23.sub.10 and the product of the data D.sub.-17 +D.sub.17 and the mantissa of the coefficient C.sub.17 supplied from the multiplier 23.sub.9 is calculated, and the sum thus calculated is outputted to the shifter 25.sub.6.

Since the exponent part difference of the coefficient C.sub.17 having the mantissa part for which the product of the data D.sub.-17 +D.sub.17 is calculated by the multiplier 23.sub.9 is 1, that is, the difference between the exponent part of the coefficient C.sub.17 having the mantissa part for which the product of the data D.sub.-17 +D.sub.17 is calculated by the multiplier 23.sub.9 and the exponent part of the coefficient C.sub.15 having the mantissa part for which the product of the data D.sub.-15 +D.sub.15 is calculated by the multiplier 23.sub.8 is 1 (FIG. 3), the value outputted from the adder 24.sub.9 is shifted down by one bit and then supplied to the adder 24.sub.8. Then at the adder 24.sub.8, a sum of the output of the shifter 25.sub.6 and the output of the multiplier 23.sub.8 is calculated.

Since the exponent part difference of the coefficient C.sub.15 having the mantissa part for which the product of the data D.sub.-15 +D.sub.15 is calculated by the multiplier 23.sub.8 is 1 (FIG. 3), the output of the multiplier 23.sub.8 is supplied as it is to the adder 24.sub.7, and the sum of the output of the adder 24.sub.8 and the output of the multiplier 23.sub.7 is calculated by the adder 24.sub.7.

Similarly, the output of the adder 24.sub.7 is shifted down by one bit by the shifter 25.sub.5, and the sum of the output of the shifter 25.sub.5 and the output of the multiplier 23.sub.6 is calculated by the adder 24.sub.6 ; the sum of the output of the adder 24.sub.6 and the output of the multiplier 23.sub.5 is calculated by the adder 24.sub.5 ; the output of the adder 24.sub.5 is shifted down by one bit by the shifter 25.sub.4, and the sum of the output of the shifter 25.sub.4 and the multiplier 23.sub.4 is calculated by the adder 24.sub.4 ; the output of the adder 24.sub.4 is shifted down by one bit by the shifter 25.sub.3, and the sum of the output of the shifter 25.sub.3 and the output of the multiplier 23.sub.3 is calculated by the adder 24.sub.3 ; the output of the adder 24.sub.3 is shifted down by one bit by the shifter 25.sub.2, and the sum of the output of the shifter 25.sub.2 and the output of the multiplier 23.sub.2 is calculated by the adder 24.sub.2 ; and the output of the adder 24.sub.2 is shifted down by one bit by the shifter 25.sub.1, and the sum of the output of the shifter 25.sub.1 and the output of the multiplier 23.sub.1 is calculated by the adder 24.sub.1.

In this manner, a result of the calculation of a sum of products, which is an odd-numbered sample of the filter output, that is, C.sub.1 (D.sub.-1 + D.sub.1) + C.sub.3 (D.sub.-3 - D.sub.3) + C.sub.5 (.sub.-5 + D.sub.5) + C.sub.7 (D.sub.-7 + D.sub.7) + C.sub.9 (D.sub.-9 + D.sub.9) + C.sub.11 (D.sub.-11 + D.sub.11) + C.sub.13 (D.sub.-13 + D.sub.13) + C.sub.15 (D.sub.-15) + C.sub.17 (D.sub.-17 + D.sub.17) + C.sub.19 (D.sub.-19 + D.sub.19), is outputted from the adder 241.

Further, data latched in the period of 1/fs by the register 21.sub.11 is latched in the period of 1/2fs by the register 26, and the value latched in the register 26 and the output of the adder 24.sub.1 are alternately selected by the switch 27. Consequently, a twofold oversampled filter output can be obtained.

Referring now to FIG. 10, there is shown a digital low-pass filter to which an apparatus for calculating a sum of products according to the present invention is applied. The present digital low-pass filter is a digital filter of the interpolation type of order 39 which can twofold oversample an input digital signal to produce a filter output, similarly as in the digital low-pass filters described hereinabove with reference to FIGS. 1 and 9. Also the present digital low-pass filter is designed so that the impulse response thereof presents such a waveform as shown in FIG. 2.

An interface (I/O) 31 controls inputs and outputs of data from and to the outside. A data memory 32 stores therein data D.sub.n received from the interface 31 by way of a data bus 41. A coefficient memory 33 has the mantissa parts and exponent part differences of the filter coefficients C.sub.n (FIG. 3) Similarly as in the digital low-pass filter of FIG. 1.

A register (AReg) 34 latches the output of an arithmetic and logic unit (ALU) 36. Another register (BReg) 35.latches data D.sub.n stored in the data memory 32. A further register (xReg) 37 latches latched data of the register 35 by way of the data bus 41. A still further register (yReg) 40 latches the mantissa part of a coefficient C.sub.n stored in the coefficient memory 33. A multiplier (MPY) 38 calculates the product of data latched in the register 37 and data latched in the register 38. A yet further register (pReg) 39 latches the product of latched data of the register 37 and latched data of the register 38 outputted from the multiplier 38.

The arithmetic and logic unit 36 executes addition and one-bit shifting of input data. Further, the arithmetic and logic unit 36 outputs 0 in order to initialize the registers 34, 35, 37, 39 and 40 to zero.

Referring now to FIG. 11, there is illustrated operation of the digital low-pass filter shown in FIG. 10. First at step S1, data for one frame, that is, D.sub.-19, D.sub.-17, D.sub.-15, D.sub.-13, D.sub.-11, D.sub.-9, D.sub.-7, D.sub.-5, D.sub.-3, D.sub.-1, D.sub.1, D.sub.3, D.sub.5, D.sub.7, D.sub.9, D.sub.11, D.sub.13, D.sub.15, D.sub.17 and D.sub.19, are fetched from the interface 31 and stored into the data memory 32 by way of the data bus 41. Further at step 1, the register 34 is cleared in response to "0" outputted from the arithmetic and logic unit 36, and the variable n which corresponds to the suffix to a filter coefficient is set to one half the order number of the digital low-pass filter, that is, 19 (n=19). Then, the control sequence advances to step S2.

At step S2, the data D.sub.-n is latched by the register 35. Then at step S3, the sum of the data D.sub.-n latched in the register 35 and the data D.sub.n stored in the data memory 32, that is, D.sub.-n +D.sub.n, is calculated by the arithmetic and logic unit 36, and the sum is latched by the register 35. Then at step S4, the data D.sub.-n +D.sub.n latched in the register 35 is latched by the register 37 and the mantissa part of the coefficient C.sub.n stored in the coefficient memory 32 is latched by the register 40.

At step S5, the product of the data D.sub.-n +D.sub.n latched in the register 37 and the mantissa part of the coefficient C.sub.n latched in the register 40, that is, the mantissa part of the coefficient C.sub.n .times.(D.sub.-n +D.sub.n), is calculated by the multiplier 38 and latched by the register 39.

At step S6, the sum of the data (the mantissa part of the coefficient C.sub.n .times.(D.sub.-n +D.sub.n)) latched in the register 39 and the data latched in the register 34 is calculated by the arithmetic and logic unit 36 and then latched by the register 34 again. In other words, at step S6, a cumulative sum value,of the data (coefficient C.sub.n .times.(D.sub.-n +D.sub.n)) latched in the register 39 is latched by the register 34.

After the cumulative sum value of the data (coefficient C.sub.n .times.(D.sub.-n +D.sub.n)) latched in the register 39 is latched by the register 34 at step S6, it is judged at step S7 whether or not the exponent part difference (FIG. 3) of the coefficient C.sub.n having the mantissa part latched in the register 40 is equal to 1. If the exponent part difference (FIG. 3) of the coefficient C.sub.n having the mantissa part latched in the register 40 is not equal to 1, then the control sequence advances to step S9 skipping step S8.

On the other hand, if the exponent part difference (FIG. 3) of the coefficient C.sub.n having the mantissa part latched in the register 40 is equal to 1, then the control sequence advances to step S8, at which the cumulative sum value of the data (coefficient C.sub.n .times.(D.sub.-n +D.sub.n) latched in the register 34 is multiplied by 1/2, that is, the cumulative sum value of the data (coefficient C.sub.n .times.(D.sub.-n +D.sub.n) latched in the register 34 is shifted down by one bit in order to effect adjustment in column with data to be cumulatively added subsequently at step S6, that is, the coefficient (C.sub.n-2 .times.(D.sub.-(n-2) +D.sub.n-2)), whereafter the control sequence advances to step S9.

At step S9, the variable n is decremented by 2, and then at step S10, it is judged whether or not the variable n is in the negative. If it is judged that the variable is not in the negative, that is, when calculation of a sum of products of the data for one frame is not completed, the control sequence returns to step S2 so that the processing from step S2 to step S10 will thereafter be repeated until it is judged at step S10 that the variable n is in the negative.

When it is judged at step S10 that the variable is in the negative, that is, when calculation of a sum of products of the data for one frame is completed, the control sequence advances to step S11, at which either the data D.sub.1 is supplied at an even-numbered sample (EVEN output) of the filter output or the cumulative sum value latched in the register 34 is supplied at an odd-numbered sample (ODD output) of the filter output to the interface 31.

It is to be noted that the flow chart of FIG. 11 relates to the filter output of data for one frame and the processing steps S1 to S11 described above are repeated until the data inputted to the interface 31 are all used up.

While several applications of the apparatus for calculating a sum of products according to the present invention to a digital low-pass filter are described so far, the apparatus for calculating a sum of products and the method of calculating a sum Of products according to the present invention can be applied to popular digital filters, digital equalizers, digital signal processors and so forth as well as to discrete cosine transform (DCT), fast Fourier transform (FFT) and so forth.

Having now fully described the invention, it will be apparent to one of ordinary skill in the art that many changes and modifications can be made thereto without departing from the spirit and scope of the invention as set forth herein.